[AMDGPU] Have a subtarget feature to control use of real True16 instructions.

[kosarev]

Summary

Real True16 instructions are as they are defined in the ISA. Fake True16
instructions are identical to real ones except that they take 32-bit
registers as operands and always use their low halves.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

174

Can implement this by just clearing the hasTrue16BitInsts feature in the constructor

174

Actually just using -mattr=-true16-whatever should work just as well. Do we really need a dedicated flag?

[kosarev]

Rework the command-line option into a SubtargetFeature.

[kosarev]

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

174

Done. HasTrue16BitInsts should stay raised for the existing tests to pass.

[kosarev]

Update the commit message.

[kosarev]

Rename the feature to reflect the fact that it's not just about codegen
anymore, but also assembling and disassembling.

[Joe_Nash]

LGTM

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

public:
   }
 
   bool has16BitInsts() const {
     return Has16BitInsts;
   }
 
   bool hasTrue16BitInsts() const { return HasTrue16BitInsts; }
 
+  // TODO: Remove and use hasTrue16BitInsts() instead once True16 is
+  // fully supported.
+  bool useTrue16BitInsts() const;
+
   bool hasMadMixInsts() const {
     return HasMadMixInsts;
   }
 
   bool hasMadMacF32Insts() const {
     return HasMadMacF32Insts || !isGCN();
   }
 

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

 static cl::opt<bool> UseAA("amdgpu-use-aa-in-codegen",
                            cl::desc("Enable the use of AA during codegen."),
                            cl::init(true));
 
 static cl::opt<unsigned> NSAThreshold("amdgpu-nsa-threshold",
                                       cl::desc("Number of addresses from which to enable MIMG NSA."),
                                       cl::init(3), cl::Hidden);
 
+static cl::opt<bool> EnableTrue16Codegen("amdgpu-true16",
+                                         cl::desc("Use true 16-bit registers"),
+                                         cl::init(false), cl::ReallyHidden);
+
 GCNSubtarget::~GCNSubtarget() = default;
 
 GCNSubtarget &
 GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
                                               StringRef GPU, StringRef FS) {
   // Determine default and user-specified characteristics
   //
   // We want to be able to turn these off, but making this a subtarget feature
GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
   LLVM_DEBUG(dbgs() << "sramecc setting for subtarget: "
                     << TargetID.getSramEccSetting() << '\n');
 
   return *this;
 }
 
 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT) : TargetTriple(TT) {}
 
+bool AMDGPUSubtarget::useTrue16BitInsts() const {
+  return hasTrue16BitInsts() && EnableTrue16Codegen;
+}
+
 GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
                            const GCNTargetMachine &TM)
     : // clang-format off
     AMDGPUGenSubtargetInfo(TT, GPU, /*TuneCPU*/ GPU, FS),
     AMDGPUSubtarget(TT),
     TargetTriple(TT),
     TargetID(*this),
     InstrItins(getInstrItineraryForCPU(GPU)),

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

SITargetLowering::SITargetLowering(const TargetMachine &TM,
 
   addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
   addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));
 
   addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
   addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));
 
   if (Subtarget->has16BitInsts()) {
+    if (Subtarget->useTrue16BitInsts()) {
+      addRegisterClass(MVT::i16, &AMDGPU::VGPR_16RegClass);
+      addRegisterClass(MVT::f16, &AMDGPU::VGPR_16RegClass);
+    } else {
       addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
       addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
+    }
 
     // Unless there are also VOP3P operations, not operations are really legal.
     addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
     addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
     addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
     addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
     addRegisterClass(MVT::v8i16, &AMDGPU::SGPR_128RegClass);
     addRegisterClass(MVT::v8f16, &AMDGPU::SGPR_128RegClass);