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Differential D156106

[AMDGPU] Test codegen'ing True16 additions.
ClosedPublic

Authored by kosarev on Jul 24 2023, 4:14 AM.

Details

Reviewers
arsenm
rampitec
Joe_Nash
foad
Commits
rGbe8b559956b1: [AMDGPU] Test codegen'ing True16 additions.
Summary

The GlobalISel part is to be addressed later.

Diff Detail

Event Timeline

kosarev created this revision.Jul 24 2023, 4:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 24 2023, 4:14 AM
Herald added subscribers: StephenFan, kerbowa, tpr and 4 others. · View Herald Transcript
kosarev requested review of this revision.Jul 24 2023, 4:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 24 2023, 4:14 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
kosarev added a parent revision: D156105: [AMDGPU][True16] Support emitting copies between different register sizes..Jul 24 2023, 4:24 AM
Harbormaster completed remote builds in B247622: Diff 543470.Jul 24 2023, 5:49 AM
rampitec added a comment.Jul 24 2023, 10:55 AM

You have 'llc: Unknown command line argument '-amdgpu-true16'. Try: '/var/lib/buildkite-agent/builds/llvm-project/build/bin/llc --help' error in testing.

kosarev updated this revision to Diff 543649.Jul 24 2023, 11:06 AM

Enable true True16 codegen with -mattr.

kosarev added a comment.Jul 24 2023, 11:46 AM

You have 'llc: Unknown command line argument '-amdgpu-true16'. Try: '/var/lib/buildkite-agent/builds/llvm-project/build/bin/llc --help' error in testing.

Must be because D156100 is not submitted yet?

Harbormaster completed remote builds in B247754: Diff 543649.Jul 24 2023, 8:26 PM
kosarev updated this revision to Diff 545123.Jul 28 2023, 6:04 AM

Rebase on top of D156529.

Harbormaster completed remote builds in B248822: Diff 545123.Jul 28 2023, 6:05 AM
kosarev edited parent revisions, added: D156529: [AMDGPU][True16] Pre-commit addition tests.; removed: D156105: [AMDGPU][True16] Support emitting copies between different register sizes..Jul 28 2023, 11:52 AM
kosarev updated this revision to Diff 545986.Aug 1 2023, 2:56 AM

Update to use the new feature name.

Harbormaster completed remote builds in B249437: Diff 545986.Aug 1 2023, 2:57 AM
kosarev added a child revision: D156939: [AMDGPU][True16] Support disassembling .h registers..Aug 2 2023, 1:57 PM
kosarev added a comment.Aug 22 2023, 4:37 AM

Ping.

Joe_Nash accepted this revision.Aug 22 2023, 6:33 AM

LGTM

This revision is now accepted and ready to land.Aug 22 2023, 6:33 AM
This revision was landed with ongoing or failed builds.Sep 27 2023, 3:11 AM
Closed by commit rGbe8b559956b1: [AMDGPU] Test codegen'ing True16 additions. (authored by kosarev). · Explain Why
This revision was automatically updated to reflect the committed changes.
kosarev added a commit: rGbe8b559956b1: [AMDGPU] Test codegen'ing True16 additions..

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
14 lines

Diff 557395

llvm/test/CodeGen/AMDGPU/fadd.f16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=SI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=VI %s ; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11 %s ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11 %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
define amdgpu_kernel void @fadd_f16( define amdgpu_kernel void @fadd_f16(
; SI-LABEL: fadd_f16: ; SI-LABEL: fadd_f16:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
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; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s6, s10 ; GFX11-NEXT: s_mov_b32 s6, s10
; GFX11-NEXT: s_mov_b32 s7, s11 ; GFX11-NEXT: s_mov_b32 s7, s11
; GFX11-NEXT: buffer_load_u16 v0, off, s[4:7], 0 glc dlc ; GFX11-NEXT: buffer_load_u16 v0, off, s[4:7], 0 glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_load_u16 v1, off, s[0:3], 0 glc dlc ; GFX11-NEXT: buffer_load_u16 v1, off, s[0:3], 0 glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_f16_e32 v0, v0, v1 ; GFX11-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
; GFX11-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-NEXT: buffer_store_b16 v0, off, s[8:11], 0
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
; ;
; GFX11-FAKE16-LABEL: fadd_f16: ; GFX11-FAKE16-LABEL: fadd_f16:
; GFX11-FAKE16: ; %bb.0: ; %entry ; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: s_clause 0x1
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; GFX11-NEXT: s_mov_b32 s4, s0 ; GFX11-NEXT: s_mov_b32 s4, s0
; GFX11-NEXT: s_mov_b32 s5, s1 ; GFX11-NEXT: s_mov_b32 s5, s1
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s6 ; GFX11-NEXT: s_mov_b32 s2, s6
; GFX11-NEXT: s_mov_b32 s3, s7 ; GFX11-NEXT: s_mov_b32 s3, s7
; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0 ; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_f16_e32 v0, 1.0, v0 ; GFX11-NEXT: v_mov_b16_e32 v0.h, 0x3c00
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0 ; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
; ;
; GFX11-FAKE16-LABEL: fadd_f16_imm_a: ; GFX11-FAKE16-LABEL: fadd_f16_imm_a:
; GFX11-FAKE16: ; %bb.0: ; %entry ; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX11-NEXT: s_mov_b32 s4, s0 ; GFX11-NEXT: s_mov_b32 s4, s0
; GFX11-NEXT: s_mov_b32 s5, s1 ; GFX11-NEXT: s_mov_b32 s5, s1
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s6 ; GFX11-NEXT: s_mov_b32 s2, s6
; GFX11-NEXT: s_mov_b32 s3, s7 ; GFX11-NEXT: s_mov_b32 s3, s7
; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0 ; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_f16_e32 v0, 2.0, v0 ; GFX11-NEXT: v_mov_b16_e32 v0.h, 0x4000
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0 ; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
; ;
; GFX11-FAKE16-LABEL: fadd_f16_imm_b: ; GFX11-FAKE16-LABEL: fadd_f16_imm_b:
; GFX11-FAKE16: ; %bb.0: ; %entry ; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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