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[AMDGPU] Switch to using real True16 operands.
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Authored by kosarev on Jul 24 2023, 4:08 AM.

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Summary

The DPP source and e64 destination operands remain unchanged for now.

Diff Detail

Event Timeline

kosarev created this revision.Jul 24 2023, 4:08 AM
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kosarev requested review of this revision.Jul 24 2023, 4:08 AM
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Joe_Nash added inline comments.Jul 27 2023, 1:56 PM
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
60 ↗(On Diff #543468)

Why has only the dst changed to a 16 bit register?

Joe_Nash added a comment.EditedJul 28 2023, 6:46 AM

After this patch, it seems the disassembly output for 16-bit instructions will be changed. We we be in a state where the ones using true16 print .l/.h suffixes and the other ones don't. Is that a problem for users?

kosarev added inline comments.Jul 28 2023, 11:50 AM
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
60 ↗(On Diff #543468)

The DPP source operand fields in VOPProfile_True16 still refer to the Fake16 operands.

Joe_Nash added inline comments.Jul 31 2023, 2:04 PM
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
60 ↗(On Diff #543468)

The disassembler changes in this patch include:

  • Some non-complete subset of the total number of 16-bit instructions are converted to True16, such that when disassembled they will have .h and .l suffixes on their operands. The other instructions remain unchanged. This seems fairly uncontroversial to me. It looks like there is no disassembly coverage of the .h operands; can some of the downstream tests be added to this patch?
  • Some operands of instructions have been converted to True16, while others have not. This results in disassembler output where some operands of the instruction explicitly have the .lo suffix, where some do not have that suffix but are implicitly lo. I think there is some potential for confusion in the users here, so all the operands should be transitioned simultaneously.
kosarev updated this revision to Diff 545981.Aug 1 2023, 2:40 AM

Rebase on top of the latest changes in the patches up the chain.

kosarev edited the summary of this revision. (Show Details)Aug 1 2023, 2:42 AM

Disassembler tests went to D156782.

kosarev updated this revision to Diff 546595.Aug 2 2023, 1:51 PM

Update to add bits necessary for disassembling .h registers.

This revision is now accepted and ready to land.Aug 22 2023, 7:19 AM
This revision was automatically updated to reflect the committed changes.
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir