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Differential D156985

[AMDGPU] Remove the support for non-True16 copies between different register sizes.
ClosedPublic

Authored by kosarev on Aug 3 2023, 3:44 AM.

Details

Reviewers
arsenm
rampitec
Joe_Nash
foad
Commits
rG287f6cdd17cd: [AMDGPU] Remove the support for non-True16 copies between different register…

Diff Detail

Event Timeline

kosarev created this revision.Aug 3 2023, 3:44 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 3 2023, 3:44 AM
Herald added subscribers: StephenFan, kerbowa, hiraditya and 5 others. · View Herald Transcript
kosarev requested review of this revision.Aug 3 2023, 3:44 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 3 2023, 3:44 AM
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Harbormaster completed remote builds in B250016: Diff 546791.Aug 3 2023, 3:45 AM
kosarev added a parent revision: D156105: [AMDGPU][True16] Support emitting copies between different register sizes..Aug 3 2023, 3:45 AM
kosarev added a child revision: D156529: [AMDGPU][True16] Pre-commit addition tests..
foad accepted this revision.Aug 3 2023, 3:49 AM

This can be committed with no dependencies, right? If so it LGTM.

This revision is now accepted and ready to land.Aug 3 2023, 3:49 AM
Joe_Nash added a comment.Aug 3 2023, 6:54 AM
In D156985#4557036, @foad wrote:

This can be committed with no dependencies, right? If so it LGTM.

Yes, that is my understanding. It could even be modified to be on tip of tree instead of in the stack.

Joe_Nash accepted this revision.Aug 17 2023, 11:55 AM

LGTM

This revision was landed with ongoing or failed builds.Sep 26 2023, 6:46 AM
Closed by commit rG287f6cdd17cd: [AMDGPU] Remove the support for non-True16 copies between different register… (authored by kosarev). · Explain Why
This revision was automatically updated to reflect the committed changes.
kosarev added a commit: rG287f6cdd17cd: [AMDGPU] Remove the support for non-True16 copies between different register….

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
17 lines
test/
CodeGen/
AMDGPU/

Diff 557359

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 727 Lines • ▼ Show 20 Linesvoid SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg); const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);
unsigned SrcSize = RI.getRegSizeInBits(*SrcRC); unsigned SrcSize = RI.getRegSizeInBits(*SrcRC);
// The rest of copyPhysReg assumes Src and Dst size are the same size. // The rest of copyPhysReg assumes Src and Dst size are the same size.
// TODO-GFX11_16BIT If all true 16 bit instruction patterns are completed can // TODO-GFX11_16BIT If all true 16 bit instruction patterns are completed can
// we remove Fix16BitCopies and this code block? // we remove Fix16BitCopies and this code block?
if (Fix16BitCopies) { if (Fix16BitCopies) {
if (((Size == 16) != (SrcSize == 16))) { if (((Size == 16) != (SrcSize == 16))) {
if (ST.hasTrue16BitInsts()) {
// Non-VGPR Src and Dst will later be expanded back to 32 bits. // Non-VGPR Src and Dst will later be expanded back to 32 bits.
assert(ST.hasTrue16BitInsts());
MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg; MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16); MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
RegToFix = SubReg; RegToFix = SubReg;
} else {
MCRegister &RegToFix = (Size == 16) ? DestReg : SrcReg;
MCRegister Super = RI.get32BitRegister(RegToFix);
assert(RI.getSubReg(Super, AMDGPU::lo16) == RegToFix ||
RI.getSubReg(Super, AMDGPU::hi16) == RegToFix);
RegToFix = Super;
}
if (DestReg == SrcReg) { if (DestReg == SrcReg) {
// Identity copy. Insert empty bundle since ExpandPostRA expects an // Identity copy. Insert empty bundle since ExpandPostRA expects an
// instruction here. // instruction here.
BuildMI(MBB, MI, DL, get(AMDGPU::BUNDLE)); BuildMI(MBB, MI, DL, get(AMDGPU::BUNDLE));
return; return;
} }
RC = RI.getPhysRegBaseClass(DestReg); RC = RI.getPhysRegBaseClass(DestReg);
▲ Show 20 Lines • Show All 8,452 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir

  • This file was deleted.
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass postrapseudos -amdgpu-fix-16-bit-physreg-copies -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: lo16_to_v32
# GCN: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
name: lo16_to_v32
tracksRegLiveness: true
body: |
bb.0:
$vgpr0 = IMPLICIT_DEF
$vgpr1_lo16 = COPY $vgpr0
S_ENDPGM 0
...
# GCN-LABEL: name: v32_to_lo16
# GCN: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
name: v32_to_lo16
tracksRegLiveness: true
body: |
bb.0:
$vgpr0 = IMPLICIT_DEF
$vgpr1 = COPY $vgpr0_lo16
S_ENDPGM 0
...
# GCN-LABEL: name: samereg
# GCN: $vgpr0 = IMPLICIT_DEF
# GCN-NEXT: BUNDLE
# GCN-NEXT: S_ENDPGM
name: samereg
tracksRegLiveness: true
body: |
bb.0:
$vgpr0 = IMPLICIT_DEF
$vgpr0 = COPY $vgpr0_lo16
S_ENDPGM 0
...
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp