[X86] Add PBNDKB instruction.

[FreddyYe]

Summary

For more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

[RKSimon]

Is it worth adding an error test to (to x86_errors.s or whatever) if PBNDKB gets used on 32-bit?

[pengfei]

llvm/lib/Target/X86/X86InstrSystem.td

433

It defs RAX instead of use.

[skan]

llvm/lib/Target/X86/X86InstrSystem.td

434

Doesn't this instruction affect EFLAGS?

[FreddyYe]

In D155142#4496720, @RKSimon wrote:

Is it worth adding an error test to (to x86_errors.s or whatever) if PBNDKB gets used on 32-bit?

It seems to me we never did before, but not a bad idea to do so.

[FreddyYe]

Address comments and add test in x86_error.s

llvm/lib/Target/X86/X86InstrSystem.td

433

Good catch!

434

Good catch. Added def EFLAGS.

[skan]

llvm/test/MC/Disassembler/X86/pbndkb.txt

3

Remove -x86-asm-syntax=intel

[skan]

llvm/lib/Target/X86/X86InstrSystem.td

432–433

I don't know if it would make a difference, but according to SPEC, should we change RAX to EAX?

[FreddyYe]

Address comment.

llvm/lib/Target/X86/X86InstrSystem.td

432–433

This instruction is 64 bit only valid. So I think it's a typo in SPEC's 'Description' section. And I notice that in 'Operation' section, it used RAX instead.

[pengfei]

LGTM.

[skan]

LGTM

llvm/docs/ReleaseNotes.rst

 Changes to the Windows Target
 -----------------------------
 
 Changes to the X86 Backend
 --------------------------
 
 * ``__builtin_unpredictable`` (unpredictable metadata in LLVM IR), is handled by X86 Backend.
   ``X86CmovConversion`` pass now respects this builtin and does not convert CMOVs to branches.
+* Add support for the ``PBNDKB`` instruction.
 
 
 Changes to the OCaml bindings
 -----------------------------
 
 Changes to the Python bindings
 ------------------------------
 

llvm/lib/Target/X86/X86InstrSystem.td

 // Specialized register support
 let SchedRW = [WriteSystem] in {
 let Uses = [EAX, ECX, EDX] in
 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
 let Uses = [EAX, ECX, EDX] in
 def WRMSRNS : I<0x01, MRM_C6, (outs), (ins), "wrmsrns", []>, PS;
 let Defs = [EAX, EDX], Uses = [ECX] in
 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
-
+let Defs = [RAX, EFLAGS], Uses = [RBX, RCX], Predicates = [In64BitMode] in
+def PBNDKB : I<0x01, MRM_C7, (outs), (ins), "pbndkb", []>, PS;
 let Uses = [RSI, RDI, RCX], Predicates = [In64BitMode] in {
 def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, XS;
 def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, XD;
 }
 
 let Defs = [RAX, RDX], Uses = [ECX] in
 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
 
 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),

llvm/test/MC/Disassembler/X86/pbndkb.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s
+
+# CHECK: pbndkb
+0x0f,0x01,0xc7
+

llvm/test/MC/X86/pbndkb.s

+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: pbndkb
+// CHECK: encoding: [0x0f,0x01,0xc7]
+          pbndkb
+

llvm/test/MC/X86/x86_errors.s

 
 // 32: error: unsupported instruction
 // 64: error: unsupported instruction
 {evex} vmovdqu %xmm0, %xmm0
 
 // 32: 12: error: immediate must be an integer in range [0, 15]
 // 64: 12: error: immediate must be an integer in range [0, 15]
 vpermil2pd $16, %xmm3, %xmm5, %xmm1, %xmm2
+
+// 32: error: instruction requires: 64-bit mode
+pbndkb