[Mips] Remove unused TableGen classes and multiclasses.

[kosarev]

Summary

And warn on them from now on.

[sdardis]

LGTM. After checking the classes removed, they fall into the cases of classes that were added for completeness' sake or were never expanded on. The microMIPS64R6 class was missed during the removal of support for that ISA variant.

llvm/lib/Target/Mips/CMakeLists.txt

 add_llvm_component_group(Mips HAS_JIT)
 
 set(LLVM_TARGET_DEFINITIONS Mips.td)
 
 tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel -warn-on-unused-entities)
 tablegen(LLVM MipsGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
               -combiners="MipsPostLegalizerCombinerHelper")
 tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)

llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td

class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
   let Inst{25-21} = ft;
   let Inst{20-16} = fs;
   let Inst{15} = 0;
   let Inst{14-13} = fmt;
   let Inst{12-6} = funct;
   let Inst{5-0} = 0b111011;
 }
 
-class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  bits<5> ft;
-  bits<5> fs;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010101;
-  let Inst{25-21} = ft;
-  let Inst{20-16} = fs;
-  let Inst{15}    = 0;
-  let Inst{14-13} = fmt;
-  let Inst{12-6}  = funct;
-  let Inst{5-0}   = 0b111011;
-}
-
 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
     : MMR6Arch<instr_asm>, MipsR6Inst {
   bits<5> ft;
   bits<5> fs;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b010101;

llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
 class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">;
 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
-class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
-class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
class MTC1_MMR6_DESC_BASE<
   dag InOperandList = (ins SrcRC:$rt);
   dag OutOperandList = (outs DstRC:$fs);
   string AsmString = !strconcat(opstr, "\t$rt, $fs");
   list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
   Format f = FrmFR;
   InstrItinClass Itinerary = Itin;
   string BaseOpcode = opstr;
 }
-class MTC1_64_MMR6_DESC_BASE<
-      string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
-      InstrItinClass Itin = NoItinerary> : MipsR6Inst {
-  dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
-  dag OutOperandList = (outs DstRC:$fs);
-  string AsmString = !strconcat(opstr, "\t$rt, $fs");
-  list<dag> Pattern = [];
-  Format f = FrmFR;
-  InstrItinClass Itinerary = Itin;
-  string BaseOpcode = opstr;
-  // $fs_in is part of a white lie to work around a widespread bug in the FPU
-  // implementation. See expandBuildPairF64 for details.
-  let Constraints = "$fs = $fs_in";
-}
 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
                          RegisterOperand SrcRC, InstrItinClass Itin> {
   dag InOperandList = (ins SrcRC:$rt);
   dag OutOperandList = (outs DstRC:$impl);
   string AsmString = !strconcat(opstr, "\t$rt, $impl");
   list<dag> Pattern = [];
   Format f = FrmFR;
   string BaseOpcode = opstr;

 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
                                                     FGR32Opnd, II_TRUNC>;
 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
                                                     FGR64Opnd, II_TRUNC>;
 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
                                                     FGR32Opnd, II_TRUNC>;
 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
                                                     FGR64Opnd, II_TRUNC>;
-class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
-                                                 II_SQRT_S, fsqrt>;
-class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd,
-                                                AFGR64Opnd, II_SQRT_D, fsqrt>;
 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
                                                    FGR32Opnd, II_ROUND>;
 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
                                                    FGR64Opnd, II_ROUND>;
 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
                                                    FGR32Opnd, II_ROUND>;
 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
                                                    FGR64Opnd, II_ROUND>;

llvm/lib/Target/Mips/Mips16InstrFormats.td

class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
   let subfunct = _subfunct;
 
   let Inst{10-8} = rx;
   let Inst{7-5} = subfunct;
   let Inst{4-0}   = funct;
 }
 
 //
-// just used for breakpoint (hardware and software) instructions.
-//
-class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
-           list<dag> pattern, InstrItinClass itin>:
-  MipsInst16<outs, ins, asmstr, pattern, itin>
-{
-  bits<6>  _code;  // code is a keyword in tablegen
-  bits<5>  funct;
-
-  let Opcode = 0b11101; // RR
-  let funct  = _funct;
-
-  let Inst{10-5} = _code;
-  let Inst{4-0}   = funct;
-}
-
-//
 // J(AL)R(C) subformat
 //
 class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
                   dag outs, dag ins, string asmstr,
                   list<dag> pattern, InstrItinClass itin>:
   MipsInst16<outs, ins, asmstr, pattern, itin>
 {
   bits<3>  rx;
class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
   let Inst{10-8} = rx;
   let Inst{7} = nd;
   let Inst{6} = l;
   let Inst{5} = ra;
   let Inst{4-0} = 0;
 }
 
 //===----------------------------------------------------------------------===//
-// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
-//===----------------------------------------------------------------------===//
-
-class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
-             list<dag> pattern, InstrItinClass itin>:
-  MipsInst16<outs, ins, asmstr, pattern, itin>
-{
-  bits<3>  rx;
-  bits<3>  ry;
-  bits<5>  imm5;
-
-  let Opcode = op;
-
-
-  let Inst{10-8} = rx;
-  let Inst{7-5} = ry;
-  let Inst{4-0}   = imm5;
-}
-
-//===----------------------------------------------------------------------===//
 // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
 //===----------------------------------------------------------------------===//
 
 class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
              list<dag> pattern, InstrItinClass itin>:
   MipsInst16<outs, ins, asmstr, pattern, itin>
 {
   bits<3>  rx;
   bits<3>  ry;
   bits<3>  rz;
   bits<2>  f;
 
   let Opcode = 0b11100;
   let f  = _f;
 
   let Inst{10-8} = rx;
   let Inst{7-5} = ry;
   let Inst{4-2} = rz;
   let Inst{1-0}   = f;
 }
 
 //===----------------------------------------------------------------------===//
-// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
-//===----------------------------------------------------------------------===//
-
-class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
-               list<dag> pattern, InstrItinClass itin>:
-  MipsInst16<outs, ins, asmstr, pattern, itin>
-{
-  bits<3>  rx;
-  bits<3>  ry;
-  bits<1>  f;
-  bits<4>  imm4;
-
-  let Opcode = 0b01000;
-  let  f = _f;
-
-  let Inst{10-8} = rx;
-  let Inst{7-5} = ry;
-  let Inst{4} = f;
-  let Inst{3-0}   = imm4;
-}
-
-//===----------------------------------------------------------------------===//
-// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
-//===----------------------------------------------------------------------===//
-
-class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
-               list<dag> pattern, InstrItinClass itin>:
-  MipsInst16<outs, ins, asmstr, pattern, itin>
-{
-  bits<3>  rx;
-  bits<3>  ry;
-  bits<3>  sa;
-  bits<2>  f;
-
-  let Opcode = 0b00110;
-  let f  = _f;
-
-  let Inst{10-8} = rx;
-  let Inst{7-5} = ry;
-  let Inst{4-2} = sa;
-  let Inst{1-0}   = f;
-}
-
-//===----------------------------------------------------------------------===//
 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
 //===----------------------------------------------------------------------===//
 
 class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
             list<dag> pattern, InstrItinClass itin>:
   MipsInst16<outs, ins, asmstr, pattern, itin>
 {
   bits<3>  func;
class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
   let Inst{20-16} = imm16{15-11};
   let Inst{15-11} = eop;
   let Inst{10-5} = 0;
   let Inst{4-0} = imm16{4-0};
 
 }
 
 //===----------------------------------------------------------------------===//
-// Format ASMACRO instruction class in Mips16 :
-//    <EXTEND|select|p4|p3|RRR|p2|p1|p0>
-//===----------------------------------------------------------------------===//
-
-class FASMACRO16<dag outs, dag ins, string asmstr,
-                 list<dag> pattern, InstrItinClass itin>:
-  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
-{
-  bits<3> select;
-  bits<3> p4;
-  bits<5> p3;
-  bits<5> RRR = 0b11100;
-  bits<3> p2;
-  bits<3> p1;
-  bits<5> p0;
-
-
-  let Inst{26-24} = select;
-  let Inst{23-21} = p4;
-  let Inst{20-16} = p3;
-  let Inst{15-11} = RRR;
-  let Inst{10-8} = p2;
-  let Inst{7-5} = p1;
-  let Inst{4-0} = p0;
-
-}
-
-
-//===----------------------------------------------------------------------===//
 // Format EXT-RI instruction class in Mips16 :
 //    <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
 //===----------------------------------------------------------------------===//
 
 class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
                 list<dag> pattern, InstrItinClass itin>:
   MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
 {
class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
   let Inst{26-21} = imm16{10-5};
   let Inst{20-16} = imm16{15-11};
   let Inst{15-11} = I8;
   let Inst{10-8} = funct;
   let Inst{7-5} = 0;
   let Inst{4-0} = imm16{4-0};
 
 }
-
-//===----------------------------------------------------------------------===//
-// Format EXT-I8_SVRS instruction class in Mips16 :
-//    <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
-//===----------------------------------------------------------------------===//
-
-class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
-                     list<dag> pattern, InstrItinClass itin>:
-  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
-{
-  bits<3> xsregs =0;
-  bits<8> framesize =0;
-  bits<3> aregs =0;
-  bits<5> I8 = 0b01100;
-  bits<3> SVRS = 0b100;
-  bits<1> s;
-  bits<1> ra = 0;
-  bits<1> s0 = 0;
-  bits<1> s1 = 0;
-
-  let s= s_;
-
-  let Inst{26-24} = xsregs;
-  let Inst{23-20} = framesize{7-4};
-  let Inst{19} = 0;
-  let Inst{18-16} = aregs;
-  let Inst{15-11} = I8;
-  let Inst{10-8} = SVRS;
-  let Inst{7} = s;
-  let Inst{6} = ra;
-  let Inst{5} = s0;
-  let Inst{4} = s1;
-  let Inst{3-0} = framesize{3-0};
-
-
-}
-

llvm/lib/Target/Mips/Mips16InstrInfo.td

MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
                !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
   let isCodeGenOnly=1;
 }
 
 //
 // RR-type instruction format
 //
 
-class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
-  FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
-        !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
-}
-
 class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
   FRRBreak16<(outs), (ins), asmstr, [], itin> {
   let Code=0;
 }
 
 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
   FRR16<f, (outs), (ins  CPU16Regs:$rx, CPU16Regs:$ry),
         !strconcat(asmstr, "\t$rx, $ry"), [], itin> {

llvm/lib/Target/Mips/MipsInstrInfo.td

 class ISA_MICROMIPS32R5 {
   list<Predicate> InsnPredicates = [HasMips32r5];
   list<Predicate> EncodingPredicates = [InMicroMips];
 }
 class ISA_MICROMIPS32R6 {
   list<Predicate> InsnPredicates = [HasMips32r6];
   list<Predicate> EncodingPredicates = [InMicroMips];
 }
-class ISA_MICROMIPS64R6 {
-  list<Predicate> InsnPredicates = [HasMips64r6];
-  list<Predicate> EncodingPredicates = [InMicroMips];
-}
 class ISA_MICROMIPS32_NOT_MIPS32R6 {
   list<Predicate> InsnPredicates = [NotMips32r6];
   list<Predicate> EncodingPredicates = [InMicroMips];
 }
 class ASE_EVA { list<Predicate> ASEPredicate = [HasEVA]; }
 
 // The portions of MIPS-III that were also added to MIPS32
 class INSN_MIPS3_32 {

 }
 
 // The portions of MIPS-III that were also added to MIPS32
 class INSN_MIPS3_32R2 {
   list<Predicate> InsnPredicates = [HasMips3_32r2];
   list<Predicate> EncodingPredicates = [HasStdEnc];
 }
 
-// The portions of MIPS-IV that were also added to MIPS32.
-class INSN_MIPS4_32 {
-  list <Predicate> InsnPredicates = [HasMips4_32];
-  list<Predicate> EncodingPredicates = [HasStdEnc];
-}
-
 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
 // MIPS32r6 and MIPS64r6.
 class INSN_MIPS4_32_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
   list<Predicate> EncodingPredicates = [HasStdEnc];
 }
 
 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in

 class NOT_ASE_CNMIPS {
   list<Predicate> ASEPredicate = [NotCnMips];
 }
 
 class ASE_CNMIPSP {
   list<Predicate> ASEPredicate = [HasCnMipsP];
 }
 
-class NOT_ASE_CNMIPSP {
-  list<Predicate> ASEPredicate = [NotCnMipsP];
-}
-
 class ASE_MIPS64_CNMIPS {
   list<Predicate> ASEPredicate = [HasMips64, HasCnMips];
 }
 
 class ASE_MSA {
   list<Predicate> ASEPredicate = [HasMSA];
 }
 

 class ASE_VIRT {
   list <Predicate> ASEPredicate = [HasVirt];
 }
 
 class ASE_GINV {
   list <Predicate> ASEPredicate = [HasGINV];
 }
 
-// Class used for separating microMIPSr6 and microMIPS (r3) instruction.
-// It can be used only on instructions that doesn't inherit PredicateControl.
-class ISA_MICROMIPS_NOT_32R6 : PredicateControl {
-  let InsnPredicates = [NotMips32r6];
-  let EncodingPredicates = [InMicroMips];
-}
-
 class ASE_NOT_DSP {
   list<Predicate> ASEPredicate = [NotDSP];
 }
 
 class MADD4 {
   list<Predicate> AdditionalPredicates = [HasMadd4];
 }
 
class IsCommutable {
   bit isCommutable = 1;
 }
 
 class IsBranch {
   bit isBranch = 1;
   bit isCTI = 1;
 }
 
-class IsReturn {
-  bit isReturn = 1;
-  bit isCTI = 1;
-}
-
-class IsCall {
-  bit isCall = 1;
-  bit isCTI = 1;
-}
-
-class IsTailCall {
-  bit isCall = 1;
-  bit isTerminator = 1;
-  bit isReturn = 1;
-  bit isBarrier = 1;
-  bit hasExtraSrcRegAllocReq = 1;
-  bit isCodeGenOnly = 1;
-  bit isCTI = 1;
-}
-
 class IsAsCheapAsAMove {
   bit isAsCheapAsAMove = 1;
 }
 
 class NeverHasSideEffects {
   bit hasSideEffects = 0;
 }
 

llvm/lib/Target/Mips/MipsMSAInstrInfo.td

 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
                             (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
                             (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
                             (MipsVSHF (vsplati64_splat_d node:$i),
                                       node:$v, node:$v)>;
 
-class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
-                   SDNodeXForm xform = NOOP_SDNodeXForm>
-  : PatLeaf<frag, pred, xform> {
-  Operand OpClass = opclass;
-}
-
 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
                           list<SDNode> roots = [],
                           list<SDNodeProperty> props = []> :
   ComplexPattern<ty, numops, fn, roots, props> {
   Operand OpClass = opclass;
 }
 
 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,

llvm/lib/Target/Mips/MipsRegisterInfo.td

 
 // Accumulator Registers
 class ACCReg<bits<16> Enc, string n, list<Register> subregs>
   : MipsRegWithSubRegs<Enc, n, subregs> {
   let SubRegIndices = [sub_lo, sub_hi];
   let CoveredBySubRegs = 1;
 }
 
-// Mips Hardware Registers
-class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
-
 //===----------------------------------------------------------------------===//
 //  Registers
 //===----------------------------------------------------------------------===//
 
 let Namespace = "Mips" in {
   // General Purpose Registers
   let isConstant = true in
   def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;