[PowerPC] Remove unused TableGen classes and multiclasses.

[kosarev]

Summary

And warn on them from now on.

[lattner]

seems obvious to me, but I don't work on PPC backend anymore.

llvm/lib/Target/PowerPC/CMakeLists.txt

 add_llvm_component_group(PowerPC HAS_JIT)
 
 set(LLVM_TARGET_DEFINITIONS PPC.td)
 
 tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel -warn-on-unused-entities)
 tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
 tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM PPCGenExegesis.inc -gen-exegesis)
 tablegen(LLVM PPCGenRegisterBank.inc -gen-register-bank)

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 // Helpers for defining instructions that directly correspond to intrinsics.
 
 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
   : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
               !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
                        [(set Ty:$RT, (IntID Ty:$RA, Ty:$RB, Ty:$RC))]>;
 
-// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
-// inputs doesn't match the type of the output.
-class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
-                   ValueType InTy>
-  : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
-              !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
-                       [(set OutTy:$RT, (IntID InTy:$RA, InTy:$RB, InTy:$RC))]>;
-
 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
 // input types and an output type.
 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
                    ValueType In1Ty, ValueType In2Ty>
   : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
               !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
                        [(set OutTy:$RT,
                          (IntID In1Ty:$RA, In1Ty:$RB, In2Ty:$RC))]>;

llvm/lib/Target/PowerPC/PPCInstrFormats.td

 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
 class PPC970_MicroCode;
 
 class PPC970_Unit_Pseudo   { bits<3> PPC970_Unit = 0;   }
 class PPC970_Unit_FXU      { bits<3> PPC970_Unit = 1;   }
 class PPC970_Unit_LSU      { bits<3> PPC970_Unit = 2;   }
 class PPC970_Unit_FPU      { bits<3> PPC970_Unit = 3;   }
 class PPC970_Unit_CRU      { bits<3> PPC970_Unit = 4;   }
-class PPC970_Unit_VALU     { bits<3> PPC970_Unit = 5;   }
-class PPC970_Unit_VPERM    { bits<3> PPC970_Unit = 6;   }
 class PPC970_Unit_BRU      { bits<3> PPC970_Unit = 7;   }
 
 class XFormMemOp { bits<1> XFormMemOp = 1; }
 class SExt32To64 { bits<1> SExt32To64 = 1; }
 class ZExt32To64 { bits<1> ZExt32To64 = 1; }
 
 // Two joined instructions; used to emit two adjacent instructions as one.
 // The itinerary from the first instruction is used for scheduling and
class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
   let TSFlags{2}   = PPC970_Cracked;
   let TSFlags{5-3} = PPC970_Unit;
 
   // Fields used for relation models.
   string BaseName = "";
   bit Interpretation64Bit = 0;
 }
 
-// Base class for all X-Form memory instructions
-class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr,
-                  InstrItinClass itin>
-        :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp;
-
 // 1.7.1 I-Form
 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
             InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   let Pattern = pattern;
   bits<24> LI;
 
   let Inst{6-29}  = LI;
class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   
   let Inst{6-10}  = FRT;
   let Inst{11-15} = FRA;
   let Inst{16-20} = FRB;
   let Inst{21-30} = xo;
   let Inst{31}    = 0;
 }
 
-class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
-              InstrItinClass itin, list<dag> pattern> 
-  : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
-  let FRA = 0;
-}
-
-class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
-               InstrItinClass itin, list<dag> pattern>
-         : I<opcode, OOL, IOL, asmstr, itin> {
-  bits<5> FRT;
-  bits<5> FRA;
-  bits<5> FRB;
-  bits<4> tttt;
-
-  let Pattern = pattern;
-  
-  let Inst{6-10}  = FRT;
-  let Inst{11-15} = FRA;
-  let Inst{16-20} = FRB;
-  let Inst{21-24} = tttt;
-  let Inst{25-30} = xo;
-  let Inst{31}    = 0;
-}
-
 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern> 
   : I<opcode, OOL, IOL, asmstr, itin> {
   let Pattern = pattern;
   let Inst{6-10}  = 31;
   let Inst{11-15} = 0;
   let Inst{16-20} = 0;
   let Inst{21-30} = xo;