It is because of "defined(ANDROID) && defined(LP64)" part.

LGTM.

LGTM with few nits.

LGTM with a few nits.

LGTM with a nit.

LGTM with a nit.

LGTM.

LGTM otherwise.

LGTM.

LGTM.

LGTM.

In order to use iterative compilation algorithm for target different then MIPS it is necessary to implement appropriate function fitness pass that evaluates generated code. In our patch criteria used is code size and pass is implemented in lib/Target/Mips/MipsFunctionFitness.cpp file.
In case of X86 code size calculation is more complex because of variable-length machine instruction encoding.
We are looking for possibilities to issue more informative error message until architecture is supported.

New patch version.
Patch rebased and formatting comments addressed.

New patch version rebased to r256194.
Any comments to this work?

New patch version rebased to r256194.
Any comments on this work?

New patch version.
Generated code is correct (sd/ld are used to store/restore pointer value).
It passes -verify-machineinstrs for o32, n32 and n64.

New patch version that only changes type of AlignedAddr and uses appropriate AND instruction for calculating value of AlignedAddr (although correct output will be produced with any AND instruction because they all work on register size data - functionally there is no AND32 and AND64).

As stated in description of the patch it is new revision of: http://reviews.llvm.org/D13649, which was created by Jelena Losic, and all following revisions were based on received comments.
This revision is based on latest set of comments received on http://reviews.llvm.org/D13649.
I do believe that it produces correct output.
Also, I do agree that particular issue can be fixed by only changing type of alignedaddr pseudo to i64 when pointers are 64 bit.
I will prepare new patch version that handles issue in that manner.

Just to PING.
Any comments on this work?

Replaced by:
http://reviews.llvm.org/D6582

Replaced by:
http://reviews.llvm.org/D6039

Replaced by:

New patch version that corresponds to latest version of:
http://reviews.llvm.org/D12199

This version introduces new algorithm for exploring decision trees.
As stated in the last patch, splitting one big decision tree into multiple ones for every function in compilation unit can improve results.
Furthermore, separate decision trees are needed for each optimization phase (interprocedural, precodegen and codegen).

Usage of simm19_lsl2 replaced by simm18_lsl3.

Rebased to work with top of the tree. There were issues with recently added RDHWR and RDPGPR instructions.

Updated to follow new revision of patch for iterative compilation in llvm:
http://reviews.llvm.org/D12199

*Places for improvement*

Test files renamed and changed usage of predicates.

LGTM.

LGTM with a nit.

LGTM

This patch needs to be applied along with the patch for clang.
See http://reviews.llvm.org/D12200 for more details.

This patch needs to be applied along with the patch for llvm.
See http://reviews.llvm.org/D12199 for more details.

This is a follow-up work on the iterative compilation framework for clang/llvm.
Initial discussion as well as the introduction to this approach has been presented at:

LGTM.

LGTM with a nit.

LGTM

There may be encoding changes for these instructions.

LGTM with a nit.

LGTM with a nit.

LGTM with a nit.

LGTM.

LGTM.

LGTM.

LGTM

Fixed issues. Rebased.

LGTM

LGTM

LGTM.

Fixed issue with non sequential register allocation order.

LGTM

LGTM

Disassembler test cases added.

Fixed issue with lw16 and reg+offset addresses.

Fixed issues with test cases.

Modified and rebased patch.

There is the same issue with PseudoReturn.

Test case modified according to review.

Labels also relocated with the symbol.