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Differential D153524

[Hexagon] Remove unused TableGen classes and multiclasses.
AcceptedPublic

Authored by kosarev on Jun 22 2023, 4:02 AM.

Details

Reviewers
kparzysz
colinl
jverma
Summary

And warn on them from now on.

Diff Detail

Event Timeline

kosarev created this revision.Jun 22 2023, 4:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 22 2023, 4:02 AM
Herald added a subscriber: hiraditya. · View Herald Transcript
kosarev requested review of this revision.Jun 22 2023, 4:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 22 2023, 4:02 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B240458: Diff 533541.Jun 22 2023, 4:18 AM
kosarev added a parent revision: D152373: [TableGen] Support warnings on unused classes and multiclasses..Jun 22 2023, 4:31 AM
kosarev added reviewers: kparzysz, colinl, jverma.Jun 22 2023, 4:34 AM
kparzysz accepted this revision.Jun 29 2023, 4:13 PM

A lot of the removed stuff is in files that are auto-generated... Sure, feel free to commit this.

This revision is now accepted and ready to land.Jun 29 2023, 4:13 PM
barannikov88 added a subscriber: barannikov88.Jun 29 2023, 4:51 PM
In D153524#4462061, @kparzysz wrote:

A lot of the removed stuff is in files that are auto-generated...

Is the generator publicly available?

Revision Contents

Diff 533541

llvm/lib/Target/Hexagon/CMakeLists.txt

add_llvm_component_group(Hexagon) add_llvm_component_group(Hexagon)
set(LLVM_TARGET_DEFINITIONS Hexagon.td) set(LLVM_TARGET_DEFINITIONS Hexagon.td)
tablegen(LLVM HexagonGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM HexagonGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv) tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel) tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel -warn-on-unused-entities)
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer) tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info) tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info) tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM HexagonGenSubtargetInfo.inc -gen-subtarget) tablegen(LLVM HexagonGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(HexagonCommonTableGen) add_public_tablegen_target(HexagonCommonTableGen)
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llvm/lib/Target/Hexagon/Hexagon.td

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// predicated forms. // predicated forms.
class PredRel; class PredRel;
class PredNewRel: PredRel; class PredNewRel: PredRel;
// NewValueRel - Filter class used to relate regular store instructions with // NewValueRel - Filter class used to relate regular store instructions with
// their new-value store form. // their new-value store form.
class NewValueRel: PredNewRel; class NewValueRel: PredNewRel;
class AddrModeRel: NewValueRel; class AddrModeRel: NewValueRel;
class PostInc_BaseImm; class PostInc_BaseImm;
class IntrinsicsRel;
// ... through here. // ... through here.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Generate mapping table to relate non-predicate instructions with their // Generate mapping table to relate non-predicate instructions with their
// predicated formats - true and false. // predicated formats - true and false.
// //
def getPredOpcode : InstrMapping { def getPredOpcode : InstrMapping {
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def takenBranchPrediction : InstrMapping { def takenBranchPrediction : InstrMapping {
let FilterClass = "PredRel"; let FilterClass = "PredRel";
let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
let ColFields = ["isBrTaken"]; let ColFields = ["isBrTaken"];
let KeyCol = ["false"]; let KeyCol = ["false"];
let ValueCols = [["true"]]; let ValueCols = [["true"]];
} }
def getRealHWInstr : InstrMapping {
let FilterClass = "IntrinsicsRel";
let RowFields = ["BaseOpcode"];
let ColFields = ["InstrType"];
let KeyCol = ["Pseudo"];
let ValueCols = [["Pseudo"], ["Real"]];
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register File, Instruction Descriptions // Register File, Instruction Descriptions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "HexagonSchedule.td" include "HexagonSchedule.td"
include "HexagonRegisterInfo.td" include "HexagonRegisterInfo.td"
include "HexagonOperands.td" include "HexagonOperands.td"
include "HexagonDepOperands.td" include "HexagonDepOperands.td"
include "HexagonDepITypes.td" include "HexagonDepITypes.td"
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llvm/lib/Target/Hexagon/HexagonDepIICHVX.td

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def tc_e3f68a46 : InstrItinClass; def tc_e3f68a46 : InstrItinClass;
def tc_e675c45a : InstrItinClass; def tc_e675c45a : InstrItinClass;
def tc_e699ae41 : InstrItinClass; def tc_e699ae41 : InstrItinClass;
def tc_e99d4c2e : InstrItinClass; def tc_e99d4c2e : InstrItinClass;
def tc_f175e046 : InstrItinClass; def tc_f175e046 : InstrItinClass;
def tc_f1de44ef : InstrItinClass; def tc_f1de44ef : InstrItinClass;
def tc_f21e8abb : InstrItinClass; def tc_f21e8abb : InstrItinClass;
class DepHVXItinV55 {
list<InstrItinData> DepHVXItinV55_list = [
InstrItinData <tc_0390c1ca, /*SLOT01,LOAD,VA,VX_DV*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_04da405a, /*SLOT0123,VP_VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>], [9, 5],
[HVX_FWD, HVX_FWD]>,
InstrItinData <tc_05ca8cfd, /*SLOT0123,VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>], [9, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_08a4f1b6, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_0afc8be9, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5],
[HVX_FWD, HVX_FWD]>,
InstrItinData <tc_0b04c6c7, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_0ec46cf9, /*SLOT0123,VA*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7],
[HVX_FWD, HVX_FWD]>,
InstrItinData <tc_131f1c81, /*SLOT0,NOSLOT1,STORE,VP*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_XLANE]>], [2, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_1381a97c, /*SLOT0123,4SLOT*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ALL]>], [],
[]>,
InstrItinData <tc_15fdf750, /*SLOT23,VS_VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_16ff9ef8, /*SLOT0123,VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>], [9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_191381c1, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 7, 1, 2, 7],
[Hex_FWD, HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_1ad8a370, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 2, 2],
[HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1ba8a0cd, /*SLOT01,LOAD,VA*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_20a4bbec, /*SLOT0,STORE*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_227864f7, /*SLOT0,STORE,VA,VX_DV*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE], 0>,
InstrStage<1, [CVI_MPY01]>], [3, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_257f6f7c, /*SLOT0123,VA*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_26a377fe, /*SLOT23,4SLOT_MPY*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2],
[HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_2b4c548e, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_2c745bb8, /*SLOT0123,VP_VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_2d4051cd, /*SLOT23,4SLOT_MPY*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 7, 5, 2],
[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_309dbb4f, /*SLOT0123,VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_37820f4c, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_3904b926, /*SLOT01,LOAD*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD]>], [9, 2, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3aacf4a8, /*SLOT0123,VA*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7],
[HVX_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3c56e5ce, /*SLOT0,NOSLOT1,LOAD,VP*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 3, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3c8c15d0, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5],
[HVX_FWD, HVX_FWD]>,
InstrItinData <tc_3ce09744, /*SLOT0,STORE*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3e2aaafc, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_447d9895, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_453fe68d, /*SLOT01,LOAD,VA*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 2, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_46d6c3e0, /*SLOT0123,VP*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_4942646a, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_51d0ecc3, /*SLOT0123,VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>], [9, 5],
[HVX_FWD, HVX_FWD]>,
InstrItinData <tc_52447ecc, /*SLOT01,LOAD*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD]>], [9, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_531b383c, /*SLOT0123*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [9, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_540c3da3, /*SLOT0,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
[Hex_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_54a0dc47, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 2, 1, 2, 7],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_561aaa58, /*SLOT0123,VP_VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_56c4f9fe, /*SLOT0123,VA*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_56e64202, /*SLOT0123,VP*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_58d21193, /*SLOT0,STORE,VA_DV*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_5bf8afbb, /*SLOT0123,VP*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 2],
[HVX_FWD, Hex_FWD]>,
InstrItinData <tc_5cdf8c84, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7],
[HVX_FWD, HVX_FWD]>,
InstrItinData <tc_61bf7c03, /*SLOT23,4SLOT_MPY*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_649072c2, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_660769f1, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_663c80a7, /*SLOT01,LOAD*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD]>], [9, 3, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6942b6e0, /*SLOT0,STORE*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_6e7fa133, /*SLOT0123,VP*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_7095ecba, /*SLOT1,LOAD,VA_DV*/
[InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
[Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_71646d06, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_7177e272, /*SLOT0,STORE*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [2, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_718b5c53, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
[HVX_FWD]>,
InstrItinData <tc_7273323b, /*SLOT0,STORE,VA_DV*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
[Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_72e2b393, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_73efe966, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_7417e785, /*SLOT0123,VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_767c4e9d, /*SLOT0123,4SLOT*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ALL]>], [3, 2],
[HVX_FWD, Hex_FWD]>,
InstrItinData <tc_7d68d5c2, /*SLOT1,LOAD,VA*/
[InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_7e6a3e89, /*SLOT0123,VA*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_8772086c, /*SLOT0123,VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>], [9, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_87adc037, /*SLOT0123,VP_VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_8e420e4d, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_90bcc1db, /*SLOT2,VX_DV*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_933f2b39, /*SLOT23,4SLOT_MPY*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 7, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_946013d8, /*SLOT0123,VP*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 5],
[HVX_FWD, HVX_FWD]>,
InstrItinData <tc_9a1cab75, /*SLOT01,LOAD,VA,VX_DV*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 3, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9aff7a2a, /*SLOT0,STORE,VA,VX_DV*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE], 0>,
InstrStage<1, [CVI_MPY01]>], [1, 2, 5],
[Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_9d1dc972, /*SLOT0123,VP_VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_9f363d21, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
[Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_a02a10a8, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_ZW]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a19b9305, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_a28f32b5, /*SLOT1,LOAD,VA*/
[InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
[Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_a69eeee1, /*SLOT1,LOAD,VA_DV*/
[InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_a7e6707d, /*SLOT0,NOSLOT1,LOAD,VP*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ab23f776, /*SLOT0,STORE*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [1, 2, 5],
[Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_abe8c3b2, /*SLOT01,LOAD,VA*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ac4046bc, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_af25efd9, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 2, 7, 7],
[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_b091f1c6, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_b28e51aa, /*SLOT0123,4SLOT*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ALL]>], [2],
[Hex_FWD]>,
InstrItinData <tc_b4416217, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
[HVX_FWD, HVX_FWD]>,
InstrItinData <tc_b9db8205, /*SLOT01,LOAD*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_bb599486, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_c0749f3c, /*SLOT01,LOAD,VA*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_c127de3a, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_c4edf264, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 2],
[HVX_FWD, Hex_FWD]>,
InstrItinData <tc_c5dba46e, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
[Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_c7039829, /*SLOT0,NOSLOT1,STORE,VP*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_XLANE]>], [3, 2, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_cd94bfe0, /*SLOT23,VS_VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_cda936da, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_d8287c14, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_db5555f3, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_dcca380f, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_ZW]>], [2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_df80eeb0, /*SLOT0123,VP_VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_e2d2e9e5, /*SLOT0,NOSLOT1,STORE,VP*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_e2fdd6e6, /*SLOT0123*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [9, 7],
[HVX_FWD, HVX_FWD]>,
InstrItinData <tc_e35c1e93, /*SLOT0123,VA*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
InstrItinData <tc_e3f68a46, /*SLOT0123,4SLOT*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ALL]>], [3],
[HVX_FWD]>,
InstrItinData <tc_e675c45a, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_e699ae41, /*SLOT01,ZW*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_ZW]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_e99d4c2e, /*SLOT0,STORE*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
InstrItinData <tc_f175e046, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_f1de44ef, /*SLOT2,VX_DV*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
InstrItinData <tc_f21e8abb, /*SLOT0,NOSLOT1,STORE,VP*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_XLANE]>], [1, 2, 5],
[Hex_FWD, Hex_FWD, HVX_FWD]>
];
}
class DepHVXItinV60 { class DepHVXItinV60 {
list<InstrItinData> DepHVXItinV60_list = [ list<InstrItinData> DepHVXItinV60_list = [
InstrItinData <tc_0390c1ca, /*SLOT01,LOAD,VA,VX_DV*/ InstrItinData <tc_0390c1ca, /*SLOT01,LOAD,VA,VX_DV*/
[InstrStage<1, [SLOT0, SLOT1], 0>, [InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE], 0>, InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 1, 2], InstrStage<1, [CVI_MPY01]>], [9, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD]>, [HVX_FWD, Hex_FWD, Hex_FWD]>,
▲ Show 20 Lines • Show All 5,319 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonDepIICScalar.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,005 Lines • ▼ Show 20 Lines InstrItinData <tc_fae9dfa5, /*tc_3x*/
[Hex_FWD, Hex_FWD]>, [Hex_FWD, Hex_FWD]>,
InstrItinData <tc_fedb7e19, /*tc_ld*/ InstrItinData <tc_fedb7e19, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>
]; ];
} }
class DepScalarItinV60se {
list<InstrItinData> DepScalarItinV60se_list = [
InstrItinData <tc_011e0e9d, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_01d44cb2, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_01e1be3b, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_02fe1c65, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0655b949, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_075c8dd8, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0a195f2c, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0a6c20ae, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0ba0d5da, /*tc_2early*/
[InstrStage<1, [SLOT2]>], [1],
[Hex_FWD]>,
InstrItinData <tc_0dfac0a7, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0fac1eb8, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_112d30d6, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
[Hex_FWD]>,
InstrItinData <tc_1242dc2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [2],
[Hex_FWD]>,
InstrItinData <tc_1248597c, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_14ab4f41, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_151bf368, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_158aa3f7, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_197dce51, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1981450d, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3],
[Hex_FWD]>,
InstrItinData <tc_1c2c7a4a, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1c7522a8, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1d41f8b7, /*tc_3stall*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1fcb8495, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1fe4ab69, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_20131976, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_2237d952, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_23708a21, /*tc_2early*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [],
[]>,
InstrItinData <tc_2471c1c8, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_24e109c7, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_24f426ab, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_27106296, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_280f7fe1, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_28e55c6f, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [1, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_2c13e7f5, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_2c3e17fc, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [1],
[Hex_FWD]>,
InstrItinData <tc_2f573607, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_33e7e673, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [],
[]>,
InstrItinData <tc_362b0be2, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [1],
[Hex_FWD]>,
InstrItinData <tc_38382228, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_388f9897, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_38e0bae9, /*tc_3stall*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3d14a17b, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3edca78f, /*tc_2*/
[InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3fbf1042, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1]>], [3],
[Hex_FWD]>,
InstrItinData <tc_407e96f9, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_40d64c94, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4222e6bf, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_42ff66ba, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_442395f3, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_449acf79, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_44d5a428, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_44fffc58, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [2],
[Hex_FWD]>,
InstrItinData <tc_45791fb8, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_45f9d1be, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [2],
[Hex_FWD]>,
InstrItinData <tc_49fdfd4b, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4a55d03c, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4abdbdc6, /*tc_3stall*/
[InstrStage<1, [SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4ac61d92, /*tc_2latepred*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4bf903b0, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,
InstrItinData <tc_503ce0f3, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_53c851ab, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5502c366, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_55255f2b, /*tc_3stall*/
[InstrStage<1, [SLOT3]>], [],
[]>,
InstrItinData <tc_556f6577, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_55a9a350, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_55b33fda, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_56a124a7, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_57a55b54, /*tc_2early*/
[InstrStage<1, [SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5944960d, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_59a7822c, /*tc_2early*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5a4b5e58, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5b347363, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5ceb2f9e, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5da50c4b, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5deb5e47, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5e4cf0e8, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5f2afaf7, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_60e324ff, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [1],
[Hex_FWD]>,
InstrItinData <tc_63567288, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1]>], [3],
[Hex_FWD]>,
InstrItinData <tc_64b00d8a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_651cbe02, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_65279839, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_65cbd974, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_69bfb303, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6ae3426b, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6d861a95, /*tc_3stall*/
[InstrStage<1, [SLOT3]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6e20402a, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 3],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6f42bc60, /*tc_3stall*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6fc5dbea, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_711c805f, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_713b66bf, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7401744f, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7476d766, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_74a42bda, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_76bb5435, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_77f94a5e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [],
[]>,
InstrItinData <tc_788b1d09, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7af3a37e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 3],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7b9187d3, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7c6d32e4, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7dc63b5c, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7f7f45f5, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7f8ae742, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8035e91f, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_822c3c68, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_829d8a86, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_838c4d7a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_84a7500d, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_86173609, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_887d1bb7, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8a6d0d94, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8a825db2, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8b5bd4f5, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8e82e8ca, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8f36a2fd, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9124c04f, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_92240447, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_934753bb, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_937dd41c, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [],
[]>,
InstrItinData <tc_9406230a, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_95a33176, /*tc_2*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_95f43c5e, /*tc_3*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [1],
[Hex_FWD]>,
InstrItinData <tc_96ef76ef, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_975a4e54, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [2, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9783714b, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9b34f5e0, /*tc_2early*/
[InstrStage<1, [SLOT2]>], [],
[]>,
InstrItinData <tc_9b3c0462, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9bcfb2ee, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9c52f549, /*tc_2early*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9e27f2f9, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9e72dc89, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9edb7c77, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9edefe01, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9f6cd987, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a08b630b, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a1297125, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a154b476, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a2b365d2, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a3070909, /*tc_3stall*/
[InstrStage<1, [SLOT0]>], [1, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a32e03e7, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a38c45dc, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a4e22bbd, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a4ee89db, /*tc_2early*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [],
[]>,
InstrItinData <tc_a7a13fac, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a7bdb22c, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a9edeffa, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_abfd9a6d, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ac65613f, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_addc37a8, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ae5babd7, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_aee6250c, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_af6af259, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_b1ae5f67, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1],
[Hex_FWD]>,
InstrItinData <tc_b4dc7630, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_b7c4062a, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_b837298f, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
[]>,
InstrItinData <tc_ba9255a6, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_bb07f2c5, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_bb831a7c, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_bf2ffc0f, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_c20701f0, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_c21d7447, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_c57d9f39, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_c818ff7f, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [],
[]>,
InstrItinData <tc_ce59038e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_cfa0e29b, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d03278fd, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d33e5eee, /*tc_2early*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d3632d88, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d45ba9cd, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [1],
[Hex_FWD]>,
InstrItinData <tc_d57d649c, /*tc_3stall*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [2],
[Hex_FWD]>,
InstrItinData <tc_d61dfdc3, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d68dca5c, /*tc_3stall*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d7718fbe, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [1],
[Hex_FWD]>,
InstrItinData <tc_db596beb, /*tc_3stall*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_db96aa6b, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1],
[Hex_FWD]>,
InstrItinData <tc_dc51281d, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_decdde8a, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [2],
[Hex_FWD]>,
InstrItinData <tc_df5d53f9, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_e3d699e3, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_e60def48, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [1],
[Hex_FWD]>,
InstrItinData <tc_e9170fb7, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ed03645c, /*tc_2early*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [3, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_eeda4109, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ef921005, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f098b237, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f0cdeccf, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f0e8e832, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f34c1c21, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f38f92e1, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [2],
[Hex_FWD]>,
InstrItinData <tc_f529831b, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f6e2aff9, /*tc_newvjump*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f7569068, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f97707c1, /*tc_1*/
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_ST]>], [2],
[Hex_FWD]>,
InstrItinData <tc_f999c66e, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_ST]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_fae9dfa5, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_fedb7e19, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>
];
}
class DepScalarItinV62 { class DepScalarItinV62 {
list<InstrItinData> DepScalarItinV62_list = [ list<InstrItinData> DepScalarItinV62_list = [
InstrItinData <tc_011e0e9d, /*tc_st*/ InstrItinData <tc_011e0e9d, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 1, 2, 3], [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_01d44cb2, /*tc_2*/ InstrItinData <tc_01d44cb2, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
▲ Show 20 Lines • Show All 2,384 Lines • ▼ Show 20 Lines InstrItinData <tc_fae9dfa5, /*tc_3x*/
[Hex_FWD, Hex_FWD]>, [Hex_FWD, Hex_FWD]>,
InstrItinData <tc_fedb7e19, /*tc_ld*/ InstrItinData <tc_fedb7e19, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>
]; ];
} }
class DepScalarItinV67 {
list<InstrItinData> DepScalarItinV67_list = [
InstrItinData <tc_011e0e9d, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_01d44cb2, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_01e1be3b, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_02fe1c65, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0655b949, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 3],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_075c8dd8, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0a195f2c, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0a6c20ae, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0ba0d5da, /*tc_3stall*/
[InstrStage<1, [SLOT2]>], [1],
[Hex_FWD]>,
InstrItinData <tc_0dfac0a7, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_0fac1eb8, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_112d30d6, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
[Hex_FWD]>,
InstrItinData <tc_1242dc2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [2],
[Hex_FWD]>,
InstrItinData <tc_1248597c, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_14ab4f41, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [3, 3, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_151bf368, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_158aa3f7, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_197dce51, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1981450d, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,
InstrItinData <tc_1c2c7a4a, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1c7522a8, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1d41f8b7, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1fcb8495, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_1fe4ab69, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_20131976, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_2237d952, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_23708a21, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
[]>,
InstrItinData <tc_2471c1c8, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_24e109c7, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [3, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_24f426ab, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_27106296, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_280f7fe1, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_28e55c6f, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [1, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_2c13e7f5, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_2c3e17fc, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [1],
[Hex_FWD]>,
InstrItinData <tc_2f573607, /*tc_1*/
[InstrStage<1, [SLOT2]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_33e7e673, /*tc_2early*/
[InstrStage<1, [SLOT2]>], [],
[]>,
InstrItinData <tc_362b0be2, /*tc_3*/
[InstrStage<1, [SLOT2]>], [1],
[Hex_FWD]>,
InstrItinData <tc_38382228, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_388f9897, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_38e0bae9, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3d14a17b, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3edca78f, /*tc_2*/
[InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_3fbf1042, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1]>], [3],
[Hex_FWD]>,
InstrItinData <tc_407e96f9, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_40d64c94, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [3, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4222e6bf, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_42ff66ba, /*tc_1*/
[InstrStage<1, [SLOT2]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_442395f3, /*tc_2latepred*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_449acf79, /*tc_latepredstaia*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_44d5a428, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_44fffc58, /*tc_3*/
[InstrStage<1, [SLOT2, SLOT3]>], [2],
[Hex_FWD]>,
InstrItinData <tc_45791fb8, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_45f9d1be, /*tc_2early*/
[InstrStage<1, [SLOT2]>], [2],
[Hex_FWD]>,
InstrItinData <tc_49fdfd4b, /*tc_3stall*/
[InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4a55d03c, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4abdbdc6, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4ac61d92, /*tc_2latepred*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_4bf903b0, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,
InstrItinData <tc_503ce0f3, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_53c851ab, /*tc_3stall*/
[InstrStage<1, [SLOT2]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5502c366, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_55255f2b, /*tc_3stall*/
[InstrStage<1, [SLOT3]>], [],
[]>,
InstrItinData <tc_556f6577, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_55a9a350, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_55b33fda, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_56a124a7, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_57a55b54, /*tc_1*/
[InstrStage<1, [SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5944960d, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_59a7822c, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5a4b5e58, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5b347363, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5ceb2f9e, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5da50c4b, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5deb5e47, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5e4cf0e8, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_5f2afaf7, /*tc_latepredldaia*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 4, 3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_60e324ff, /*tc_1*/
[InstrStage<1, [SLOT2]>], [2],
[Hex_FWD]>,
InstrItinData <tc_63567288, /*tc_2latepred*/
[InstrStage<1, [SLOT0, SLOT1]>], [4],
[Hex_FWD]>,
InstrItinData <tc_64b00d8a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_651cbe02, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_65279839, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_65cbd974, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_69bfb303, /*tc_3*/
[InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6ae3426b, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6d861a95, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6e20402a, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 3],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6f42bc60, /*tc_3stall*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_6fc5dbea, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_711c805f, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_713b66bf, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7401744f, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7476d766, /*tc_3stall*/
[InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_74a42bda, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_76bb5435, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_77f94a5e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [],
[]>,
InstrItinData <tc_788b1d09, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7af3a37e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 3],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7b9187d3, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7c6d32e4, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7dc63b5c, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7f7f45f5, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_7f8ae742, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8035e91f, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_822c3c68, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_829d8a86, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_838c4d7a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_84a7500d, /*tc_2*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_86173609, /*tc_2latepred*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_887d1bb7, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8a6d0d94, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8a825db2, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8b5bd4f5, /*tc_2*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8e82e8ca, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_8f36a2fd, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9124c04f, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_92240447, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_934753bb, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_937dd41c, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [],
[]>,
InstrItinData <tc_9406230a, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_95a33176, /*tc_2*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_95f43c5e, /*tc_3*/
[InstrStage<1, [SLOT2]>], [1],
[Hex_FWD]>,
InstrItinData <tc_96ef76ef, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_975a4e54, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [3, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9783714b, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9b34f5e0, /*tc_3stall*/
[InstrStage<1, [SLOT2]>], [],
[]>,
InstrItinData <tc_9b3c0462, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9bcfb2ee, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9c52f549, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9e27f2f9, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9e72dc89, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9edb7c77, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9edefe01, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_9f6cd987, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a08b630b, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a1297125, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a154b476, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a2b365d2, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a3070909, /*tc_3stall*/
[InstrStage<1, [SLOT0]>], [1, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a32e03e7, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a38c45dc, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a4e22bbd, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a4ee89db, /*tc_2early*/
[InstrStage<1, [SLOT0]>], [],
[]>,
InstrItinData <tc_a7a13fac, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a7bdb22c, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_a9edeffa, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_abfd9a6d, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ac65613f, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_addc37a8, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ae5babd7, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_aee6250c, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_af6af259, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_b1ae5f67, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1],
[Hex_FWD]>,
InstrItinData <tc_b4dc7630, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_b7c4062a, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_b837298f, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
[]>,
InstrItinData <tc_ba9255a6, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_bb07f2c5, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_bb831a7c, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_bf2ffc0f, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_c20701f0, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_c21d7447, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_c57d9f39, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_c818ff7f, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [],
[]>,
InstrItinData <tc_ce59038e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_cfa0e29b, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d03278fd, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d33e5eee, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d3632d88, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d45ba9cd, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [1],
[Hex_FWD]>,
InstrItinData <tc_d57d649c, /*tc_3stall*/
[InstrStage<1, [SLOT2]>], [2],
[Hex_FWD]>,
InstrItinData <tc_d61dfdc3, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d68dca5c, /*tc_3stall*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_d7718fbe, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [1],
[Hex_FWD]>,
InstrItinData <tc_db596beb, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_db96aa6b, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1],
[Hex_FWD]>,
InstrItinData <tc_dc51281d, /*tc_3*/
[InstrStage<1, [SLOT2]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_decdde8a, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
[Hex_FWD]>,
InstrItinData <tc_df5d53f9, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [3, 2, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_e3d699e3, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_e60def48, /*tc_1*/
[InstrStage<1, [SLOT2]>], [2],
[Hex_FWD]>,
InstrItinData <tc_e9170fb7, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ed03645c, /*tc_1*/
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_eeda4109, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_ef921005, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f098b237, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f0cdeccf, /*tc_3x*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f0e8e832, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f34c1c21, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f38f92e1, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [2],
[Hex_FWD]>,
InstrItinData <tc_f529831b, /*tc_latepredstaia*/
[InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f6e2aff9, /*tc_newvjump*/
[InstrStage<1, [SLOT0]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f7569068, /*tc_4x*/
[InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_f97707c1, /*tc_1*/
[InstrStage<1, [SLOT2]>], [2],
[Hex_FWD]>,
InstrItinData <tc_f999c66e, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_fae9dfa5, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
InstrItinData <tc_fedb7e19, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>
];
}
class DepScalarItinV67T { class DepScalarItinV67T {
list<InstrItinData> DepScalarItinV67T_list = [ list<InstrItinData> DepScalarItinV67T_list = [
InstrItinData <tc_011e0e9d, /*tc_st*/ InstrItinData <tc_011e0e9d, /*tc_st*/
[InstrStage<1, [SLOT0]>], [2, 1, 2, 3], [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
InstrItinData <tc_01d44cb2, /*tc_2*/ InstrItinData <tc_01d44cb2, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
▲ Show 20 Lines • Show All 4,791 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td

Show All 38 Linesclass Enc_041d7b : OpcodeHexagon {
bits <4> Rs16; bits <4> Rs16;
let Inst{19-16} = Rs16{3-0}; let Inst{19-16} = Rs16{3-0};
bits <5> n1; bits <5> n1;
let Inst{28-28} = n1{4-4}; let Inst{28-28} = n1{4-4};
let Inst{24-23} = n1{3-2}; let Inst{24-23} = n1{3-2};
let Inst{13-13} = n1{1-1}; let Inst{13-13} = n1{1-1};
let Inst{8-8} = n1{0-0}; let Inst{8-8} = n1{0-0};
} }
class Enc_046afa : OpcodeHexagon {
bits <1> Mu2;
let Inst{13-13} = Mu2{0-0};
bits <5> Vss32;
let Inst{4-0} = Vss32{4-0};
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
class Enc_04c959 : OpcodeHexagon { class Enc_04c959 : OpcodeHexagon {
bits <2> Ii; bits <2> Ii;
let Inst{13-13} = Ii{1-1}; let Inst{13-13} = Ii{1-1};
let Inst{7-7} = Ii{0-0}; let Inst{7-7} = Ii{0-0};
bits <6> II; bits <6> II;
let Inst{11-8} = II{5-2}; let Inst{11-8} = II{5-2};
let Inst{6-5} = II{1-0}; let Inst{6-5} = II{1-0};
bits <5> Rt32; bits <5> Rt32;
▲ Show 20 Lines • Show All 1,285 Lines • ▼ Show 20 Lines
class Enc_5eac98 : OpcodeHexagon { class Enc_5eac98 : OpcodeHexagon {
bits <6> Ii; bits <6> Ii;
let Inst{13-8} = Ii{5-0}; let Inst{13-8} = Ii{5-0};
bits <5> Rss32; bits <5> Rss32;
let Inst{20-16} = Rss32{4-0}; let Inst{20-16} = Rss32{4-0};
bits <5> Rdd32; bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0}; let Inst{4-0} = Rdd32{4-0};
} }
class Enc_5eb169 : OpcodeHexagon {
bits <3> Ii;
let Inst{10-8} = Ii{2-0};
bits <5> Vdd32;
let Inst{4-0} = Vdd32{4-0};
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
class Enc_607661 : OpcodeHexagon { class Enc_607661 : OpcodeHexagon {
bits <6> Ii; bits <6> Ii;
let Inst{12-7} = Ii{5-0}; let Inst{12-7} = Ii{5-0};
bits <5> Rd32; bits <5> Rd32;
let Inst{4-0} = Rd32{4-0}; let Inst{4-0} = Rd32{4-0};
} }
class Enc_6185fe : OpcodeHexagon { class Enc_6185fe : OpcodeHexagon {
bits <2> Ii; bits <2> Ii;
Show All 37 Linesclass Enc_6339d5 : OpcodeHexagon {
let Inst{6-5} = Pv4{1-0}; let Inst{6-5} = Pv4{1-0};
bits <5> Rs32; bits <5> Rs32;
let Inst{20-16} = Rs32{4-0}; let Inst{20-16} = Rs32{4-0};
bits <5> Ru32; bits <5> Ru32;
let Inst{12-8} = Ru32{4-0}; let Inst{12-8} = Ru32{4-0};
bits <5> Rt32; bits <5> Rt32;
let Inst{4-0} = Rt32{4-0}; let Inst{4-0} = Rt32{4-0};
} }
class Enc_634460 : OpcodeHexagon {
bits <4> Ii;
let Inst{13-13} = Ii{3-3};
let Inst{10-8} = Ii{2-0};
bits <5> Rt32;
let Inst{20-16} = Rt32{4-0};
bits <5> Vdd32;
let Inst{4-0} = Vdd32{4-0};
}
class Enc_63eaeb : OpcodeHexagon { class Enc_63eaeb : OpcodeHexagon {
bits <2> Ii; bits <2> Ii;
let Inst{1-0} = Ii{1-0}; let Inst{1-0} = Ii{1-0};
bits <4> Rs16; bits <4> Rs16;
let Inst{7-4} = Rs16{3-0}; let Inst{7-4} = Rs16{3-0};
} }
class Enc_6413b6 : OpcodeHexagon { class Enc_6413b6 : OpcodeHexagon {
bits <11> Ii; bits <11> Ii;
▲ Show 20 Lines • Show All 361 Lines • ▼ Show 20 Linesclass Enc_800e04 : OpcodeHexagon {
let Inst{7-1} = Ii{8-2}; let Inst{7-1} = Ii{8-2};
bits <4> Rs16; bits <4> Rs16;
let Inst{19-16} = Rs16{3-0}; let Inst{19-16} = Rs16{3-0};
bits <6> n1; bits <6> n1;
let Inst{28-28} = n1{5-5}; let Inst{28-28} = n1{5-5};
let Inst{25-22} = n1{4-1}; let Inst{25-22} = n1{4-1};
let Inst{13-13} = n1{0-0}; let Inst{13-13} = n1{0-0};
} }
class Enc_80296d : OpcodeHexagon {
bits <5> Rs32;
let Inst{12-8} = Rs32{4-0};
bits <5> Rtt32;
let Inst{20-16} = Rtt32{4-0};
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
class Enc_802dc0 : OpcodeHexagon { class Enc_802dc0 : OpcodeHexagon {
bits <1> Ii; bits <1> Ii;
let Inst{8-8} = Ii{0-0}; let Inst{8-8} = Ii{0-0};
bits <2> Qv4; bits <2> Qv4;
let Inst{23-22} = Qv4{1-0}; let Inst{23-22} = Qv4{1-0};
} }
class Enc_81ac1d : OpcodeHexagon { class Enc_81ac1d : OpcodeHexagon {
bits <24> Ii; bits <24> Ii;
let Inst{24-16} = Ii{23-15}; let Inst{24-16} = Ii{23-15};
let Inst{13-1} = Ii{14-2}; let Inst{13-1} = Ii{14-2};
} }
class Enc_8203bb : OpcodeHexagon { class Enc_8203bb : OpcodeHexagon {
bits <6> Ii; bits <6> Ii;
let Inst{12-7} = Ii{5-0}; let Inst{12-7} = Ii{5-0};
bits <8> II; bits <8> II;
let Inst{13-13} = II{7-7}; let Inst{13-13} = II{7-7};
let Inst{6-0} = II{6-0}; let Inst{6-0} = II{6-0};
bits <5> Rs32; bits <5> Rs32;
let Inst{20-16} = Rs32{4-0}; let Inst{20-16} = Rs32{4-0};
} }
class Enc_829a68 : OpcodeHexagon {
bits <1> Mu2;
let Inst{13-13} = Mu2{0-0};
bits <5> Vdd32;
let Inst{4-0} = Vdd32{4-0};
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
class Enc_830e5d : OpcodeHexagon { class Enc_830e5d : OpcodeHexagon {
bits <8> Ii; bits <8> Ii;
let Inst{12-5} = Ii{7-0}; let Inst{12-5} = Ii{7-0};
bits <8> II; bits <8> II;
let Inst{22-16} = II{7-1}; let Inst{22-16} = II{7-1};
let Inst{13-13} = II{0-0}; let Inst{13-13} = II{0-0};
bits <2> Pu4; bits <2> Pu4;
let Inst{24-23} = Pu4{1-0}; let Inst{24-23} = Pu4{1-0};
▲ Show 20 Lines • Show All 674 Lines • ▼ Show 20 Linesclass Enc_adf111 : OpcodeHexagon {
let Inst{1-0} = Qx4{1-0}; let Inst{1-0} = Qx4{1-0};
} }
class Enc_b00112 : OpcodeHexagon { class Enc_b00112 : OpcodeHexagon {
bits <5> Rss32; bits <5> Rss32;
let Inst{20-16} = Rss32{4-0}; let Inst{20-16} = Rss32{4-0};
bits <5> Rtt32; bits <5> Rtt32;
let Inst{12-8} = Rtt32{4-0}; let Inst{12-8} = Rtt32{4-0};
} }
class Enc_b025d6 : OpcodeHexagon {
bits <3> Ii;
let Inst{10-8} = Ii{2-0};
bits <5> Vss32;
let Inst{4-0} = Vss32{4-0};
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
class Enc_b05839 : OpcodeHexagon { class Enc_b05839 : OpcodeHexagon {
bits <7> Ii; bits <7> Ii;
let Inst{8-5} = Ii{6-3}; let Inst{8-5} = Ii{6-3};
bits <1> Mu2; bits <1> Mu2;
let Inst{13-13} = Mu2{0-0}; let Inst{13-13} = Mu2{0-0};
bits <5> Rdd32; bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0}; let Inst{4-0} = Rdd32{4-0};
bits <5> Rx32; bits <5> Rx32;
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Linesclass Enc_b97f71 : OpcodeHexagon {
let Inst{8-5} = Ii{5-2}; let Inst{8-5} = Ii{5-2};
bits <2> Pt4; bits <2> Pt4;
let Inst{10-9} = Pt4{1-0}; let Inst{10-9} = Pt4{1-0};
bits <5> Rd32; bits <5> Rd32;
let Inst{4-0} = Rd32{4-0}; let Inst{4-0} = Rd32{4-0};
bits <5> Rx32; bits <5> Rx32;
let Inst{20-16} = Rx32{4-0}; let Inst{20-16} = Rx32{4-0};
} }
class Enc_b98b95 : OpcodeHexagon {
bits <4> Ii;
let Inst{13-13} = Ii{3-3};
let Inst{10-8} = Ii{2-0};
bits <5> Rt32;
let Inst{20-16} = Rt32{4-0};
bits <5> Vss32;
let Inst{4-0} = Vss32{4-0};
}
class Enc_b9c5fb : OpcodeHexagon { class Enc_b9c5fb : OpcodeHexagon {
bits <5> Rss32; bits <5> Rss32;
let Inst{20-16} = Rss32{4-0}; let Inst{20-16} = Rss32{4-0};
bits <5> Rdd32; bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0}; let Inst{4-0} = Rdd32{4-0};
} }
class Enc_bc03e5 : OpcodeHexagon { class Enc_bc03e5 : OpcodeHexagon {
bits <17> Ii; bits <17> Ii;
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Linesclass Enc_c85e2a : OpcodeHexagon {
bits <5> Ii; bits <5> Ii;
let Inst{12-8} = Ii{4-0}; let Inst{12-8} = Ii{4-0};
bits <5> II; bits <5> II;
let Inst{22-21} = II{4-3}; let Inst{22-21} = II{4-3};
let Inst{7-5} = II{2-0}; let Inst{7-5} = II{2-0};
bits <5> Rd32; bits <5> Rd32;
let Inst{4-0} = Rd32{4-0}; let Inst{4-0} = Rd32{4-0};
} }
class Enc_c89067 : OpcodeHexagon {
bits <5> Rtt32;
let Inst{20-16} = Rtt32{4-0};
bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0};
bits <5> Rx32;
let Inst{12-8} = Rx32{4-0};
}
class Enc_c90aca : OpcodeHexagon { class Enc_c90aca : OpcodeHexagon {
bits <8> Ii; bits <8> Ii;
let Inst{12-5} = Ii{7-0}; let Inst{12-5} = Ii{7-0};
bits <5> Rs32; bits <5> Rs32;
let Inst{20-16} = Rs32{4-0}; let Inst{20-16} = Rs32{4-0};
bits <5> Rx32; bits <5> Rx32;
let Inst{4-0} = Rx32{4-0}; let Inst{4-0} = Rx32{4-0};
} }
▲ Show 20 Lines • Show All 698 Lines • ▼ Show 20 Lines
class Enc_fb6577 : OpcodeHexagon { class Enc_fb6577 : OpcodeHexagon {
bits <2> Pu4; bits <2> Pu4;
let Inst{9-8} = Pu4{1-0}; let Inst{9-8} = Pu4{1-0};
bits <5> Rs32; bits <5> Rs32;
let Inst{20-16} = Rs32{4-0}; let Inst{20-16} = Rs32{4-0};
bits <5> Rd32; bits <5> Rd32;
let Inst{4-0} = Rd32{4-0}; let Inst{4-0} = Rd32{4-0};
} }
class Enc_fc4562 : OpcodeHexagon {
bits <5> Rs32;
let Inst{12-8} = Rs32{4-0};
bits <5> Rtt32;
let Inst{20-16} = Rtt32{4-0};
bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0};
}
class Enc_fcf7a7 : OpcodeHexagon { class Enc_fcf7a7 : OpcodeHexagon {
bits <5> Rss32; bits <5> Rss32;
let Inst{20-16} = Rss32{4-0}; let Inst{20-16} = Rss32{4-0};
bits <5> Rtt32; bits <5> Rtt32;
let Inst{12-8} = Rtt32{4-0}; let Inst{12-8} = Rtt32{4-0};
bits <2> Pd4; bits <2> Pd4;
let Inst{1-0} = Pd4{1-0}; let Inst{1-0} = Pd4{1-0};
} }
Show All 25 Lines

llvm/lib/Target/Hexagon/HexagonInstrFormats.td

Show First 20 Lines • Show All 330 Lines • ▼ Show 20 Linesclass InstDuplex<bits<4> iClass, string cstr = ""> : Instruction,
bits<2> opExtentAlign = 0; bits<2> opExtentAlign = 0;
let TSFlags{29-28} = opExtentAlign; // Alignment exponent before extending. let TSFlags{29-28} = opExtentAlign; // Alignment exponent before extending.
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction Classes Definitions - // Instruction Classes Definitions -
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "HexagonInstrFormatsV60.td"
include "HexagonInstrFormatsV65.td" include "HexagonInstrFormatsV65.td"

llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td

  • This file was deleted.
//==- HexagonInstrFormatsV60.td - Hexagon Instruction Formats -*- tablegen -==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the Hexagon V60 instruction classes in TableGen format.
//
//===----------------------------------------------------------------------===//
//----------------------------------------------------------------------------//
// Instruction Classes Definitions +
//----------------------------------------------------------------------------//
class CVI_VA_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = CVI_VA>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
OpcodeHexagon, Requires<[HasV60, UseHVX]>;

llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td

Show All 14 Lines
// //
// *** Must match BaseInfo.h *** // *** Must match BaseInfo.h ***
//----------------------------------------------------------------------------// //----------------------------------------------------------------------------//
//----------------------------------------------------------------------------// //----------------------------------------------------------------------------//
// Instruction Classes Definitions + // Instruction Classes Definitions +
//----------------------------------------------------------------------------// //----------------------------------------------------------------------------//
class CVI_VA_Resource_NoOpcode<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = CVI_VA>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>;
class CVI_GATHER_TMP_LD_Resource_NoOpcode<dag outs, dag ins, string asmstr, class CVI_GATHER_TMP_LD_Resource_NoOpcode<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "", list<dag> pattern = [], string cstr = "",
InstrItinClass itin = CVI_GATHER_PSEUDO> InstrItinClass itin = CVI_GATHER_PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_GATHER>; : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_GATHER>;

llvm/lib/Target/Hexagon/HexagonInstrInfo.h

Show First 20 Lines • Show All 416 Lines • ▼ Show 20 Linespublic:
bool addLatencyToSchedule(const MachineInstr &MI1, bool addLatencyToSchedule(const MachineInstr &MI1,
const MachineInstr &MI2) const; const MachineInstr &MI2) const;
bool canExecuteInBundle(const MachineInstr &First, bool canExecuteInBundle(const MachineInstr &First,
const MachineInstr &Second) const; const MachineInstr &Second) const;
bool doesNotReturn(const MachineInstr &CallMI) const; bool doesNotReturn(const MachineInstr &CallMI) const;
bool hasEHLabel(const MachineBasicBlock *B) const; bool hasEHLabel(const MachineBasicBlock *B) const;
bool hasNonExtEquivalent(const MachineInstr &MI) const; bool hasNonExtEquivalent(const MachineInstr &MI) const;
bool hasPseudoInstrPair(const MachineInstr &MI) const;
bool hasUncondBranch(const MachineBasicBlock *B) const; bool hasUncondBranch(const MachineBasicBlock *B) const;
bool mayBeCurLoad(const MachineInstr &MI) const; bool mayBeCurLoad(const MachineInstr &MI) const;
bool mayBeNewStore(const MachineInstr &MI) const; bool mayBeNewStore(const MachineInstr &MI) const;
bool producesStall(const MachineInstr &ProdMI, bool producesStall(const MachineInstr &ProdMI,
const MachineInstr &ConsMI) const; const MachineInstr &ConsMI) const;
bool producesStall(const MachineInstr &MI, bool producesStall(const MachineInstr &MI,
MachineBasicBlock::const_instr_iterator MII) const; MachineBasicBlock::const_instr_iterator MII) const;
bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const; bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const;
Show All 16 Linespublic:
int getDotNewOp(const MachineInstr &MI) const; int getDotNewOp(const MachineInstr &MI) const;
int getDotNewPredJumpOp(const MachineInstr &MI, int getDotNewPredJumpOp(const MachineInstr &MI,
const MachineBranchProbabilityInfo *MBPI) const; const MachineBranchProbabilityInfo *MBPI) const;
int getDotNewPredOp(const MachineInstr &MI, int getDotNewPredOp(const MachineInstr &MI,
const MachineBranchProbabilityInfo *MBPI) const; const MachineBranchProbabilityInfo *MBPI) const;
int getDotOldOp(const MachineInstr &MI) const; int getDotOldOp(const MachineInstr &MI) const;
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
const; const;
short getEquivalentHWInstr(const MachineInstr &MI) const;
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
const MachineInstr &MI) const; const MachineInstr &MI) const;
bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const; bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
unsigned getInvertedPredicatedOpcode(const int Opc) const; unsigned getInvertedPredicatedOpcode(const int Opc) const;
int getMaxValue(const MachineInstr &MI) const; int getMaxValue(const MachineInstr &MI) const;
unsigned getMemAccessSize(const MachineInstr &MI) const; unsigned getMemAccessSize(const MachineInstr &MI) const;
int getMinValue(const MachineInstr &MI) const; int getMinValue(const MachineInstr &MI) const;
short getNonExtOpcode(const MachineInstr &MI) const; short getNonExtOpcode(const MachineInstr &MI) const;
bool getPredReg(ArrayRef<MachineOperand> Cond, Register &PredReg, bool getPredReg(ArrayRef<MachineOperand> Cond, Register &PredReg,
unsigned &PredRegPos, unsigned &PredRegFlags) const; unsigned &PredRegPos, unsigned &PredRegFlags) const;
short getPseudoInstrPair(const MachineInstr &MI) const;
short getRegForm(const MachineInstr &MI) const; short getRegForm(const MachineInstr &MI) const;
unsigned getSize(const MachineInstr &MI) const; unsigned getSize(const MachineInstr &MI) const;
uint64_t getType(const MachineInstr &MI) const; uint64_t getType(const MachineInstr &MI) const;
InstrStage::FuncUnits getUnits(const MachineInstr &MI) const; InstrStage::FuncUnits getUnits(const MachineInstr &MI) const;
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const; MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const;
/// getInstrTimingClassLatency - Compute the instruction latency of a given /// getInstrTimingClassLatency - Compute the instruction latency of a given
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

Show First 20 Lines • Show All 3,120 Lines • ▼ Show 20 Lines if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
} }
if (NonExtOpcode < 0) if (NonExtOpcode < 0)
return false; return false;
return true; return true;
} }
return false; return false;
} }
bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
return Hexagon::getRealHWInstr(MI.getOpcode(),
Hexagon::InstrType_Pseudo) >= 0;
}
bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B) bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
const { const {
MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end(); MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
while (I != E) { while (I != E) {
if (I->isBarrier()) if (I->isBarrier())
return true; return true;
++I; ++I;
} }
▲ Show 20 Lines • Show All 1,123 Lines • ▼ Show 20 Lines case Hexagon::dup_A2_zxth:
if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg)) if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
return HexagonII::HSIG_A; return HexagonII::HSIG_A;
break; break;
} }
return HexagonII::HSIG_None; return HexagonII::HSIG_None;
} }
short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
}
unsigned HexagonInstrInfo::getInstrTimingClassLatency( unsigned HexagonInstrInfo::getInstrTimingClassLatency(
const InstrItineraryData *ItinData, const MachineInstr &MI) const { const InstrItineraryData *ItinData, const MachineInstr &MI) const {
// Default to one cycle for no itinerary. However, an "empty" itinerary may // Default to one cycle for no itinerary. However, an "empty" itinerary may
// still have a MinLatency property, which getStageLatency checks. // still have a MinLatency property, which getStageLatency checks.
if (!ItinData) if (!ItinData)
return getInstrLatency(ItinData, MI); return getInstrLatency(ItinData, MI);
if (MI.isTransient()) if (MI.isTransient())
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesbool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
PredRegFlags = 0; PredRegFlags = 0;
if (Cond[1].isImplicit()) if (Cond[1].isImplicit())
PredRegFlags = RegState::Implicit; PredRegFlags = RegState::Implicit;
if (Cond[1].isUndef()) if (Cond[1].isUndef())
PredRegFlags |= RegState::Undef; PredRegFlags |= RegState::Undef;
return true; return true;
} }
short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
}
short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const { short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
return Hexagon::getRegForm(MI.getOpcode()); return Hexagon::getRegForm(MI.getOpcode());
} }
// Return the number of bytes required to encode the instruction. // Return the number of bytes required to encode the instruction.
// Hexagon instructions are fixed length, 4 bytes, unless they // Hexagon instructions are fixed length, 4 bytes, unless they
// use a constant extender, which requires another 4 bytes. // use a constant extender, which requires another 4 bytes.
// For debug instructions and prolog labels, return 0. // For debug instructions and prolog labels, return 0.
▲ Show 20 Lines • Show All 196 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonPatterns.td

Show First 20 Lines • Show All 336 Lines • ▼ Show 20 Linesclass AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
: Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)), : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)),
(MI RegPred:$Rx, RegPred:$Rs, imm:$I)>; (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>;
class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
PatFrag RxPred, PatFrag RsPred, PatFrag RtPred> PatFrag RxPred, PatFrag RsPred, PatFrag RtPred>
: Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)), : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
(MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>; (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val,
InstHexagon InstA, InstHexagon InstB> {
def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B),
(InstA Val:$A, Val:$B)>;
def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A),
(InstB Val:$A, Val:$B)>;
}
multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS, multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS,
SDPatternOperator Sel, SDPatternOperator CmpOp, SDPatternOperator Sel, SDPatternOperator CmpOp,
ValueType CmpType, PatFrag CmpPred> { ValueType CmpType, PatFrag CmpPred> {
def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)),
CmpPred:$Vt, CmpPred:$Vs), CmpPred:$Vt, CmpPred:$Vs),
(PickT CmpPred:$Vs, CmpPred:$Vt)>; (PickT CmpPred:$Vs, CmpPred:$Vt)>;
def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)),
CmpPred:$Vs, CmpPred:$Vt), CmpPred:$Vs, CmpPred:$Vt),
▲ Show 20 Lines • Show All 3,067 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonRegisterInfo.td

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lineslet Namespace = "Hexagon" in {
// Rp - false/pseudo registers. These registers are used // Rp - false/pseudo registers. These registers are used
// to provide a distinct set of aliases for both styles of vector // to provide a distinct set of aliases for both styles of vector
// register pairs without encountering subregister indexing constraints. // register pairs without encountering subregister indexing constraints.
class R_fake<string n> : class R_fake<string n> :
HexagonFakeReg<n>; HexagonFakeReg<n>;
// Rf - 32-bit floating-point registers.
class Rf<bits<5> num, string n> : HexagonReg<num, n>;
// Rd - 64-bit registers. // Rd - 64-bit registers.
class Rd<bits<5> num, string n, list<Register> subregs, class Rd<bits<5> num, string n, list<Register> subregs,
list<string> alt = []> : list<string> alt = []> :
HexagonDoubleReg<num, n, subregs, alt> { HexagonDoubleReg<num, n, subregs, alt> {
let SubRegs = subregs; let SubRegs = subregs;
} }
// Rp - predicate registers // Rp - predicate registers
Show All 24 Lineslet Namespace = "Hexagon" in {
// Rss - 64-bit system registers. // Rss - 64-bit system registers.
class Rss<bits<7> num, string n, list<Register> subregs, class Rss<bits<7> num, string n, list<Register> subregs,
list<string> alt = []> : list<string> alt = []> :
HexagonDoubleSys<num, n, subregs, alt> { HexagonDoubleSys<num, n, subregs, alt> {
let SubRegs = subregs; let SubRegs = subregs;
} }
// Mx - address modifier registers
class Mx<bits<1> num, string n> : Register<n, []> {
let HWEncoding{0} = num;
}
// Rg - Guest/Hypervisor registers // Rg - Guest/Hypervisor registers
class Rg<bits<5> num, string n, class Rg<bits<5> num, string n,
list<string> alt = [], list<Register> alias = []> : list<string> alt = [], list<Register> alias = []> :
HexagonReg<num, n, alt, alias>; HexagonReg<num, n, alt, alias>;
// Rgg - 64-bit Guest/Hypervisor registers // Rgg - 64-bit Guest/Hypervisor registers
class Rgg<bits<5> num, string n, list<Register> subregs> : class Rgg<bits<5> num, string n, list<Register> subregs> :
HexagonDoubleReg<num, n, subregs> { HexagonDoubleReg<num, n, subregs> {
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llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td