[ARM] Remove unused TableGen classes and multiclasses.

[kosarev]

Summary

And warn on them from now on.

llvm/lib/Target/ARM/ARMInstrFormats.td

 
 // Misc flags.
 
 // The instruction has an Rn register operand.
 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
 // it doesn't have a Rn operand.
 class UnaryDP    { bit isUnaryDataProc = 1; }
 
-// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
-// a 16-bit Thumb instruction if certain conditions are met.
-class Xform16Bit { bit canXformTo16Bit = 1; }
-
 //===----------------------------------------------------------------------===//
 // ARM Instruction flags.  These need to match ARMBaseInstrInfo.h.
 //
 
 // FIXME: Once the JIT is MC-ized, these can go away.
 // Addressing mode.
 class AddrMode<bits<5> val> {
   bits<5> Value = val;

 }
 
 class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
   : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
 class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
   : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
 class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
   : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
-class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
-  : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
-class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)>
-  : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>;
-class MVEAsmPseudo<string asm, dag iops, dag oops = (outs)>
-  : AsmPseudoInst<asm, iops, oops>, Requires<[HasMVEInt]>;
 
 // Pseudo instructions for the code generator.
 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
   : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
                  GenericDomain, "", itin> {
   let OutOperandList = oops;
   let InOperandList = iops;
   let Pattern = pattern;
class XI<dag oops, dag iops, AddrMode am, int sz,
   let Pattern = pattern;
   list<Predicate> Predicates = [IsARM];
 }
 
 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
          string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
       opc, asm, "", pattern>;
-class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
-          string opc, string asm, list<dag> pattern>
-  : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
-       opc, asm, "", pattern>;
 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
           string asm, list<dag> pattern>
   : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
        asm, "", pattern>;
 class AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin,
           string asm, list<dag> pattern>
   : XI<oops, iops, am, 4, IndexModeNone, f, itin,
        asm, "", pattern>;

 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
            string asm, list<dag> pattern>
   : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
        asm, "", pattern> {
   let Inst{27-24} = opcod;
 }
 
 // BR_JT instructions
-class JTI<dag oops, dag iops, InstrItinClass itin,
-          string asm, list<dag> pattern>
-  : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
-       asm, "", pattern>;
-
 class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
               string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
       opc, asm, "", pattern> {
   bits<4> Rt;
   bits<4> addr;
   let Inst{27-23} = 0b00011;
   let Inst{22-21} = opcod;

 }
 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
        opc, asm, "", pattern> {
   let Inst{24-21} = opcod;
   let Inst{27-26} = 0b00;
 }
-class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
-           string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
-       asm, "", pattern> {
-  let Inst{24-21} = opcod;
-  let Inst{27-26} = 0b00;
-}
 
 // loads
 
 // LDR/LDRB/STR/STRB/...
 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
              Format f, InstrItinClass itin, string opc, string asm,
              list<dag> pattern>
   : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
   bits<4> Rt;
   let Inst{27-26} = 0b01;
   let Inst{24}    = isPre; // P bit
   let Inst{22}    = isByte; // B bit
   let Inst{21}    = isPre; // W bit
   let Inst{20}    = isLd; // L bit
   let Inst{15-12} = Rt;
 }
-class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
-                IndexMode im, Format f, InstrItinClass itin, string opc,
-                string asm, string cstr, list<dag> pattern>
-  : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
-               pattern> {
-  // AM2 store w/ two operands: (GPR, am2offset)
-  // {12}     isAdd
-  // {11-0}   imm12/Rm
-  bits<14> offset;
-  bits<4> Rn;
-  let Inst{25} = 1;
-  let Inst{23} = offset{12};
-  let Inst{19-16} = Rn;
-  let Inst{11-5} = offset{11-5};
-  let Inst{4} = 0;
-  let Inst{3-0} = offset{3-0};
-}
-
-class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
-                IndexMode im, Format f, InstrItinClass itin, string opc,
-                string asm, string cstr, list<dag> pattern>
-  : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
-               pattern> {
-  // AM2 store w/ two operands: (GPR, am2offset)
-  // {12}     isAdd
-  // {11-0}   imm12/Rm
-  bits<14> offset;
-  bits<4> Rn;
-  let Inst{25} = 0;
-  let Inst{23} = offset{12};
-  let Inst{19-16} = Rn;
-  let Inst{11-0} = offset{11-0};
-}
 
 
-// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
-// but for now use this class for STRT and STRBT.
-class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
-                IndexMode im, Format f, InstrItinClass itin, string opc,
-                string asm, string cstr, list<dag> pattern>
-  : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
-               pattern> {
-  // AM2 store w/ two operands: (GPR, am2offset)
-  // {17-14}  Rn
-  // {13}     1 == Rm, 0 == imm12
-  // {12}     isAdd
-  // {11-0}   imm12/Rm
-  bits<18> addr;
-  let Inst{25} = addr{13};
-  let Inst{23} = addr{12};
-  let Inst{19-16} = addr{17-14};
-  let Inst{11-0} = addr{11-0};
-}
-
 // addrmode3 instructions
 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
             InstrItinClass itin, string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
       opc, asm, "", pattern> {
   bits<14> addr;
   bits<4> Rt;
   let Inst{27-25} = 0b000;
class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
            list<dag> pattern>
     : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
       Encoding {
   let Inst{31-27} = opcod1;
   let Inst{15-14} = opcod2;
   let Inst{12}    = opcod3;
 }
 
-// BR_JT instructions
-class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
-           list<dag> pattern>
-  : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
-
 // Thumb1 only
 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
               InstrItinClass itin, string asm, string cstr, list<dag> pattern>
   : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
   let OutOperandList = oops;
   let InOperandList = iops;
   let AsmString = asm;
   let Pattern = pattern;
   list<Predicate> Predicates = [IsThumb, IsThumb1Only];
 }
 
 class T1I<dag oops, dag iops, InstrItinClass itin,
           string asm, list<dag> pattern>
   : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
-class T1Ix2<dag oops, dag iops, InstrItinClass itin,
-            string asm, list<dag> pattern>
-  : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
-
-// Two-address instructions
-class T1It<dag oops, dag iops, InstrItinClass itin,
-           string asm, string cstr, list<dag> pattern>
-  : Thumb1I<oops, iops, AddrModeNone, 2, itin,
-            asm, cstr, pattern>;
 
 // Thumb1 instruction that can either be predicated or set CPSR.
 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
                InstrItinClass itin,
                string opc, string asm, string cstr, list<dag> pattern>
   : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
   let OutOperandList = !con(oops, (outs s_cc_out:$s));
   let InOperandList = !con(iops, (ins pred:$p));

 
 class T2sI<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
 
 class T2XI<dag oops, dag iops, InstrItinClass itin,
            string asm, list<dag> pattern>
   : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
-class T2JTI<dag oops, dag iops, InstrItinClass itin,
-            string asm, list<dag> pattern>
-  : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
 
 // Move to/from coprocessor instructions
 class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm,
             list<dag> pattern>
   : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> {
   let Inst{31-28} = opc;
 }
 

llvm/lib/Target/ARM/ARMInstrNEON.td

 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
 def VSTMQIA
   : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
                     IIC_fpStore_m, "",
                    [(word_alignedstore (v2f64 DPair:$src), GPR:$Rn)]>;
 
 // Classes for VLD* pseudo-instructions with multi-register operands.
 // These are expanded to real instructions after register allocation.
-class VLDQPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
-class VLDQWBPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
-                (ins addrmode6:$addr, am6offset:$offset), itin,
-                "$addr.addr = $wb">;
-class VLDQWBfixedPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
-                (ins addrmode6:$addr), itin,
-                "$addr.addr = $wb">;
-class VLDQWBregisterPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
-                (ins addrmode6:$addr, rGPR:$offset), itin,
-                "$addr.addr = $wb">;
-
 class VLDQQPseudo<InstrItinClass itin>
   : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
 class VLDQQWBPseudo<InstrItinClass itin>
   : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
                 (ins addrmode6:$addr, am6offset:$offset), itin,
                 "$addr.addr = $wb">;
 class VLDQQWBfixedPseudo<InstrItinClass itin>
   : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),

 def VLD4DUPq32OddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4dupu>, Sched<[WriteVLD2]>;
 
 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
 
 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
 
 // Classes for VST* pseudo-instructions with multi-register operands.
 // These are expanded to real instructions after register allocation.
-class VSTQPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
-class VSTQWBPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs GPR:$wb),
-                (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
-                "$addr.addr = $wb">;
-class VSTQWBfixedPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs GPR:$wb),
-                (ins addrmode6:$addr, QPR:$src), itin,
-                "$addr.addr = $wb">;
-class VSTQWBregisterPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs GPR:$wb),
-                (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
-                "$addr.addr = $wb">;
 class VSTQQPseudo<InstrItinClass itin>
   : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
 class VSTQQWBPseudo<InstrItinClass itin>
   : PseudoNLdSt<(outs GPR:$wb),
                 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
                 "$addr.addr = $wb">;
 class VSTQQWBfixedPseudo<InstrItinClass itin>
   : PseudoNLdSt<(outs GPR:$wb),
multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
                         InstrItinClass itin, string OpcodeStr, string Dt,
                         SDPatternOperator IntOp> {
   def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
                           OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
   def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
                         OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
 }
 
-// ....then also with element size of 8 bits:
-multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
-                       InstrItinClass itin16, InstrItinClass itin32,
-                       string OpcodeStr, string Dt,
-                       SDPatternOperator IntOp, bit Commutable = 0>
-  : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
-               IntOp, Commutable> {
-  def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
-                      OpcodeStr, !strconcat(Dt, "8"),
-                      v8i16, v8i8, IntOp, Commutable>;
-}
-
 // ....with explicit extend (VABDL).
 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
                        InstrItinClass itin, string OpcodeStr, string Dt,
                        SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
   def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
                          OpcodeStr, !strconcat(Dt, "8"),
                          v8i16, v8i8, IntOp, ExtOp, Commutable>;
   def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
multiclass N3VInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
 
   // 128-bit vector types.
   def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ16,
                        OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
   def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ32,
                        OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
 }
 
-//   element sizes of 8, 16 and 32 bits:
-multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
-                       InstrItinClass itinD16, InstrItinClass itinD32,
-                       InstrItinClass itinQ16, InstrItinClass itinQ32,
-                       string OpcodeStr, string Dt, SDPatternOperator IntOp>
-           :N3VInt3_HS <op24, op23, op11_8, op4, itinD16, itinD32,
-                        itinQ16, itinQ32, OpcodeStr, Dt, IntOp>{
-  // 64-bit vector types.
-  def v8i8  : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD16,
-                       OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
-  // 128-bit vector types.
-  def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ16,
-                       OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
-}
-
 // Neon Long Multiply-Op vector operations,
 //   element sizes of 8, 16 and 32 bits:
 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
                          InstrItinClass itin16, InstrItinClass itin32,
                          string OpcodeStr, string Dt, SDNode MulOp,
                          SDNode OpNode> {
   def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
                         !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;

 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
                          string OpcodeStr, string Dt, SDPatternOperator IntOp> {
   def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
                            OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
   def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
                          OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
 }
 
-// ....then also with element size of 8 bits:
-multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
-                        InstrItinClass itin16, InstrItinClass itin32,
-                        string OpcodeStr, string Dt, SDPatternOperator IntOp>
-  : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
-  def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
-                       OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
-}
-
 // ....with explicit extend (VABAL).
 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
                             InstrItinClass itin, string OpcodeStr, string Dt,
                             SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
   def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
                            OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
                            IntOp, ExtOp, OpNode>;
   def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,

llvm/lib/Target/ARM/ARMInstrThumb2.td

 def pred_noal_inv : Operand<i32> {
   let PrintMethod = "printMandatoryInvertedPredicateOperand";
   let ParserMatchClass = pred_noal_inv_asmoperand;
 }
 //===----------------------------------------------------------------------===//
 // Multiclass helpers...
 //
 
-
-class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
-           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
-  bits<4> Rd;
-  bits<12> imm;
-
-  let Inst{11-8}  = Rd;
-  let Inst{26}    = imm{11};
-  let Inst{14-12} = imm{10-8};
-  let Inst{7-0}   = imm{7-0};
-}
-
-
 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : T2sI<oops, iops, itin, opc, asm, pattern> {
   bits<4> Rd;
   bits<4> Rn;
   bits<12> imm;
 
   let Inst{11-8}  = Rd;
class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
 
   let Inst{19-16}  = Rn;
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
   let Inst{7-0}   = imm{7-0};
 }
 
 
-class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
-           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
-  bits<4> Rd;
-  bits<12> ShiftedRm;
-
-  let Inst{11-8}  = Rd;
-  let Inst{3-0}   = ShiftedRm{3-0};
-  let Inst{5-4}   = ShiftedRm{6-5};
-  let Inst{14-12} = ShiftedRm{11-9};
-  let Inst{7-6}   = ShiftedRm{8-7};
-}
-
 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : T2sI<oops, iops, itin, opc, asm, pattern> {
   bits<4> Rd;
   bits<12> ShiftedRm;
 
   let Inst{11-8}  = Rd;
   let Inst{3-0}   = ShiftedRm{3-0};
class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<4> Rm;
 
   let Inst{19-16} = Rn;
   let Inst{3-0}   = Rm;
 }
 
 
-class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
-           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> imm;
-
-  let Inst{11-8}  = Rd;
-  let Inst{19-16} = Rn;
-  let Inst{26}    = imm{11};
-  let Inst{14-12} = imm{10-8};
-  let Inst{7-0}   = imm{7-0};
-}
-
 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : T2sI<oops, iops, itin, opc, asm, pattern> {
   bits<4> Rd;
   bits<4> Rn;
   bits<12> imm;
 
   let Inst{11-8}  = Rd;
class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<4> Rm;
 
   let Inst{11-8}  = Rd;
   let Inst{19-16} = Rn;
   let Inst{3-0}   = Rm;
 }
 
-class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
-           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> ShiftedRm;
-
-  let Inst{11-8}  = Rd;
-  let Inst{19-16} = Rn;
-  let Inst{3-0}   = ShiftedRm{3-0};
-  let Inst{5-4}   = ShiftedRm{6-5};
-  let Inst{14-12} = ShiftedRm{11-9};
-  let Inst{7-6}   = ShiftedRm{8-7};
-}
-
 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : T2sI<oops, iops, itin, opc, asm, pattern> {
   bits<4> Rd;
   bits<4> Rn;
   bits<12> ShiftedRm;
 
   let Inst{11-8}  = Rd;

llvm/lib/Target/ARM/CMakeLists.txt

 add_llvm_component_group(ARM HAS_JIT)
 
 set(LLVM_TARGET_DEFINITIONS ARM.td)
 
 tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel -warn-on-unused-entities)
 tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM ARMGenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM ARMGenSystemRegister.inc -gen-searchable-tables)