[Sparc] Remove unused TableGen classes and multiclasses.

[kosarev]

Summary

And warn on them from now on.

[koakuma]

This looks okay to me, at least.

llvm/lib/Target/Sparc/CMakeLists.txt

 add_llvm_component_group(Sparc)
 
 set(LLVM_TARGET_DEFINITIONS Sparc.td)
 
 tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel -warn-on-unused-entities)
 tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(SparcCommonTableGen)
 

llvm/lib/Target/Sparc/SparcInstr64Bit.td

multiclass BranchOnReg<list<dag> CCPattern> {
   def RA   : F2_4<1, 1, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),
              "br$rcond,a $rs1, $imm16", []>;
   def RNT  : F2_4<0, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),
              "br$rcond,pn $rs1, $imm16", []>;
   def RANT : F2_4<1, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),
              "br$rcond,a,pn $rs1, $imm16", []>;
 }
 
-multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
-  def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
-                  (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
-  def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
-                  (APT I64Regs:$rs1, bprtarget16:$imm16), 0>;
-}
-
 let Predicates = [Is64Bit] in
   defm BP : BranchOnReg<[(SPbrreg bb:$imm16, imm:$rcond, i64:$rs1)]>;
 
 // Move integer register on register condition (MOVr).
 let Predicates = [Is64Bit], Constraints = "$f = $rd" in {
   def MOVRrr : F4_4r<0b101111, 0b00000, (outs IntRegs:$rd),
                    (ins I64Regs:$rs1, IntRegs:$rs2, IntRegs:$f, RegCCOp:$rcond),
                    "movr$rcond $rs1, $rs2, $rd",

llvm/lib/Target/Sparc/SparcInstrInfo.td

 
 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
 // Section A.7 - Branch on Integer Condition Codes with Prediction (SPARC v9)
 
 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
 // unconditional branch class.
 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
   : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
-
-// Same as BranchAlways but uses the new v9 encoding
-class BranchPredictAlways<dag ins, string asmstr, list<dag> pattern>
-  : F2_3<0b001, 0, 1, (outs), ins, asmstr, pattern>;
 }
 
 let cond = 8 in
   def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
 
 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
 
 // conditional branch class: