[RISCV] Begin removing hasDummyMask.

[craig.topper]

Summary

This was used to know if we need to insert a dummy operand during
MCInstLowering. We can use the operand info from MCInstrDesc to
figure this out without needing a separate flag.

I'll remove the tablegen bits if there is consensus this is a good
idea.

[frasercrmck]

Makes sense to me as an approach.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

3210

this comment's mis-formatted

llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

226 ↗

(On Diff #528066)

This could maybe be a bit safer? If OutMI had more operands than the MCID accounts for, this access would do bad things.

Maybe rejigging that following assert so that it first asserts that OutMI has one fewer operand than OutMCID? That doesn't negate the need for the later assert, if we're conditionally adding the extra operand. Maybe moving that later assert to just before the return statement as a more global check that we've done the right thing throughout the course of the function?

[craig.topper]

Address @frasercrmck's comment

[reames]

llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

226 ↗

(On Diff #528637)

You can reuse OutNumOperands here. Or remove it, and fold the call into it's single use. It's mostly the inconsistency which is odd.

227 ↗

(On Diff #528637)

I'm guessing this if should actually be an assert? If the RegClass didn't match, we'd fail the operand check just below.

Or alternatively, maybe reorganize the whole clause as:

if (OutMI.getNumOperands() + 1 == OutMCID.getNumOperands() &&
   OutMCID.operands()[OutNumOperands].RegClass == RISCV::VMV0RegClassID)
  OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister))

The single assert at the end of the function then covers all the other cases.

[craig.topper]

Rebase and address comments

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 /// \returns the format of the instruction.
 static inline unsigned getFormat(uint64_t TSFlags) {
   return (TSFlags & InstFormatMask) >> InstFormatShift;
 }
 /// \returns the LMUL for the instruction.
 static inline VLMUL getLMul(uint64_t TSFlags) {
   return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
 }
-/// \returns true if there is a dummy mask operand for the instruction.
-static inline bool hasDummyMaskOp(uint64_t TSFlags) {
-  return TSFlags & HasDummyMaskOpMask;
-}
 /// \returns true if tail agnostic is enforced for the instruction.
 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
   return TSFlags & ForceTailAgnosticMask;
 }
 /// \returns true if there is a merge operand for the instruction.
 static inline bool hasMergeOp(uint64_t TSFlags) {
   return TSFlags & HasMergeOpMask;
 }

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
 
   OutMI.setOpcode(RVV->BaseInstr);
 
   const MachineBasicBlock *MBB = MI->getParent();
   assert(MBB && "MI expected to be in a basic block");
   const MachineFunction *MF = MBB->getParent();
   assert(MF && "MBB expected to be in a machine function");
 
-  const TargetRegisterInfo *TRI =
-      MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
-
+  const RISCVSubtarget &Subtarget = MF->getSubtarget<RISCVSubtarget>();
+  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   assert(TRI && "TargetRegisterInfo expected");
 
   uint64_t TSFlags = MI->getDesc().TSFlags;
   unsigned NumOps = MI->getNumExplicitOperands();
 
   // Skip policy, VL and SEW operands which are the last operands if present.
   if (RISCVII::hasVecPolicyOp(TSFlags))
     --NumOps;
case MachineOperand::MO_Immediate:
       MCOp = MCOperand::createImm(MO.getImm());
       break;
     }
     OutMI.addOperand(MCOp);
   }
 
   // Unmasked pseudo instructions need to append dummy mask operand to
   // V instructions. All V instructions are modeled as the masked version.
-  if (RISCVII::hasDummyMaskOp(TSFlags))
+  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
+  if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
+    assert(OutMCID.operands()[OutMI.getNumOperands()].RegClass ==
+               RISCV::VMV0RegClassID &&
+           "Expected only mask operand to be missing");
     OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
+  }
 
+  assert(OutMI.getNumOperands() == OutMCID.getNumOperands());
   return true;
 }
 
 bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
   if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
     return false;
 
   OutMI.setOpcode(MI->getOpcode());

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

if (I->UnmaskedTUPseudo == I->UnmaskedPseudo) {
           UseTUPseudo = true;
         }
       }
     }
   }
 
   unsigned Opc = UseTUPseudo ? I->UnmaskedTUPseudo : I->UnmaskedPseudo;
 
-  // Check that we're dropping the mask operand and any policy operand
-  // when we transform to this unmasked pseudo. Additionally, if this
-  // instruction is tail agnostic, the unmasked instruction should not have a
-  // tied destination.
+  // If this instruction is tail agnostic, the unmasked instruction should not
+  // have a tied destination.
 #ifndef NDEBUG
   const MCInstrDesc &MCID = TII.get(Opc);
   uint64_t TSFlags = MCID.TSFlags;
   bool HasTiedDest = RISCVII::isFirstDefTiedToFirstUse(MCID);
-  assert(UseTUPseudo == HasTiedDest && RISCVII::hasDummyMaskOp(TSFlags) &&
-         "Unexpected pseudo to transform to");
+  assert((UseTUPseudo == HasTiedDest) && "Unexpected pseudo to transform to");
 #endif
 
   SmallVector<SDValue, 8> Ops;
   // Skip the merge operand at index 0 if !UseTUPseudo.
   for (unsigned I = !UseTUPseudo, E = N->getNumOperands(); I != E; I++) {
     // Skip the mask, the policy, and the Glue.
     SDValue Op = N->getOperand(I);
     if (I == MaskOpIdx || I == TailPolicyOpIdx ||