[CodeGen] Rename `MachineInstr::defs` to `MachineInstr::explicit_defs` (NFC)

[barannikov88]

Summary

defs and uses are two misnomers that have a very high potential of introducing bugs.
This patch deals with defs by giving it a proper name explicit_defs.
It is more difficult to find an appropriate name for uses, leave it as it is for now.
(uses returns explicit uses plus all implicit operands, including implicit defs.)

[barannikov88]

Update SPIRV

[foad]

This makes a lot of sense to me.

It is more difficult to find an appropriate name for uses

Agreed. Maybe the solution is to remove uses? How "useful" is it? Can we migrate to operands and/or implicit_operands?

[barannikov88]

In D150868#4355621, @foad wrote:

This makes a lot of sense to me.

It is more difficult to find an appropriate name for uses

Agreed. Maybe the solution is to remove uses? How "useful" is it? Can we migrate to operands and/or implicit_operands?

I tried, but it is not always obvious from the context what would be the correct change.
I got the impression that you are familiar with AMDGPU (it is one of the main consumers of defs()/uses(), as the diff shows),
so maybe you could handle this part?

[foad]

In D150868#4355739, @barannikov88 wrote:

In D150868#4355621, @foad wrote:

This makes a lot of sense to me.

It is more difficult to find an appropriate name for uses

Agreed. Maybe the solution is to remove uses? How "useful" is it? Can we migrate to operands and/or implicit_operands?

I tried, but it is not always obvious from the context what would be the correct change.
I got the impression that you are familiar with AMDGPU (it is one of the main consumers of defs()/uses(), as the diff shows),
so maybe you could handle this part?

Sure, I can help, but I can't promise how much time I can spend on it.

I see this sort of pattern a few times:

for (auto &MO : I->uses()) {
  if (MO.isReg() && MO.isUse()) {
    MRI.clearKillFlags(MO.getReg());
  }
}

Here we could really use a proper uses (or maybe all_uses) iterator that does the filtering for us, so it returns all use operands and only the use operands.

Do you think it would be worth renaming the current uses to something ugly like uses_and_implicit_operands, in the hope of migrating all users to something less ugly and then removing it?

[barannikov88]

In D150868#4355814, @foad wrote:

Sure, I can help, but I can't promise how much time I can spend on it.

Thanks! There is no hurry.

I see this sort of pattern a few times:

for (auto &MO : I->uses()) {
  if (MO.isReg() && MO.isUse()) {
    MRI.clearKillFlags(MO.getReg());
  }
}

Here we could really use a proper uses (or maybe all_uses) iterator that does the filtering for us, so it returns all use operands and only the use operands.

Do you think it would be worth renaming the current uses to something ugly like uses_and_implicit_operands, in the hope of migrating all users to something less ugly and then removing it?

SGTM assuming we provide a replacement for cases where we only need uses (explicit + implicit).
uses() would be a natural choise for this, but changing its behavior silently will cause problems to downstream users.
Either some time should pass before we can re-introduce uses() or a different name should be picked (all_uses() sounds good to me as well).

BTW should uses() be deprecated instead of removed in this patch?

[foad]

In D150868#4355843, @barannikov88 wrote:

In D150868#4355814, @foad wrote:

Sure, I can help, but I can't promise how much time I can spend on it.

Thanks! There is no hurry.

I see this sort of pattern a few times:

for (auto &MO : I->uses()) {
  if (MO.isReg() && MO.isUse()) {
    MRI.clearKillFlags(MO.getReg());
  }
}

Here we could really use a proper uses (or maybe all_uses) iterator that does the filtering for us, so it returns all use operands and only the use operands.

Do you think it would be worth renaming the current uses to something ugly like uses_and_implicit_operands, in the hope of migrating all users to something less ugly and then removing it?

SGTM assuming we provide a replacement for cases where we only need uses (explicit + implicit).
uses() would be a natural choise for this, but changing its behavior silently will cause problems to downstream users.
Either some time should pass before we can re-introduce uses() or a different name should be picked (all_uses() sounds good to me as well).

BTW should uses() be deprecated instead of removed in this patch?

If we implement all_uses (and all_defs?) then maybe there is no need to rename uses after all. In the future hopefully we can deprecate and then remove it.

[barannikov88]

In D150868#4355880, @foad wrote:

If we implement all_uses (and all_defs?) then maybe there is no need to rename uses after all.

Good point.
I'll create a discourse topic to see how people feel about all_uses/all_defs.

[barannikov88]

RFC is here https://discourse.llvm.org/t/rfc-renaming-machineinstr-methods-returning-operand-ranges/70756

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

static void replaceRegOrBuildCopy(Register DstReg, Register SrcReg,
     // Notify the observer that we changed the instructions.
     for (auto *UseMI : UseMIs)
       Observer.changedInstr(*UseMI);
   }
 
   /// Return the operand index in \p MI that defines \p Def
   static unsigned getDefIndex(const MachineInstr &MI, Register SearchDef) {
     unsigned DefIdx = 0;
-    for (const MachineOperand &Def : MI.defs()) {
+    for (const MachineOperand &Def : MI.explicit_defs()) {
       if (Def.getReg() == SearchDef)
         break;
       ++DefIdx;
     }
 
     return DefIdx;
   }
 
Register findValueFromDefImpl(Register DefReg, unsigned StartBit,
       // For unmerge however with multiple defs, we need to compute the offset
       // into the source of the unmerge.
       switch (Def->getOpcode()) {
       case TargetOpcode::G_CONCAT_VECTORS:
         return findValueFromConcat(cast<GConcatVectors>(*Def), StartBit, Size);
       case TargetOpcode::G_UNMERGE_VALUES: {
         unsigned DefStartBit = 0;
         unsigned DefSize = MRI.getType(DefReg).getSizeInBits();
-        for (const auto &MO : Def->defs()) {
+        for (const auto &MO : Def->explicit_defs()) {
           if (MO.getReg() == DefReg)
             break;
           DefStartBit += DefSize;
         }
         Register SrcReg = Def->getOperand(Def->getNumOperands() - 1).getReg();
         Register SrcOriginReg =
             findValueFromDefImpl(SrcReg, StartBit + DefStartBit, Size);
         if (SrcOriginReg)
while (PrevMI != &DefMI) {
       } else
         break;
       PrevMI = TmpDef;
     }
 
     if (PrevMI == &DefMI) {
       unsigned I = 0;
       bool IsDead = true;
-      for (MachineOperand &Def : DefMI.defs()) {
+      for (MachineOperand &Def : DefMI.explicit_defs()) {
         if (I != DefIdx) {
           if (!MRI.use_empty(Def.getReg())) {
             IsDead = false;
             break;
           }
         } else {
           if (!MRI.hasOneUse(DefMI.getOperand(DefIdx).getReg()))
             break;

llvm/include/llvm/CodeGen/MachineInstr.h

public:
   }
   /// \copydoc debug_operands()
   iterator_range<const_mop_iterator> debug_operands() const {
     assert((isDebugValueLike()) && "Must be a debug value instruction.");
     return isNonListDebugValue()
                ? make_range(operands_begin(), operands_begin() + 1)
                : make_range(operands_begin() + 2, operands_end());
   }
-  /// Returns a range over all explicit operands that are register definitions.
-  /// Implicit definition are not included!
-  iterator_range<mop_iterator> defs() {
-    return make_range(operands_begin(),
-                      operands_begin() + getNumExplicitDefs());
-  }
-  /// \copydoc defs()
-  iterator_range<const_mop_iterator> defs() const {
-    return make_range(operands_begin(),
-                      operands_begin() + getNumExplicitDefs());
-  }
   /// Returns a range that includes all operands that are register uses.
   /// This may include unrelated operands which are not register uses.
   iterator_range<mop_iterator> uses() {
     return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
   }
   /// \copydoc uses()
   iterator_range<const_mop_iterator> uses() const {
     return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
   }
+
+  /// Returns a range over all explicit operands that are register definitions.
+  iterator_range<mop_iterator> explicit_defs() {
+    return make_range(operands_begin(),
+                      operands_begin() + getNumExplicitDefs());
+  }
+
+  /// \copydoc explicit_defs()
+  iterator_range<const_mop_iterator> explicit_defs() const {
+    return make_range(operands_begin(),
+                      operands_begin() + getNumExplicitDefs());
+  }
+
+  /// Returns a range over all explicit operands that are register uses.
   iterator_range<mop_iterator> explicit_uses() {
     return make_range(operands_begin() + getNumExplicitDefs(),
                       operands_begin() + getNumExplicitOperands());
   }
+
+  /// \copydoc explicit_uses()
   iterator_range<const_mop_iterator> explicit_uses() const {
     return make_range(operands_begin() + getNumExplicitDefs(),
                       operands_begin() + getNumExplicitOperands());
   }
 
   /// Returns the number of the operand iterator \p I points to.
   unsigned getOperandNo(const_mop_iterator I) const {
     return I - operands_begin();

llvm/lib/CodeGen/CodeGenCommonISel.cpp

 }
 
 static MachineOperand *getSalvageOpsForTrunc(const MachineRegisterInfo &MRI,
                                             MachineInstr &Trunc,
                                             SmallVectorImpl<uint64_t> &Ops) {
   assert(Trunc.getOpcode() == TargetOpcode::G_TRUNC && "Must be a G_TRUNC");
 
   const auto FromLLT = MRI.getType(Trunc.getOperand(1).getReg());
-  const auto ToLLT = MRI.getType(Trunc.defs().begin()->getReg());
+  const auto ToLLT = MRI.getType(Trunc.explicit_defs().begin()->getReg());
 
   // TODO: Support non-scalar types.
   if (!FromLLT.isScalar()) {
     return nullptr;
   }
 
   auto ExtOps = DIExpression::getExtOps(FromLLT.getSizeInBits(),
                                         ToLLT.getSizeInBits(), false);

llvm/lib/CodeGen/DetectDeadLanes.cpp

void DeadLaneDetector::transferDefinedLanesStep(const MachineOperand &Use,
   // instruction.
   const MachineInstr &MI = *Use.getParent();
   if (MI.getDesc().getNumDefs() != 1)
     return;
   // FIXME: PATCHPOINT instructions announce a Def that does not always exist,
   // they really need to be modeled differently!
   if (MI.getOpcode() == TargetOpcode::PATCHPOINT)
     return;
-  const MachineOperand &Def = *MI.defs().begin();
+  const MachineOperand &Def = *MI.explicit_defs().begin();
   Register DefReg = Def.getReg();
   if (!DefReg.isVirtual())
     return;
   unsigned DefRegIdx = Register::virtReg2Index(DefReg);
   if (!DefinedByCopy.test(DefRegIdx))
     return;
 
   unsigned OpNum = Use.getOperandNo();
for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
 
     const MachineInstr &UseMI = *MO.getParent();
     if (UseMI.isKill())
       continue;
 
     unsigned SubReg = MO.getSubReg();
     if (lowersToCopies(UseMI)) {
       assert(UseMI.getDesc().getNumDefs() == 1);
-      const MachineOperand &Def = *UseMI.defs().begin();
+      const MachineOperand &Def = *UseMI.explicit_defs().begin();
       Register DefReg = Def.getReg();
       // The used lanes of COPY-like instruction operands are determined by the
       // following dataflow analysis.
       if (DefReg.isVirtual()) {
         // But ignore copies across incompatible register classes.
         bool CrossCopy = false;
         if (lowersToCopies(UseMI)) {
           const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);

llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp

public:
 
   // Iterates over statepoint meta args to find caller saver registers.
   // Also cache the size of found registers.
   // Returns true if caller save registers found.
   bool findRegistersToSpill() {
     SmallSet<Register, 8> GCRegs;
     // All GC pointer operands assigned to registers produce new value.
     // Since they're tied to their defs, it is enough to collect def registers.
-    for (const auto &Def : MI.defs())
+    for (const auto &Def : MI.explicit_defs())
       GCRegs.insert(Def.getReg());
 
     SmallSet<Register, 8> VisitedRegs;
     for (unsigned Idx = StatepointOpers(&MI).getVarIdx(),
                   EndIdx = MI.getNumOperands();
          Idx < EndIdx; ++Idx) {
       MachineOperand &MO = MI.getOperand(Idx);
       // Leave `undef` operands as is, StackMaps will rewrite them

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

MachineIRBuilder::buildPadVectorWithUndefElements(const DstOp &Res,
   assert((ResTy.isVector() && Op0Ty.isVector()) && "Non vector type");
   assert((ResTy.getElementType() == Op0Ty.getElementType()) &&
          "Different vector element types");
   assert((ResTy.getNumElements() > Op0Ty.getNumElements()) &&
          "Op0 has more elements");
 
   auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
   SmallVector<Register, 8> Regs;
-  for (auto Op : Unmerge.getInstr()->defs())
+  for (auto Op : Unmerge.getInstr()->explicit_defs())
     Regs.push_back(Op.getReg());
   Register Undef = buildUndef(Op0Ty.getElementType()).getReg(0);
   unsigned NumberOfPadElts = ResTy.getNumElements() - Regs.size();
   for (unsigned i = 0; i < NumberOfPadElts; ++i)
     Regs.push_back(Undef);
   return buildMergeLikeInstr(Res, Regs);
 }
 

llvm/lib/CodeGen/GlobalISel/Utils.cpp

 }
 
 void llvm::eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI,
                       LostDebugLocObserver *LocObserver) {
   return eraseInstrs({&MI}, MRI, LocObserver);
 }
 
 void llvm::salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI) {
-  for (auto &Def : MI.defs()) {
+  for (auto &Def : MI.explicit_defs()) {
     assert(Def.isReg() && "Must be a reg");
 
     SmallVector<MachineOperand *, 16> DbgUsers;
     for (auto &MOUse : MRI.use_operands(Def.getReg())) {
       MachineInstr *DbgValue = MOUse.getParent();
       // Ignore partially formed DBG_VALUEs.
       if (DbgValue->isNonListDebugValue() && DbgValue->getNumOperands() == 4) {
         DbgUsers.push_back(&MOUse);
       }
     }
 
     if (!DbgUsers.empty()) {
       salvageDebugInfoForDbgValue(MRI, MI, DbgUsers);
     }
   }
 }

llvm/lib/CodeGen/MachineCopyPropagation.cpp

 }
 
 /// For an MI that has multiple definitions, check whether \p MI has
 /// a definition that overlaps with another of its definitions.
 /// For example, on ARM: umull   r9, r9, lr, r0
 /// The umull instruction is unpredictable unless RdHi and RdLo are different.
 bool MachineCopyPropagation::hasOverlappingMultipleDef(
     const MachineInstr &MI, const MachineOperand &MODef, Register Def) {
-  for (const MachineOperand &MIDef : MI.defs()) {
+  for (const MachineOperand &MIDef : MI.explicit_defs()) {
     if ((&MIDef != &MODef) && MIDef.isReg() &&
         TRI->regsOverlap(Def, MIDef.getReg()))
       return true;
   }
 
   return false;
 }
 

llvm/lib/CodeGen/MachineLoopUtils.cpp

MachineBasicBlock *llvm::PeelSingleBlockLoop(LoopPeelDirection Direction,
   else
     MF.insert(std::next(Loop->getIterator()), NewBB);
 
   DenseMap<Register, Register> Remaps;
   auto InsertPt = NewBB->end();
   for (MachineInstr &MI : *Loop) {
     MachineInstr *NewMI = MF.CloneMachineInstr(&MI);
     NewBB->insert(InsertPt, NewMI);
-    for (MachineOperand &MO : NewMI->defs()) {
+    for (MachineOperand &MO : NewMI->explicit_defs()) {
       Register OrigR = MO.getReg();
       if (OrigR.isPhysical())
         continue;
       Register &R = Remaps[OrigR];
       R = MRI.createVirtualRegister(MRI.getRegClass(OrigR));
       MO.setReg(R);
 
       if (Direction == LPD_Back) {

llvm/lib/CodeGen/MachineScheduler.cpp

if (MI->getOperand(UnscheduledOper).getReg().isPhysical())
       return AtBoundary ? -1 : 1;
   }
 
   if (MI->isMoveImmediate()) {
     // If we have a move immediate and all successors have been assigned, bias
     // towards scheduling this later. Make sure all register defs are to
     // physical registers.
     bool DoBias = true;
-    for (const MachineOperand &Op : MI->defs()) {
+    for (const MachineOperand &Op : MI->explicit_defs()) {
       if (Op.isReg() && !Op.getReg().isPhysical()) {
         DoBias = false;
         break;
       }
     }
 
     if (DoBias)
       return isTop ? -1 : 1;

llvm/lib/CodeGen/ModuloSchedule.cpp

void KernelRewriter::rewrite() {
   // loop-carried phis.
   for (auto MI = BB->getFirstNonPHI(); MI != BB->end(); ++MI) {
     if (MI->isPHI()) {
       Register R = MI->getOperand(0).getReg();
       phi(R);
       continue;
     }
 
-    for (MachineOperand &Def : MI->defs()) {
+    for (MachineOperand &Def : MI->explicit_defs()) {
       for (MachineInstr &MI : MRI.use_instructions(Def.getReg())) {
         if (MI.getParent() != BB) {
           phi(Def.getReg());
           break;
         }
       }
     }
   }
void PeelingModuloScheduleExpander::filterInstructions(MachineBasicBlock *MB,
                                                        int MinStage) {
   for (auto I = MB->getFirstInstrTerminator()->getReverseIterator();
        I != std::next(MB->getFirstNonPHI()->getReverseIterator());) {
     MachineInstr *MI = &*I++;
     int Stage = getStage(MI);
     if (Stage == -1 || Stage >= MinStage)
       continue;
 
-    for (MachineOperand &DefMO : MI->defs()) {
+    for (MachineOperand &DefMO : MI->explicit_defs()) {
       SmallVector<std::pair<MachineInstr *, Register>, 4> Subs;
       for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) {
         // Only PHIs can use values from this block by construction.
         // Match with the equivalent PHI in B.
         assert(UseMI.isPHI());
         Register Reg = getEquivalentRegisterIn(UseMI.getOperand(0).getReg(),
                                                MI->getParent());
         Subs.emplace_back(&UseMI, Reg);
void PeelingModuloScheduleExpander::rewriteUsesOf(MachineInstr *MI) {
   }
 
   int Stage = getStage(MI);
   if (Stage == -1 || LiveStages.count(MI->getParent()) == 0 ||
       LiveStages[MI->getParent()].test(Stage))
     // Instruction is live, no rewriting to do.
     return;
 
-  for (MachineOperand &DefMO : MI->defs()) {
+  for (MachineOperand &DefMO : MI->explicit_defs()) {
     SmallVector<std::pair<MachineInstr *, Register>, 4> Subs;
     for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) {
       // Only PHIs can use values from this block by construction.
       // Match with the equivalent PHI in B.
       assert(UseMI.isPHI());
       Register Reg = getEquivalentRegisterIn(UseMI.getOperand(0).getReg(),
                                              MI->getParent());
       Subs.emplace_back(&UseMI, Reg);

llvm/lib/CodeGen/SplitKit.cpp

if (Original) {
     }
   } else {
     // This is a new def: either from rematerialization, or from an inserted
     // copy. Since rematerialization can regenerate a definition of a sub-
     // register, we need to check which subranges need to be updated.
     const MachineInstr *DefMI = LIS.getInstructionFromIndex(Def);
     assert(DefMI != nullptr);
     LaneBitmask LM;
-    for (const MachineOperand &DefOp : DefMI->defs()) {
+    for (const MachineOperand &DefOp : DefMI->explicit_defs()) {
       Register R = DefOp.getReg();
       if (R != LI.reg())
         continue;
       if (unsigned SR = DefOp.getSubReg())
         LM |= TRI.getSubRegIndexLaneMask(SR);
       else {
         LM = MRI.getMaxLaneMaskForVReg(R);
         break;
SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
   VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
                               MBB.SkipPHIsLabelsAndDebug(MBB.begin()));
   RegAssign.insert(Start, VNI->def, OpenIdx);
   LLVM_DEBUG(dump());
   return VNI->def;
 }
 
 static bool hasTiedUseOf(MachineInstr &MI, unsigned Reg) {
-  return any_of(MI.defs(), [Reg](const MachineOperand &MO) {
+  return any_of(MI.explicit_defs(), [Reg](const MachineOperand &MO) {
     return MO.isReg() && MO.isTied() && MO.getReg() == Reg;
   });
 }
 
 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
   assert(OpenIdx && "openIntv not called before overlapIntv");
   const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
   assert(ParentVNI == Edit->getParent().getVNInfoBefore(End) &&

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

bool TwoAddressInstructionPass::convertInstTo3Addr(
   LLVM_DEBUG(dbgs() << "2addr:         TO 3-ADDR: " << *NewMI);
 
   // If the old instruction is debug value tracked, an update is required.
   if (auto OldInstrNum = mi->peekDebugInstrNum()) {
     assert(mi->getNumExplicitDefs() == 1);
     assert(NewMI->getNumExplicitDefs() == 1);
 
     // Find the old and new def location.
-    unsigned OldIdx = mi->defs().begin()->getOperandNo();
-    unsigned NewIdx = NewMI->defs().begin()->getOperandNo();
+    unsigned OldIdx = mi->explicit_defs().begin()->getOperandNo();
+    unsigned NewIdx = NewMI->explicit_defs().begin()->getOperandNo();
 
     // Record that one def has been replaced by the other.
     unsigned NewInstrNum = NewMI->getDebugInstrNum();
     MF->makeDebugValueSubstitution(std::make_pair(OldInstrNum, OldIdx),
                                    std::make_pair(NewInstrNum, NewIdx));
   }
 
   MBB->erase(mi); // Nuke the old inst.

llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

void AArch64A57FPLoadBalancing::scanInstruction(
     MachineInstr *MI, unsigned Idx, std::map<unsigned, Chain *> &ActiveChains,
     std::vector<std::unique_ptr<Chain>> &AllChains) {
   // Inspect "MI", updating ActiveChains and AllChains.
 
   if (isMul(MI)) {
 
     for (auto &I : MI->uses())
       maybeKillChain(I, Idx, ActiveChains);
-    for (auto &I : MI->defs())
+    for (auto &I : MI->explicit_defs())
       maybeKillChain(I, Idx, ActiveChains);
 
     // Create a new chain. Multiplies don't require forwarding so can go on any
     // unit.
     Register DestReg = MI->getOperand(0).getReg();
 
     LLVM_DEBUG(dbgs() << "New chain started for register "
                       << printReg(DestReg, TRI) << " at " << *MI);
if (isMul(MI)) {
     AllChains.push_back(std::move(G));
 
   } else {
 
     // Non-MUL or MLA instruction. Invalidate any chain in the uses or defs
     // lists.
     for (auto &I : MI->uses())
       maybeKillChain(I, Idx, ActiveChains);
-    for (auto &I : MI->defs())
+    for (auto &I : MI->explicit_defs())
       maybeKillChain(I, Idx, ActiveChains);
 
   }
 }
 
 void AArch64A57FPLoadBalancing::
 maybeKillChain(MachineOperand &MO, unsigned Idx,
                std::map<unsigned, Chain*> &ActiveChains) {

llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp

for (; MBBI != E; MBBI = NextMBBI) {
 
     // For general purpose register loads, harden the registers loaded into.
     // For other loads, harden the address loaded from.
     // Masking the loaded value is expected to result in less performance
     // overhead, as the load can still execute speculatively in comparison to
     // when the address loaded from gets masked. However, masking is only
     // easy to do efficiently on GPR registers, so for loads into non-GPR
     // registers (e.g. floating point loads), mask the address loaded from.
-    bool AllDefsAreGPR = llvm::all_of(MI.defs(), [&](MachineOperand &Op) {
-      return Op.isReg() && (AArch64::GPR32allRegClass.contains(Op.getReg()) ||
-                            AArch64::GPR64allRegClass.contains(Op.getReg()));
+    bool AllDefsAreGPR =
+        llvm::all_of(MI.explicit_defs(), [&](MachineOperand &Op) {
+          return Op.isReg() &&
+                 (AArch64::GPR32allRegClass.contains(Op.getReg()) ||
         });
     // FIXME: it might be a worthwhile optimization to not mask loaded
     // values if all the registers involved in address calculation are already
     // hardened, leading to this load not able to execute on a miss-speculated
     // path.
     bool HardenLoadedData = AllDefsAreGPR;
     bool HardenAddressLoadedFrom = !HardenLoadedData;
 
     // First remove registers from AlreadyMaskedRegisters if their value is
     // updated by this instruction - it makes them contain a new value that is
     // not guaranteed to already have been masked.
-    for (MachineOperand Op : MI.defs())
+    for (MachineOperand Op : MI.explicit_defs())
       for (MCRegAliasIterator AI(Op.getReg(), TRI, true); AI.isValid(); ++AI)
         RegsAlreadyMasked.reset(*AI);
 
     // FIXME: loads from the stack with an immediate offset from the stack
     // pointer probably shouldn't be hardened, which could result in a
     // significant optimization. See section "Don’t check loads from
     // compile-time constant stack offsets", in
     // https://llvm.org/docs/SpeculativeLoadHardening.html
 
     if (HardenLoadedData)
-      for (auto Def : MI.defs()) {
+      for (auto Def : MI.explicit_defs()) {
         if (Def.isDead())
           // Do not mask a register that is not used further.
           continue;
         // FIXME: For pre/post-increment addressing modes, the base register
         // used in address calculation is also defined by this instruction.
         // It might be a worthwhile optimization to not harden that
         // base register increment/decrement when the increment/decrement is
         // an immediate.
case AArch64::SpeculationSafeValueX:
     // miss-speculation isn't happening because we're already inserting barriers
     // to guarantee that.
     if (!UseControlFlowSpeculationBarrier && !UsesFullSpeculationBarrier) {
       Register DstReg = MI.getOperand(0).getReg();
       Register SrcReg = MI.getOperand(1).getReg();
       // Mark this register and all its aliasing registers as needing to be
       // value speculation hardened before its next use, by using a CSDB
       // barrier instruction.
-      for (MachineOperand Op : MI.defs())
+      for (MachineOperand Op : MI.explicit_defs())
         for (MCRegAliasIterator AI(Op.getReg(), TRI, true); AI.isValid(); ++AI)
           RegsNeedingCSDBBeforeUse.set(*AI);
 
       // Mask off with taint state.
       BuildMI(MBB, MBBI, MI.getDebugLoc(),
               Is64Bit ? TII->get(AArch64::ANDXrs) : TII->get(AArch64::ANDWrs))
           .addDef(DstReg)
           .addUse(SrcReg, RegState::Kill)

llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp

for (auto &MI : MBB.instrs()) {
           // TODO: For VALU->SALU delays should we use s_delay_alu or s_nop or
           // just ignore them?
           LastDelayAlu = emitDelayAlu(MI, Delay, LastDelayAlu);
         }
       }
 
       if (Type != OTHER) {
         // TODO: Scan implicit defs too?
-        for (const auto &Op : MI.defs()) {
+        for (const auto &Op : MI.explicit_defs()) {
           unsigned Latency = SchedModel.computeOperandLatency(
               &MI, Op.getOperandNo(), nullptr, 0);
           for (MCRegUnitIterator UI(Op.getReg(), TRI); UI.isValid(); ++UI)
             State[*UI] = DelayInfo(Type, Latency);
         }
       }
 
       // Advance by the number of cycles it takes to issue this instruction.

llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

 
 void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB,
                                      const MachineRegisterInfo *MRI,
                                      const TargetRegisterInfo *TRI,
                                      PHILinearize &PHIInfo) {
   LLVM_DEBUG(dbgs() << "-Store Live Outs Begin (" << printMBBReference(*MBB)
                     << ")-\n");
   for (auto &II : *MBB) {
-    for (auto &RI : II.defs()) {
+    for (auto &RI : II.explicit_defs()) {
       storeLiveOutReg(MBB, RI.getReg(), RI.getParent(), MRI, TRI, PHIInfo);
     }
     for (auto &IRI : II.implicit_operands()) {
       if (IRI.isDef()) {
         storeLiveOutReg(MBB, IRI.getReg(), IRI.getParent(), MRI, TRI, PHIInfo);
       }
     }
   }

 }
 
 void LinearizedRegion::storeMBBLiveOuts(MachineBasicBlock *MBB,
                                         const MachineRegisterInfo *MRI,
                                         const TargetRegisterInfo *TRI,
                                         PHILinearize &PHIInfo,
                                         RegionMRT *TopRegion) {
   for (auto &II : *MBB) {
-    for (auto &RI : II.defs()) {
+    for (auto &RI : II.explicit_defs()) {
       storeLiveOutRegRegion(TopRegion, RI.getReg(), RI.getParent(), MRI, TRI,
                             PHIInfo);
     }
     for (auto &IRI : II.implicit_operands()) {
       if (IRI.isDef()) {
         storeLiveOutRegRegion(TopRegion, IRI.getReg(), IRI.getParent(), MRI,
                               TRI, PHIInfo);
       }

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

static void addRegsToSet(const SIRegisterInfo &TRI,
   for (const MachineOperand &Op : Ops) {
     if (Op.isReg())
       addRegUnits(TRI, Set, Op.getReg().asMCReg());
   }
 }
 
 void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) {
   // XXX: Do we need to worry about implicit operands
-  addRegsToSet(TRI, MI.defs(), ClauseDefs);
+  addRegsToSet(TRI, MI.explicit_defs(), ClauseDefs);
   addRegsToSet(TRI, MI.uses(), ClauseUses);
 }
 
 static bool breaksSMEMSoftClause(MachineInstr *MI) {
   return !SIInstrInfo::isSMRD(*MI);
 }
 
 static bool breaksVMEMSoftClause(MachineInstr *MI) {
int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) {
 
   // This checks for the hazard where VMEM instructions that store more than
   // 8 bytes can have there store data over written by the next instruction.
   if (!ST.has12DWordStoreHazard())
     return WaitStatesNeeded;
 
   const MachineRegisterInfo &MRI = MF.getRegInfo();
 
-  for (const MachineOperand &Def : VALU->defs()) {
+  for (const MachineOperand &Def : VALU->explicit_defs()) {
     WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Def, MRI));
   }
 
   return WaitStatesNeeded;
 }
 
 int GCNHazardRecognizer::checkInlineAsmHazards(MachineInstr *IA) {
   // This checks for hazards associated with inline asm statements.
bool GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(MachineInstr *MI) {
 
   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 
   auto IsHazardFn = [TRI, MI](const MachineInstr &I) {
     if (!SIInstrInfo::isVMEM(I) && !SIInstrInfo::isDS(I) &&
         !SIInstrInfo::isFLAT(I))
       return false;
 
-    for (const MachineOperand &Def : MI->defs()) {
+    for (const MachineOperand &Def : MI->explicit_defs()) {
       const MachineOperand *Op =
           I.findRegisterUseOperand(Def.getReg(), false, TRI);
       if (!Op)
         continue;
       return true;
     }
     return false;
   };
if ((Opc == AMDGPU::V_FMA_F64_e64 ||
     int WaitStatesNeededForUse = DMFMAToFMA64WaitStates -
       getWaitStatesSince(IsDGEMMFn, DMFMAToFMA64WaitStates);
     WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
   }
 
   if (!IsVALU && !IsMemOrExport)
     return WaitStatesNeeded;
 
-  for (const MachineOperand &Def : MI->defs()) {
+  for (const MachineOperand &Def : MI->explicit_defs()) {
     const int SMFMA4x4WriteVgprVALUWawWaitStates = 5;
     const int SMFMA16x16WriteVgprVALUWawWaitStates = 11;
     const int SMFMA32x32WriteVgprVALUWawWaitStates = 19;
     const int GFX940_SMFMA2PassWriteVgprVALUWawWaitStates = 4;
     const int GFX940_SMFMA4PassWriteVgprVALUWawWaitStates = 6;
     const int GFX940_SMFMA8PassWriteVgprVALUWawWaitStates = 10;
     const int GFX940_SMFMA16PassWriteVgprVALUWawWaitStates = 18;
     const int GFX940_XDL2PassWriteVgprVALUWawWaitStates = 5;

llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

if (!MI.mayLoad() || MI.mayStore())
     return false;
   if (SIInstrInfo::isAtomic(MI))
     return false;
   if (IsVMEMClause && !isVMEMClauseInst(MI))
     return false;
   if (!IsVMEMClause && !isSMEMClauseInst(MI))
     return false;
   // If this is a load instruction where the result has been coalesced with an operand, then we cannot clause it.
-  for (const MachineOperand &ResMO : MI.defs()) {
+  for (const MachineOperand &ResMO : MI.explicit_defs()) {
     Register ResReg = ResMO.getReg();
     for (const MachineOperand &MO : MI.uses()) {
       if (!MO.isReg() || MO.isDef())
         continue;
       if (MO.getReg() == ResReg)
         return false;
     }
     break; // Only check the first def.

llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

static MachineOperand *findSingleRegDef(const MachineOperand *Reg,
                                         const MachineRegisterInfo *MRI) {
   if (!Reg->isReg())
     return nullptr;
 
   MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg->getReg());
   if (!DefInstr)
     return nullptr;
 
-  for (auto &DefMO : DefInstr->defs()) {
+  for (auto &DefMO : DefInstr->explicit_defs()) {
     if (DefMO.isReg() && DefMO.getReg() == Reg->getReg())
       return &DefMO;
   }
 
   // Ignore implicit defs.
   return nullptr;
 }
 

llvm/lib/Target/AMDGPU/SIPostRABundler.cpp

for (MachineBasicBlock &MBB : MF) {
     for (auto I = B; I != E; I = Next) {
       Next = std::next(I);
       if (!isBundleCandidate(*I))
         continue;
 
       assert(Defs.empty());
 
       if (I->getNumExplicitDefs() != 0)
-        Defs.insert(I->defs().begin()->getReg());
+        Defs.insert(I->explicit_defs().begin()->getReg());
 
       MachineBasicBlock::instr_iterator BundleStart = I;
       MachineBasicBlock::instr_iterator BundleEnd = I;
       unsigned ClauseLength = 1;
       for (I = Next; I != E; I = Next) {
         Next = std::next(I);
 
         assert(BundleEnd != I);
         if (canBundle(*BundleEnd, *I)) {
           BundleEnd = I;
           if (I->getNumExplicitDefs() != 0)
-            Defs.insert(I->defs().begin()->getReg());
+            Defs.insert(I->explicit_defs().begin()->getReg());
           ++ClauseLength;
         } else if (!I->isMetaInstruction()) {
           // Allow meta instructions in between bundle candidates, but do not
           // start or end a bundle on one.
           //
           // TODO: It may be better to move meta instructions like dbg_value
           // after the bundle. We're relying on the memory legalizer to unbundle
           // these.

llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp

for (MachineInstr &MI : *MBB) {
         InWWM = false;
       }
 
       if (!InWWM)
         continue;
 
       LLVM_DEBUG(dbgs() << "Processing " << MI);
 
-      for (MachineOperand &DefOpnd : MI.defs()) {
+      for (MachineOperand &DefOpnd : MI.explicit_defs()) {
         RegsAssigned |= processDef(DefOpnd);
       }
     }
   }
 
   if (!RegsAssigned)
     return false;
 
   rewriteRegs(MF);
   return true;
 }

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

 
 bool SIShrinkInstructions::instReadsReg(const MachineInstr *MI, unsigned Reg,
                                         unsigned SubReg) const {
   return instAccessReg(MI->uses(), Reg, SubReg);
 }
 
 bool SIShrinkInstructions::instModifiesReg(const MachineInstr *MI, unsigned Reg,
                                            unsigned SubReg) const {
-  return instAccessReg(MI->defs(), Reg, SubReg);
+  return instAccessReg(MI->explicit_defs(), Reg, SubReg);
 }
 
 TargetInstrInfo::RegSubRegPair
 SIShrinkInstructions::getSubRegForIndex(Register Reg, unsigned Sub,
                                         unsigned I) const {
   if (TRI->getRegSizeInBits(Reg, *MRI) != 32) {
     if (Reg.isPhysical()) {
       Reg = TRI->getSubReg(Reg, TRI->getSubRegFromChannel(I));

llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp

for (MachineInstr &MI : *MBB) {
                    Opcode == AMDGPU::SI_DEMOTE_I1) {
           KillInstrs.push_back(&MI);
           BBI.NeedsLowering = true;
         } else if (WQMOutputs) {
           // The function is in machine SSA form, which means that physical
           // VGPRs correspond to shader inputs and outputs. Inputs are
           // only used, outputs are only defined.
           // FIXME: is this still valid?
-          for (const MachineOperand &MO : MI.defs()) {
+          for (const MachineOperand &MO : MI.explicit_defs()) {
             if (!MO.isReg())
               continue;
 
             Register Reg = MO.getReg();
 
             if (!Reg.isVirtual() &&
                 TRI->hasVectorRegisters(TRI->getPhysRegBaseClass(Reg))) {
               Flags = StateWQM;

llvm/lib/Target/Mips/MipsInstrInfo.cpp

bool MipsInstrInfo::SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
   switch (MIInSlot.getOpcode()) {
   case Mips::BC1F:
   case Mips::BC1FL:
   case Mips::BC1T:
   case Mips::BC1TL:
     return false;
   }
 
-  for (const MachineOperand &Op : FPUMI.defs()) {
+  for (const MachineOperand &Op : FPUMI.explicit_defs()) {
     if (!Op.isReg())
       continue;
 
     bool Reads, Writes;
     std::tie(Reads, Writes) = MIInSlot.readsWritesVirtualRegister(Op.getReg());
 
     if (Reads || Writes)
       return false;
   }
 
   return true;
 }
 
 /// Predicate for distinguishing instructions that are hazardous in a load delay
 /// slot. Consider inline assembly as unsafe as well.
 bool MipsInstrInfo::SafeInLoadDelaySlot(const MachineInstr &MIInSlot,
                                         const MachineInstr &LoadMI) const {
   if (MIInSlot.isInlineAsm())
     return false;
 
-  return !llvm::any_of(LoadMI.defs(), [&](const MachineOperand &Op) {
+  return !llvm::any_of(LoadMI.explicit_defs(), [&](const MachineOperand &Op) {
     return Op.isReg() && MIInSlot.readsRegister(Op.getReg());
   });
 }
 
 /// Predicate for distingushing instructions that have forbidden slots.
 bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
   return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
 }

llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp

bool NVPTXProxyRegErasure::runOnMachineFunction(MachineFunction &MF) {
   }
 
   return !RemoveList.empty();
 }
 
 void NVPTXProxyRegErasure::replaceMachineInstructionUsage(MachineFunction &MF,
                                                           MachineInstr &MI) {
   auto &InOp = *MI.uses().begin();
-  auto &OutOp = *MI.defs().begin();
+  auto &OutOp = *MI.explicit_defs().begin();
 
   assert(InOp.isReg() && "ProxyReg input operand should be a register.");
   assert(OutOp.isReg() && "ProxyReg output operand should be a register.");
 
   for (auto &BB : MF) {
     for (auto &I : BB) {
       replaceRegisterUsage(I, OutOp, InOp);
     }

llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp

 ///
 bool PPCBranchCoalescing::canMoveToBeginning(const MachineInstr &MI,
                                           const MachineBasicBlock &TargetMBB
                                           ) const {
 
   LLVM_DEBUG(dbgs() << "Checking if " << MI << " can move to beginning of "
                     << TargetMBB.getNumber() << "\n");
 
-  for (auto &Def : MI.defs()) { // Looking at Def
+  for (auto &Def : MI.explicit_defs()) { // Looking at Def
     for (auto &Use : MRI->use_instructions(Def.getReg())) {
       if (Use.isPHI() && Use.getParent() == &TargetMBB) {
         LLVM_DEBUG(dbgs() << "    *** used in a PHI -- cannot move ***\n");
         return false;
       }
     }
   }
 
if (!validateCandidates(SourceRegion, TargetRegion))
     return false;
 
   // Walk through PHI nodes first and see if they force the merge into the
   // SourceRegion.BranchTargetBlock.
   for (MachineBasicBlock::iterator
            I = SourceRegion.BranchBlock->instr_begin(),
            E = SourceRegion.BranchBlock->getFirstNonPHI();
        I != E; ++I) {
-    for (auto &Def : I->defs())
+    for (auto &Def : I->explicit_defs())
       for (auto &Use : MRI->use_instructions(Def.getReg())) {
         if (Use.isPHI() && Use.getParent() == SourceRegion.BranchTargetBlock) {
           LLVM_DEBUG(dbgs()
                      << "PHI " << *I
                      << " defines register used in another "
                         "PHI within branch target block -- can't merge\n");
           NumPHINotMoved++;
           return false;

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

bool RISCVInitUndef::handleImplicitDef(MachineBasicBlock &MBB,
 
   for (auto MO : UseMOs)
     MO->setIsUndef(false);
 
   return true;
 }
 
 static bool isEarlyClobberMI(MachineInstr &MI) {
-  return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) {
+  return llvm::any_of(MI.explicit_defs(), [](const MachineOperand &DefMO) {
     return DefMO.isReg() && DefMO.isEarlyClobber();
   });
 }
 
 bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
                                   const DeadLaneDetector &DLD) {
   bool Changed = false;
 

llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

if (ForwardPointerTypes.find(Ty) != ForwardPointerTypes.end())
     return ForwardPointerTypes[Ty];
   return restOfCreateSPIRVType(Ty, MIRBuilder, AccQual, EmitIR);
 }
 
 Register SPIRVGlobalRegistry::getSPIRVTypeID(const SPIRVType *SpirvType) const {
   assert(SpirvType && "Attempting to get type id for nullptr type.");
   if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer)
     return SpirvType->uses().begin()->getReg();
-  return SpirvType->defs().begin()->getReg();
+  return SpirvType->explicit_defs().begin()->getReg();
 }
 
 SPIRVType *SPIRVGlobalRegistry::createSPIRVType(
     const Type *Ty, MachineIRBuilder &MIRBuilder,
     SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) {
   if (isSpecialOpaqueType(Ty))
     return getOrCreateSpecialType(Ty, MIRBuilder, AccQual);
   auto &TypeToSPIRVTypeMap = DT.getTypes()->getAllUses();

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

if (Dec == static_cast<unsigned>(SPIRV::Decoration::LinkageAttributes)) {
         const Function *ImportedFunc =
             F->getParent()->getFunction(getStringImm(MI, 2));
         Register Target = MI.getOperand(0).getReg();
         MAI.FuncMap[ImportedFunc] = MAI.getRegisterAlias(MI.getMF(), Target);
       }
     }
   } else if (MI.getOpcode() == SPIRV::OpFunction) {
     // Record all internal OpFunction declarations.
-    Register Reg = MI.defs().begin()->getReg();
+    Register Reg = MI.explicit_defs().begin()->getReg();
     Register GlobalReg = MAI.getRegisterAlias(MI.getMF(), Reg);
     assert(GlobalReg.isValid());
     MAI.FuncMap[F] = GlobalReg;
   }
 }
 
 // Collect the given instruction in the specified MS. We assume global register
 // numbering has already occurred by this point. We can directly compare reg

llvm/lib/Target/WebAssembly/WebAssemblyDebugFixup.cpp

for (auto MII = MBB.begin(); MII != MBB.end(); ++MII) {
               BuildMI(*Prev.DebugValue->getParent(), std::next(MII),
                       Prev.DebugValue->getDebugLoc(),
                       TII->get(WebAssembly::DBG_VALUE), false, Register(),
                       Prev.DebugValue->getOperand(2).getMetadata(),
                       Prev.DebugValue->getOperand(3).getMetadata());
             }
           }
         }
-        for (MachineOperand &MO : MI.defs()) {
+        for (MachineOperand &MO : MI.explicit_defs()) {
           if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) {
             Stack.push_back({MO.getReg(), nullptr});
           }
         }
       }
     }
     assert(Stack.empty() &&
            "WebAssemblyDebugFixup: Stack not empty at end of basic block!");
 
     setDanglingDebugValuesUndef(MBB, TII);
   }
 
   return true;
 }

llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

 static MachineInstr *findStartOfTree(MachineOperand &MO,
                                      MachineRegisterInfo &MRI,
                                      const WebAssemblyFunctionInfo &MFI) {
   Register Reg = MO.getReg();
   assert(MFI.isVRegStackified(Reg));
   MachineInstr *Def = MRI.getVRegDef(Reg);
 
   // If this instruction has any non-stackified defs, it is the start
-  for (auto DefReg : Def->defs()) {
+  for (auto DefReg : Def->explicit_defs()) {
     if (!MFI.isVRegStackified(DefReg.getReg())) {
       return Def;
     }
   }
 
   // Find the first stackified use and proceed from there.
   for (MachineOperand &DefMO : Def->explicit_uses()) {
     if (!DefMO.isReg())
for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
         WebAssemblyDebugValueManager(&MI).replaceWithLocal(LocalId);
 
         MI.eraseFromParent();
         Changed = true;
         continue;
       }
 
       // Insert local.sets for any defs that aren't stackified yet.
-      for (auto &Def : MI.defs()) {
+      for (auto &Def : MI.explicit_defs()) {
         Register OldReg = Def.getReg();
         if (!MFI.isVRegStackified(OldReg)) {
           const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
           Register NewReg = MRI.createVirtualRegister(RC);
           auto InsertPt = std::next(MI.getIterator());
           if (UseEmpty[Register::virtReg2Index(OldReg)]) {
             unsigned Opc = getDropOpcode(RC);
             MachineInstr *Drop =

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

if (IsFuncrefCall) {
           BuildMI(MF, DL, TII.get(WebAssembly::CONST_I32), RegZero).addImm(0);
 
       BB->insert(CallResults.getIterator(), MIBC0);
       MachineInstrBuilder(MF, CallParams).addReg(RegZero);
     } else
       CallParams.addOperand(FnPtr);
   }
 
-  for (auto Def : CallResults.defs())
+  for (auto Def : CallResults.explicit_defs())
     MIB.add(Def);
 
   if (IsIndirect) {
     // Placeholder for the type index.
     MIB.addImm(0);
     // The table into which this call_indirect indexes.
     MCSymbolWasm *Table = IsFuncrefCall
                               ? WebAssembly::getOrCreateFuncrefCallTableSymbol(

llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp

case MachineOperand::MO_Immediate: {
       if (DescIndex < Desc.NumOperands) {
         const MCOperandInfo &Info = Desc.operands()[DescIndex];
         if (Info.OperandType == WebAssembly::OPERAND_TYPEINDEX) {
           SmallVector<wasm::ValType, 4> Returns;
           SmallVector<wasm::ValType, 4> Params;
 
           const MachineRegisterInfo &MRI =
               MI->getParent()->getParent()->getRegInfo();
-          for (const MachineOperand &MO : MI->defs())
+          for (const MachineOperand &MO : MI->explicit_defs())
             Returns.push_back(
                 WebAssembly::regClassToValType(MRI.getRegClass(MO.getReg())));
           for (const MachineOperand &MO : MI->explicit_uses())
             if (MO.isReg())
               Params.push_back(
                   WebAssembly::regClassToValType(MRI.getRegClass(MO.getReg())));
 
           // call_indirect instructions have a callee operand at the end which

llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

static bool isSafeToMove(const MachineOperand *Def, const MachineOperand *Use,
   // since ExplicitLocals will not know how to place a def in a local if a
   // subsequent def is stackified. But only one def can be stackified by moving
   // the instruction, so it must be the first one.
   //
   // TODO: This could be loosened to be the first *live* def, but care would
   // have to be taken to ensure the drops of the initial dead defs can be
   // placed. This would require checking that no previous defs are used in the
   // same instruction as subsequent defs.
-  if (Def != DefI->defs().begin())
+  if (Def != DefI->explicit_defs().begin())
     return false;
 
   // If any subsequent def is used prior to the current value by the same
   // instruction in which the current value is used, we cannot
   // stackify. Stackifying in this case would require that def moving below the
   // current def in the stack, which cannot be achieved, even with locals.
   // Also ensure we don't sink the def past any other prior uses.
-  for (const auto &SubsequentDef : drop_begin(DefI->defs())) {
+  for (const auto &SubsequentDef : drop_begin(DefI->explicit_defs())) {
     auto I = std::next(MachineBasicBlock::const_iterator(DefI));
     auto E = std::next(MachineBasicBlock::const_iterator(UseI));
     for (; I != E; ++I) {
       for (const auto &PriorUse : I->uses()) {
         if (&PriorUse == Use)
           break;
         if (PriorUse.isReg() && SubsequentDef.getReg() == PriorUse.getReg())
           return false;
for (auto MII = MBB.rbegin(); MII != MBB.rend(); ++MII) {
             Commuting.maybeCommute(Insert, TreeWalker, TII);
           // Proceed to the next operand.
           continue;
         }
 
         // Stackifying a multivalue def may unlock in-place stackification of
         // subsequent defs. TODO: Handle the case where the consecutive uses are
         // not all in the same instruction.
-        auto *SubsequentDef = Insert->defs().begin();
+        auto *SubsequentDef = Insert->explicit_defs().begin();
         auto *SubsequentUse = &Use;
-        while (SubsequentDef != Insert->defs().end() &&
+        while (SubsequentDef != Insert->explicit_defs().end() &&
                SubsequentUse != Use.getParent()->uses().end()) {
           if (!SubsequentDef->isReg() || !SubsequentUse->isReg())
             break;
           Register DefReg = SubsequentDef->getReg();
           Register UseReg = SubsequentUse->getReg();
           // TODO: This single-use restriction could be relaxed by using tees
           if (DefReg != UseReg || !MRI.hasOneNonDBGUse(DefReg))
             break;
for (MachineInstr &MI : MBB) {
       for (MachineOperand &MO : reverse(MI.explicit_uses())) {
         if (!MO.isReg())
           continue;
         Register Reg = MO.getReg();
         if (MFI.isVRegStackified(Reg))
           assert(Stack.pop_back_val() == Reg &&
                  "Register stack pop should be paired with a push");
       }
-      for (MachineOperand &MO : MI.defs()) {
+      for (MachineOperand &MO : MI.explicit_defs()) {
         if (!MO.isReg())
           continue;
         Register Reg = MO.getReg();
         if (MFI.isVRegStackified(Reg))
           Stack.push_back(MO.getReg());
       }
     }
     // TODO: Generalize this code to support keeping values on the stack across
     // basic block boundaries.
     assert(Stack.empty() &&
            "Register stack pushes and pops should be balanced");
   }
 #endif
 
   return Changed;
 }

llvm/lib/Target/X86/X86CmovConversion.cpp

for (auto &I : *MBB) {
           if (MemOpCC == X86::COND_INVALID)
             // The first memory operand CMOV.
             MemOpCC = CC;
           else if (CC != MemOpCC)
             // Can't handle mixed conditions with memory operands.
             SkipGroup = true;
         }
         // Check if we were relying on zero-extending behavior of the CMOV.
-        if (!SkipGroup &&
-            llvm::any_of(
-                MRI->use_nodbg_instructions(I.defs().begin()->getReg()),
+        if (!SkipGroup && llvm::any_of(MRI->use_nodbg_instructions(
+                                           I.explicit_defs().begin()->getReg()),
                                        [&](MachineInstr &UseI) {
-                  return UseI.getOpcode() == X86::SUBREG_TO_REG;
+                                         return UseI.getOpcode() ==
+                                                X86::SUBREG_TO_REG;
                                        }))
           // FIXME: We should model the cost of using an explicit MOV to handle
           // the zero-extension rather than just refusing to handle this.
           SkipGroup = true;
         continue;
       }
       // If Group is empty, keep looking for first CMOV in the range.
       if (Group.empty())
         continue;
bool X86CmovConverterPass::checkForProfitableCmovCandidates(
   CmovGroups TempGroups;
   std::swap(TempGroups, CmovInstGroups);
   for (auto &Group : TempGroups) {
     bool WorthOpGroup = true;
     for (auto *MI : Group) {
       // Avoid CMOV instruction which value is used as a pointer to load from.
       // This is another conservative check to avoid converting CMOV instruction
       // used with tree-search like algorithm, where the branch is unpredicted.
-      auto UIs = MRI->use_instructions(MI->defs().begin()->getReg());
+      auto UIs = MRI->use_instructions(MI->explicit_defs().begin()->getReg());
       if (!UIs.empty() && ++UIs.begin() == UIs.end()) {
         unsigned Op = UIs.begin()->getOpcode();
         if (Op == X86::MOV64rm || Op == X86::MOV32rm) {
           WorthOpGroup = false;
           break;
         }
       }
 

llvm/lib/Target/X86/X86DomainReassignment.cpp

for (auto &UseMI : MRI->use_nodbg_instructions(CurReg)) {
       // We would like to avoid converting closures which calculare addresses,
       // as this should remain in GPRs.
       if (usedAsAddr(UseMI, CurReg, TII)) {
         C.setAllIllegal();
         continue;
       }
       encloseInstr(C, &UseMI);
 
-      for (auto &DefOp : UseMI.defs()) {
+      for (auto &DefOp : UseMI.explicit_defs()) {
         if (!DefOp.isReg())
           continue;
 
         Register DefReg = DefOp.getReg();
         if (!DefReg.isVirtual()) {
           C.setAllIllegal();
           continue;
         }

llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

if (HardenLoads)
       for (MachineInstr &MI : MBB) {
         // We naively assume that all def'ed registers of an instruction have
         // a data dependency on all of their operands.
         // FIXME: Do a more careful analysis of x86 to build a conservative
         // model here.
         if (llvm::any_of(MI.uses(), [&](MachineOperand &Op) {
               return Op.isReg() && LoadDepRegs.test(Op.getReg());
             }))
-          for (MachineOperand &Def : MI.defs())
+          for (MachineOperand &Def : MI.explicit_defs())
             if (Def.isReg())
               LoadDepRegs.set(Def.getReg());
 
         // Both Intel and AMD are guiding that they will change the semantics of
         // LFENCE to be a speculation barrier, so if we see an LFENCE, there is
         // no more need to guard things in this block.
         if (MI.getOpcode() == X86::LFENCE)
           break;
if (HardenLoads)
         // Record this instruction for address hardening and record its register
         // operands as being address-hardened.
         HardenLoadAddr.insert(&MI);
         if (BaseReg)
           HardenedAddrRegs.insert(BaseReg);
         if (IndexReg)
           HardenedAddrRegs.insert(IndexReg);
 
-        for (MachineOperand &Def : MI.defs())
+        for (MachineOperand &Def : MI.explicit_defs())
           if (Def.isReg())
             LoadDepRegs.set(Def.getReg());
       }
 
     // Now re-walk the instructions in the basic block, and apply whichever
     // hardening strategy we have elected. Note that we do this in a second
     // pass specifically so that we have the complete set of instructions for
     // which we will do post-load hardening and can defer it in certain