RISCV/InstrInfo: model register pressure for MICombiner

[artagnon]

Summary

We have a set of general purpose registers defined for RISC-V (32),
after which we can model the register pressure, inspired by the way it's
modeled in PPC. The motivation for this change is to get MachineCombiner
to not increase register pressure when re-ordering instructions.
Unfortunately, it's very hard to tell if a particular MICombiner
transform will increase register pressure without actually doing the
transform and re-computing register pressure. The workaround that LLVM
has for this is to predicate the transform on
shouldReduceRegisterPressure(), which should ideally tell us when we're
running out of registers. Hence, implement
shouldReduceRegisterPressure() for RISC-V, using the number of general
purpose registers as the limit.

[craig.topper]

Is it possible to add a test?

[artagnon]

Include test, from a benchmark run reduced by hand.

I know the test isn't pretty, but it's the best I could do within reasonable time.

[shiva0217]

In D150671#4353168, @artagnon wrote:

Include test, from a benchmark run reduced by hand.

I know the test isn't pretty, but it's the best I could do within reasonable time.

Could you create a phabricator patch only contain the pre-commit test and let this commit depend on it?
It could be easier to observe the difference in the test case.

[artagnon]

Show difference in added test.

[kito-cheng]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1392

Captured all variable but shadowed MBB from argument of shouldReduceRegisterPressure, this could be a separated static function rather than lambda function I think?

1617–1629

It seems like just a NFC refactor? if so this should split into a separated patch.

[artagnon]

Make getMBBPressure() a static function.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1617–1629

It's not an NFC refactor. Notice if (DoRegPressureReduce) return false;

[artagnon]

Rebase onto hand-crafted test. The differences are much clearer now.

[artagnon]

Ping.

[artagnon]

Address pending review comment by @kito-cheng, and remove NFC parts of the change.

[kito-cheng]

Does here some benchmark result on this change? I guess small benchmarks like dhrystone or coremark might not changed at all, so maybe spec cpu?

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1423

Mention it's GPR class in debug info

1627

I would like to have few more comment to mention we are only tracking reg pressure on GPR here.

[artagnon]

Address @kito-cheng's review comments.

[artagnon]

In D150671#4390724, @kito-cheng wrote:

Does here some benchmark result on this change? I guess small benchmarks like dhrystone or coremark might not changed at all, so maybe spec cpu?

Unfortunately, we currently only have an embedded chip, and can't run SPEC. Dhrystone and Coremark are unchanged. There are, however, minor improvements observed in the Embench suite. Here's a full run-down of the results:

Program                                       upstream   upstream+patch diff
test-suite :: External/Embench/ud.test           1914436    1915914      0.1%
test-suite...xternal/CoreMark/coremark.test      1197810    1197810      0.0%
test-suite...ternal/Embench/aha-mont64.test      2693624    2693624      0.0%
test-suite...External/Embench/wikisort.test       906581     906581      0.0%
test-suite...xternal/Embench/statemate.test       123791     123791      0.0%
test-suite :: External/Embench/st.test           3418254    3418254      0.0%
test-suite... :: External/Embench/slre.test      2000638    2000638      0.0%
test-suite...al/Embench/sglib-combined.test      2476950    2476950      0.0%
test-suite... External/Embench/qrduino.test      2354397    2354397      0.0%
test-suite...ternal/Embench/primecount.test      3926956    3926956      0.0%
test-suite...External/Embench/picojpeg.test      2200313    2200313      0.0%
test-suite...External/Embench/nsichneu.test      2309555    2309555      0.0%
test-suite...ternal/Embench/nettle-aes.test      2238164    2238164      0.0%
test-suite...:: External/Embench/nbody.test      3044262    3044262      0.0%
test-suite...: External/Embench/minver.test       516237     516237      0.0%
test-suite...: External/Embench/md5sum.test      1155977    1155977      0.0%
test-suite...ernal/Embench/matmult-int.test      1270437    1270437      0.0%
test-suite...xternal/Embench/huffbench.test      1794048    1794048      0.0%
test-suite :: External/Embench/edn.test          2016194    2016194      0.0%
test-suite...:: External/Embench/cubic.test      5258870    5258870      0.0%
test-suite...:: External/Embench/crc32.test      2962144    2962144      0.0%
test-suite...marks/Dhrystone/dhrystone.test       226789     226789      0.0%
test-suite... External/Embench/tarfind.test   2141216260 2140872390     -0.0%
test-suite...nal/Embench/nettle-sha256.test      1757618    1754320     -0.2%
Geomean difference                                                      -0.0%

[artagnon]

Ping.

[kito-cheng]

I reviewed and saw this is similar to other target, but I hesitate to give LGTM to this patch since I saw the test case in early version of this patch shows stack usage increases[1], which typically means the register pressure increase, so that means this patch is not always did what we expect to me.

[1] https://reviews.llvm.org/D150671?vs=on&id=523710#toc

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1418

Should this be using RegisterClassInfo::getRegPressureSetLimit which will take into account Reserved registers? I see uses of that in RegPressureTracker

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1412

Does this get called for register classes other than GPR?

If the GPR pressure is already over the limit, does that mean we return true even though the register class in question might be floating point?

[artagnon]

Due to some changes, this patch doesn't seem to be necessary any longer. Will revisit after llvm-17 if necessary.

llvm/lib/Target/RISCV/RISCVInstrInfo.h

public:
   getMachineCombinerPatterns(MachineInstr &Root,
                              SmallVectorImpl<MachineCombinerPattern> &Patterns,
                              bool DoRegPressureReduce) const override;
 
   void
   finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
                     SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
 
+  bool shouldReduceRegisterPressure(
+      const MachineBasicBlock *MBB,
+      const RegisterClassInfo *RegClassInfo) const override;
+
   void genAlternativeCodeSequence(
       MachineInstr &Root, MachineCombinerPattern Pattern,
       SmallVectorImpl<MachineInstr *> &InsInstrs,
       SmallVectorImpl<MachineInstr *> &DelInstrs,
       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
 
   bool hasReassociableSibling(const MachineInstr &Inst,
                               bool &Commuted) const override;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 #include "llvm/Analysis/MemoryLocation.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineCombinerPattern.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineTraceMetrics.h"
+#include "llvm/CodeGen/RegisterPressure.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
+#define DEBUG_TYPE "riscv-instr-info"
+
 #define GEN_CHECK_COMPRESS_INSTR
 #include "RISCVGenCompressInstEmitter.inc"
 
 #define GET_INSTRINFO_CTOR_DTOR
 #define GET_INSTRINFO_NAMED_OPS
 #include "RISCVGenInstrInfo.inc"
 
 static cl::opt<bool> PreferWholeRegisterMove(
assert(static_cast<unsigned>(RISCV::getNamedOperandIdx(
            "Instruction has unexpected number of operands");
     MachineInstrBuilder MIB(MF, NewMI);
     MIB.add(FRM);
     if (FRM.getImm() == RISCVFPRndMode::DYN)
       MIB.addUse(RISCV::FRM, RegState::Implicit);
   }
 }
 
+static std::vector<unsigned>
+getMBBPressure(const MachineBasicBlock *MBB,
+               const RegisterClassInfo *RegClassInfo,
+               const TargetRegisterInfo *TRI, const MachineRegisterInfo *MRI) {
+  RegionPressure Pressure;
+  RegPressureTracker RPTracker(Pressure);
+
+  // Initialize the register pressure tracker.
+  RPTracker.init(MBB->getParent(), RegClassInfo, nullptr, MBB, MBB->end(),
+                 /*TrackLaneMasks*/ false, /*TrackUntiedDefs=*/true);
+
+  for (const auto &MI : reverse(*MBB)) {
+    if (MI.isDebugOrPseudoInstr())
+      continue;
+    RegisterOperands RegOpers;
+    RegOpers.collect(MI, *TRI, *MRI, false, false);
+    RPTracker.recedeSkipDebugValues();
+    assert(&*RPTracker.getPos() == &MI && "RPTracker sync error!");
+    RPTracker.recede(RegOpers);
+  }
+
+  // Close the RPTracker to finalize live ins.
+  RPTracker.closeRegion();
+
+  return RPTracker.getPressure().MaxSetPressure;
+}
+
+bool RISCVInstrInfo::shouldReduceRegisterPressure(
+    const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const {
+  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
+  const MachineFunction *MF = MBB->getParent();
+  const MachineRegisterInfo *MRI = &MF->getRegInfo();
+
+  unsigned GPRLimit = TRI->getRegPressureSetLimit(
+      *MBB->getParent(), RISCV::RegisterPressureSets::GPR);
+  unsigned Pressure = getMBBPressure(MBB, RegClassInfo, TRI,
+                                     MRI)[RISCV::RegisterPressureSets::GPR];
+
+  LLVM_DEBUG(dbgs() << "GPR Register Pressure: " << Pressure << "::" << GPRLimit
+                    << "\n");
+  return Pressure > GPRLimit;
+}
+
 static bool isFADD(unsigned Opc) {
   switch (Opc) {
   default:
     return false;
   case RISCV::FADD_H:
   case RISCV::FADD_S:
   case RISCV::FADD_D:
     return true;

 }
 
 static bool getFPPatterns(MachineInstr &Root,
                           SmallVectorImpl<MachineCombinerPattern> &Patterns,
                           bool DoRegPressureReduce) {
   return getFPFusedMultiplyPatterns(Root, Patterns, DoRegPressureReduce);
 }
 
 bool RISCVInstrInfo::getMachineCombinerPatterns(
     MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
     bool DoRegPressureReduce) const {
 
+  // We only track register pressure on the GPR register class: see
+  // shouldReduceRegisterPressure() to see how DoRegPressureReduce is set.
+
   if (getFPPatterns(Root, Patterns, DoRegPressureReduce))
     return true;
 
+  if (DoRegPressureReduce)
+    return false;
+
   return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
                                                      DoRegPressureReduce);
 }
 
 static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc,
                                          MachineCombinerPattern Pattern) {
   switch (RootOpc) {
   default:

llvm/test/CodeGen/RISCV/machine-combiner.ll

 %"struct.std::__atomic_base" = type { i32 }
 
 ; Since MachineCombiner patterns may lead to an increase in register pressure
 ; resulting in spills, test that MachineCombiner doesn't kick in if there are
 ; more live registers in the MBB than available on the target machine.
 define i32 @test_reg_pressure(ptr %a) {
 ; CHECK-LABEL: test_reg_pressure:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    sd s0, 56(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    sd s1, 48(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    sd s2, 40(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    sd s3, 32(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    sd s4, 24(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    sd s5, 16(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    sd s6, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    .cfi_offset s0, -8
-; CHECK-NEXT:    .cfi_offset s1, -16
-; CHECK-NEXT:    .cfi_offset s2, -24
-; CHECK-NEXT:    .cfi_offset s3, -32
-; CHECK-NEXT:    .cfi_offset s4, -40
-; CHECK-NEXT:    .cfi_offset s5, -48
-; CHECK-NEXT:    .cfi_offset s6, -56
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw a6, 0(a0)
+; CHECK-NEXT:    lw a1, 0(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw a7, 4(a0)
+; CHECK-NEXT:    lw a2, 4(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw t0, 8(a0)
+; CHECK-NEXT:    lw a3, 8(a0)
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw t1, 12(a0)
+; CHECK-NEXT:    lw a2, 12(a0)
+; CHECK-NEXT:    or a1, a1, a3
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw t2, 16(a0)
+; CHECK-NEXT:    lw a3, 16(a0)
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw t6, 20(a0)
+; CHECK-NEXT:    lw a2, 20(a0)
+; CHECK-NEXT:    or a1, a1, a3
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw t3, 24(a0)
+; CHECK-NEXT:    lw a3, 24(a0)
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw t4, 28(a0)
+; CHECK-NEXT:    lw a2, 28(a0)
+; CHECK-NEXT:    or a1, a1, a3
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw s3, 32(a0)
+; CHECK-NEXT:    lw a3, 32(a0)
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw s2, 36(a0)
+; CHECK-NEXT:    lw a2, 36(a0)
+; CHECK-NEXT:    or a1, a1, a3
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw t5, 40(a0)
+; CHECK-NEXT:    lw a3, 40(a0)
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw s4, 44(a0)
+; CHECK-NEXT:    lw a2, 44(a0)
+; CHECK-NEXT:    or a1, a1, a3
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    lw s5, 48(a0)
+; CHECK-NEXT:    lw a3, 48(a0)
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a4, a6, a7
-; CHECK-NEXT:    lw s6, 52(a0)
+; CHECK-NEXT:    lw a2, 52(a0)
+; CHECK-NEXT:    or a1, a1, a3
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or s0, t0, t1
-; CHECK-NEXT:    lw a7, 56(a0)
+; CHECK-NEXT:    lw a3, 56(a0)
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a1, t2, t6
-; CHECK-NEXT:    lw a6, 60(a0)
+; CHECK-NEXT:    lw a2, 60(a0)
+; CHECK-NEXT:    or a1, a1, a3
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a4, a4, s0
-; CHECK-NEXT:    lw s0, 64(a0)
+; CHECK-NEXT:    lw a3, 64(a0)
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a1, a1, t3
-; CHECK-NEXT:    lw a3, 68(a0)
+; CHECK-NEXT:    lw a2, 68(a0)
+; CHECK-NEXT:    or a1, a1, a3
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a2, t4, s3
-; CHECK-NEXT:    lw t2, 72(a0)
+; CHECK-NEXT:    lw a3, 72(a0)
 ; CHECK-NEXT:    fence r, rw
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a1, a1, a4
-; CHECK-NEXT:    lw a4, 76(a0)
+; CHECK-NEXT:    lw a2, 76(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a2, a2, s2
-; CHECK-NEXT:    lw a4, 80(a0)
+; CHECK-NEXT:    or a1, a1, a3
+; CHECK-NEXT:    lw a2, 80(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a5, s4, s5
-; CHECK-NEXT:    lw t0, 84(a0)
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 84(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a2, a2, t5
-; CHECK-NEXT:    lw t1, 88(a0)
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 88(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a5, a5, s6
-; CHECK-NEXT:    lw s1, 92(a0)
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 92(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
 ; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    lw a2, 96(a0)
-; CHECK-NEXT:    or a5, a5, a7
-; CHECK-NEXT:    or a3, a3, s0
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a2, a2, s1
-; CHECK-NEXT:    lw s1, 100(a0)
-; CHECK-NEXT:    or a5, a5, a6
-; CHECK-NEXT:    or a3, a3, t2
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 100(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a2, a2, s1
-; CHECK-NEXT:    lw s1, 104(a0)
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 104(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a3, a3, a4
-; CHECK-NEXT:    lw a4, 108(a0)
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 108(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a2, a2, s1
-; CHECK-NEXT:    lw s1, 112(a0)
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 112(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a3, a3, t0
-; CHECK-NEXT:    lw s0, 116(a0)
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 116(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a2, a2, a4
-; CHECK-NEXT:    lw a4, 120(a0)
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 120(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a1, a1, a5
-; CHECK-NEXT:    lw a5, 124(a0)
-; CHECK-NEXT:    or a3, a3, t1
-; CHECK-NEXT:    or a2, a2, s1
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 124(a0)
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
-; CHECK-NEXT:    or a4, a4, a5
-; CHECK-NEXT:    lw a5, 124(a0)
-; CHECK-NEXT:    or a1, a1, a3
-; CHECK-NEXT:    or a2, a2, s0
-; CHECK-NEXT:    or a4, a4, a5
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    lw a2, 124(a0)
+; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    fence r, rw
 ; CHECK-NEXT:    fence rw, rw
 ; CHECK-NEXT:    lw a0, 124(a0)
-; CHECK-NEXT:    or a1, a1, a2
-; CHECK-NEXT:    or a0, a0, a4
 ; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    fence r, rw
-; CHECK-NEXT:    ld s0, 56(sp) # 8-byte Folded Reload
-; CHECK-NEXT:    ld s1, 48(sp) # 8-byte Folded Reload
-; CHECK-NEXT:    ld s2, 40(sp) # 8-byte Folded Reload
-; CHECK-NEXT:    ld s3, 32(sp) # 8-byte Folded Reload
-; CHECK-NEXT:    ld s4, 24(sp) # 8-byte Folded Reload
-; CHECK-NEXT:    ld s5, 16(sp) # 8-byte Folded Reload
-; CHECK-NEXT:    ld s6, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT:    addi sp, sp, 64
 ; CHECK-NEXT:    ret
 entry:
   %0 = load atomic i32, ptr %a seq_cst, align 4
   %arrayidx1 = getelementptr inbounds %"struct.std::atomic", ptr %a, i64 1
   %1 = load atomic i32, ptr %arrayidx1 seq_cst, align 4
   %arrayidx3 = getelementptr inbounds %"struct.std::atomic", ptr %a, i64 2
   %2 = load atomic i32, ptr %arrayidx3 seq_cst, align 4
   %arrayidx5 = getelementptr inbounds %"struct.std::atomic", ptr %a, i64 3