[RISCV] Support constant operand for la and lla pseudoinstruction.

[garvitgupta08]

Summary

This patch improves compatibility with GNU assembler by adding support for
constant immediate in la and lla pseudo instruction, and expanding it in the
same way as we currently expands li pseudo instruction.

Links to discussion related to the above issue in the community -
https://github.com/riscv-non-isa/riscv-arch-test/issues/105
https://github.com/riscv-non-isa/riscv-arch-test/issues/108
https://github.com/riscv-non-isa/riscv-arch-test/issues/106

[garvitgupta08]

Fixing premerge checks

[garvitgupta08]

Fixing Premerge checks

[jrtc27]

Using AUIPC to generate an absolute address (which is how GNU people seem to justify this ugly ability) sounds wrong

[garvitgupta08]

In D150133#4334850, @jrtc27 wrote:

Using AUIPC to generate an absolute address (which is how GNU people seem to justify this ugly ability) sounds wrong

To be on the same page - GCC expands this instruction as what it does with li i.e. GCC expands it into lui + addi pair. But since spec mentions auipc + addi, therefore I have used that.

[jrtc27]

In D150133#4334953, @garvitgupta08 wrote:

In D150133#4334850, @jrtc27 wrote:

Using AUIPC to generate an absolute address (which is how GNU people seem to justify this ugly ability) sounds wrong

To be on the same page - GCC expands this instruction as what it does with li i.e. GCC expands it into lui + addi pair. But since spec mentions auipc + addi, therefore I have used that.

GCC doesn't do anything with assembly, it's binutils's assembler that expands pseudos. And the spec says auipc+addi or auipc+l[wd], because it's in the context of getting a symbol's address, it doesn't document being able to pass an immediate argument at all, which does not make sense to generate with auipc + addi. So don't; it's completely broken. At which point, just reuse the expansion for li.

You'll also need to see which of la, lla and lga support an immediate in order to determine where this needs to be handled.

And please upload your diffs with full context per https://llvm.org/docs/DeveloperPolicy.html#making-and-submitting-a-patch.

[asb]

Honestly I'd be leaning towards compatibility with gas in this case. la with integer arguments may not seem elegant, but it's consistent with flexibility afforded elsewhere (e.g. add with integer arguments).

But yes, if you want to propose this please do use the same expansion that binutils/gas does (essentially having la of an immediate as an alias of li as I understand it).

[garvitgupta08]

Change la with constant immediate expand to lui + addi - same as what GNU assembler do. (Essentially making la an alias of li)

[garvitgupta08]

Hi @jrtc27 @asb, I have pushed new changes in accordance with your previous comments. Can you please check and provide an update on the same? Thanks

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1613

Size = 32 probably warrants a comment pointing back at PseudoLI's explanation

mayLoad should be 0?

1615

Why can't we just reuse ixlenimm_li?

1616

Indentation

1618

Why? We expand li during parsing, so we should never be trying to print it.

[garvitgupta08]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1615

Because the DiagnosticType in class ImmXLenAsmOperand is !strconcat("Invalid", Name), and since the error message for li and la is different (because la supports both symbol and constant immediate) therefore I had to create a new ixlenimm_la type to support that.

[garvitgupta08]

Hi @jrtc27, I have pushed new changes per your comments. Please have a look.

[garvitgupta08]

An update on the new changes will be appreciated!. Thanks

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1619

I don't understand why you need a new pseudo rather than teaching the existing one to also accept an integer

1622

You marked my "Why? We expand li during parsing, so we should never be trying to print it." comment as done yet this is still here. I do not see why we would ever want it.

[garvitgupta08]

Addressed the comments

[garvitgupta08]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1619

I did this in the revision https://reviews.llvm.org/D150133?id=521304. Below is the diff for the same but I believe that having a separate defintion for supporting constant operand in la will be much cleaner and readable than modifying the existing defintion to accept bare symbol and constant as argument.

+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

+ OperandMatchResultTy parseBareSymbolOrConstant(OperandVector &Operands);

+ // Allow Constant Immediate as well as BareSymbols
+ bool isBareSymbolOrConstant() const {
+ if (isBareSymbol())
+ return true;
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ if (!isImm())
+ return false;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ bool IsInRange = isInt<32>(Imm) || isUInt<32>(Imm) || isRV64Imm();
+ return IsConstantImm && IsInRange && VK == RISCVMCExpr::VK_RISCV_None;
+ }
+

+ case Match_InvalidBareSymbolOrConstant: {
+ return generateImmOutOfRangeError(
+ Operands, ErrorInfo, std::numeric_limits<int32_t>::min(),
+ std::numeric_limits<uint32_t>::max(),
+ "operand either must be a Bare Symbol or an integer in the range");
+ }

+OperandMatchResultTy RISCVAsmParser::parseBareSymbolOrConstant(OperandVector &Operands) {
+ if (getLexer().getKind() == AsmToken::Identifier) {
+ OperandMatchResultTy Result = parseImmediate(Operands);
+ if (Result == MatchOperand_Success)
+ return MatchOperand_Success;
+ }
+ return parseBareSymbol(Operands);
+}
+

+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td

+def BareSymbolOrConstant : AsmOperandClass {
+ let Name = "BareSymbolOrConstant";
+ let RenderMethod = "addImmOperands";
+ let DiagnosticType = "InvalidBareSymbolOrConstant";
+ let ParserMethod = "parseBareSymbolOrConstant";
+}
+

+// support constant operand for la pseudoinstruction.
+def bare_symbol_or_constant : Operand<XLenVT> {
+ let ParserMatchClass = BareSymbolOrConstant;
+}
+

-def PseudoLA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+def PseudoLA : Pseudo<(outs GPR:$dst), (ins bare_symbol_or_constant:$src), [],

[garvitgupta08]

Hi, I would like to merge this patch. Please let me know if new changes are fine. Thanks!

[garvitgupta08]

Hi @jrtc27, an update on the new changes will be appreciated!. Thanks

[garvitgupta08]

Hi @craig.topper , can you please review the patch and suggest if it needs any modifications/additions. Thanks!

[craig.topper]

Are we going to fix the same compatibility issue with "lla" and "lga"?

[garvitgupta08]

In D150133#4449904, @craig.topper wrote:

Are we going to fix the same compatibility issue with "lla" and "lga"?

I do not plan to work on it at the moment.

[craig.topper]

In D150133#4451173, @garvitgupta08 wrote:

In D150133#4449904, @craig.topper wrote:

Are we going to fix the same compatibility issue with "lla" and "lga"?

I do not plan to work on it at the moment.

Would supporting that justify the approach using bare_symbol_or_constant?

[garvitgupta08]

In D150133#4451187, @craig.topper wrote:

In D150133#4451173, @garvitgupta08 wrote:

In D150133#4449904, @craig.topper wrote:

Are we going to fix the same compatibility issue with "lla" and "lga"?

I do not plan to work on it at the moment.

Would supporting that justify the approach using bare_symbol_or_constant?

I have added support for lla as well. I believe that having a separate definition for immediate operand is much clean and readable than modifying the existing implementation (as shown in the diff above).

[craig.topper]

LGTM

[garvitgupta08]

In D150133#4465966, @craig.topper wrote:

LGTM

Can you please commit this patch on my behalf? I do not have commit access. Thanks!

Username - garvitgupta08
Name - Garvit Gupta
Mail - [e-mail]

[garvitgupta08]

Fixing Premerge checks

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

                          const MCExpr *Symbol, RISCVMCExpr::VariantKind VKHi,
                          unsigned SecondOpcode, SMLoc IDLoc, MCStreamer &Out);
 
+  // Helper to emit a combination of AUIPC and ADDI(W) instructions for
+  // constant immediate for la pseudoinstuction. Used in emitLoadAddress routine.
+  void emitAuipcInstPair(MCOperand Register, int64_t value, MCStreamer &Out);
+
   // Helper to emit pseudo instruction "lla" used in PC-rel addressing.
   void emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
 

   OperandMatchResultTy parseZeroOffsetMemOp(OperandVector &Operands);
   OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
   OperandMatchResultTy parseBareSymbol(OperandVector &Operands);
+  OperandMatchResultTy parseBareSymbolOrConstant(OperandVector &Operands);
   OperandMatchResultTy parseCallSymbol(OperandVector &Operands);
   OperandMatchResultTy parsePseudoJumpSymbol(OperandVector &Operands);
   OperandMatchResultTy parseJALOffset(OperandVector &Operands);

            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  // Allow Constant Immediate as well as BareSymbols
+  bool isBareSymbolOrConstant() const {
+    if (isBareSymbol())
+      return true;
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    bool IsInRange = isInt<32>(Imm) || isUInt<32>(Imm) || isRV64();
+    return IsConstantImm && IsInRange && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isCallSymbol() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;

     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a bare symbol name");
   }
+  case Match_InvalidBareSymbolOrConstant: {
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, std::numeric_limits<int32_t>::min(),
+        std::numeric_limits<uint32_t>::max(),
+        "operand either must be a Bare Symbol or an integer in the range");
+  }
   case Match_InvalidPseudoJumpSymbol: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a valid jump target");

   return MatchOperand_Success;
 }
 
+OperandMatchResultTy RISCVAsmParser::parseBareSymbolOrConstant(OperandVector &Operands) {
+  if (getLexer().getKind() == AsmToken::Identifier) {
+    OperandMatchResultTy Result = parseImmediate(Operands);
+    if (Result == MatchOperand_Success)
+      return MatchOperand_Success;
+  }
+  return parseBareSymbol(Operands);
+}
+
 OperandMatchResultTy RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
   SMLoc S = getLoc();
   const MCExpr *Res;

                           .addExpr(RefToLinkTmpLabel));
 }
 
+void RISCVAsmParser::emitAuipcInstPair(MCOperand Register,
+                                        int64_t Value, MCStreamer &Out) {
+  // la with constant operand expands to -
+  // la rd, constant: auipc rd, constant[31:12]
+  //                  addi rd, rd, constant[11:0]
+  MCRegister DestReg = Register.getReg();
+  if (!isRV64())
+    Value = SignExtend64<32>(Value);
+  if (isInt<32>(Value)) {
+    // Emits the MC instructions for loading a 32-bit address into a register.
+    //
+    // Depending on the active bits in the immediate Value v, the following
+    // instruction sequences are emitted:
+    //
+    // v == 0                        : ADDI(W)
+    // v[0,12) != 0 && v[12,32) == 0 : ADDI(W)
+    // v[0,12) == 0 && v[12,32) != 0 : AUIPC
+    // v[0,32) != 0                  : AUIPC+ADDI(W)
+    //
+    int64_t Hi20 = ((Value + 0x800) >> 12) & 0xFFFFF;
+    int64_t Lo12 = SignExtend64<12>(Value);
+    MCRegister SrcReg = RISCV::X0;
+
+    if (Hi20) {
+      emitToStreamer(Out,
+                     MCInstBuilder(RISCV::AUIPC).addReg(DestReg).addImm(Hi20));
+      SrcReg = DestReg;
+    }
+
+    if (Lo12 || Hi20 == 0) {
+      unsigned AddiOpcode = isRV64() ? RISCV::ADDIW : RISCV::ADDI;
+      emitToStreamer(Out, MCInstBuilder(AddiOpcode)
+                              .addReg(DestReg)
+                              .addReg(SrcReg)
+                              .addImm(Lo12));
+    }
+    return;
+  }
+  assert(isRV64() && "Can't emit >32-bit imm for non-RV64 target");
+  int64_t Lo12 = SignExtend64<12>(Value);
+  int64_t Hi52 = (Value + 0x800) >> 12;
+  int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
+  Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
+
+  emitAuipcInstPair(Register, Hi52, Out);
+
+  emitToStreamer(Out, MCInstBuilder(RISCV::SLLI)
+                          .addReg(DestReg)
+                          .addReg(DestReg)
+                          .addImm(ShiftAmount));
+
+  if (Lo12)
+    emitToStreamer(Out, MCInstBuilder(RISCV::ADDI)
+                            .addReg(DestReg)
+                            .addReg(DestReg)
+                            .addImm(Lo12));
+}
+
 void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
                                           MCStreamer &Out) {
   // The load local address pseudo-instruction "lla" is used in PC-relative

   // or (for PIC)
   //   TmpLabel: AUIPC rdest, %got_pcrel_hi(symbol)
   //             Lx rdest, %pcrel_lo(TmpLabel)(rdest)
+  // or (for constant)
+  // la rd, constant: auipc rd, constant[31:12]
+  //                  addi rd, rd, constant[11:0]
   MCOperand DestReg = Inst.getOperand(0);
-  const MCExpr *Symbol = Inst.getOperand(1).getExpr();
+  const MCOperand Op1 = Inst.getOperand(1);
   unsigned SecondOpcode;
   RISCVMCExpr::VariantKind VKHi;
   if (ParserOptions.IsPicEnabled) {

     SecondOpcode = RISCV::ADDI;
     VKHi = RISCVMCExpr::VK_RISCV_PCREL_HI;
   }
-  emitAuipcInstPair(DestReg, DestReg, Symbol, VKHi, SecondOpcode, IDLoc, Out);
+  if (Op1.isExpr()) {
+    const MCExpr *Symbol = Op1.getExpr();
+    emitAuipcInstPair(DestReg, DestReg, Symbol, VKHi, SecondOpcode, IDLoc, Out);
+  } else {
+    // If absolute address of symbol is in the instruction itself.
+    int64_t Imm = Op1.getImm();
+    emitAuipcInstPair(DestReg, Imm, Out);
+  }
 }
 
 void RISCVAsmParser::emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,

llvm/lib/Target/RISCV/RISCVInstrInfo.td

   let ParserMethod = "parseBareSymbol";
 }
 
+def BareSymbolOrConstant : AsmOperandClass {
+  let Name = "BareSymbolOrConstant";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = "InvalidBareSymbolOrConstant";
+  let ParserMethod = "parseBareSymbolOrConstant";
+}
+
 // A bare symbol.
 def bare_symbol : Operand<XLenVT> {
   let ParserMatchClass = BareSymbol;
 }
 
+// support constant operand for la pseudoinstruction.
+def bare_symbol_or_constant : Operand<XLenVT> {
+  let ParserMatchClass = BareSymbolOrConstant;
+}
+
 def CallSymbol : AsmOperandClass {
   let Name = "CallSymbol";
   let RenderMethod = "addImmOperands";

 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 0,
     isAsmParserOnly = 1 in
-def PseudoLA_TLS_IE : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+def PseudoLA_TLS_IE : Pseudo<(outs GPR:$dst), (ins bare_symbol_or_constant:$src), [],
                              "la.tls.ie", "$dst, $src">;
 
 def : Pat<(riscv_la_tls_ie tglobaltlsaddr:$in),

llvm/test/MC/RISCV/rv32i-aliases-invalid.s

 li x0, -2147483649  # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
 li t4, foo          # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
 
+la x0, 4294967296   # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
+la x0, -2147483649  # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
+
 negw x1, x2   # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
 sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
 zext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}

llvm/test/MC/RISCV/rv32i-aliases-valid.s

 # CHECK-EXPAND: addi a0, a0, 801
 li a0, CONST
 
+# CHECK-INST: addi a0, zero, 0
+# CHECK-ALIAS: li a0, 0
+la x10, 0
+# CHECK-INST: addi a0, zero, 1
+# CHECK-ALIAS: li a0, 1
+la x10, 1
+# CHECK-INST: addi a0, zero, -1
+# CHECK-ALIAS: li a0, -1
+la x10, -1
+# CHECK-INST: addi a0, zero, 2047
+# CHECK-ALIAS: li a0, 2047
+la x10, 2047
+# CHECK-INST: addi a0, zero, -2047
+# CHECK-ALIAS: li a0, -2047
+la x10, -2047
+# CHECK-INST: auipc a1, 1
+# CHECK-INST: addi a1, a1, -2048
+# CHECK-ALIAS: auipc a1, 1
+# CHECK-ALIAS: addi a1, a1, -2048
+la x11, 2048
+# CHECK-INST: addi a1, zero, -2048
+# CHECK-ALIAS: li a1, -2048
+la x11, -2048
+# CHECK-EXPAND: auipc a1, 1
+# CHECK-EXPAND: addi a1, a1, -2047
+la x11, 2049
+# CHECK-EXPAND: auipc a1, 1048575
+# CHECK-EXPAND: addi a1, a1, 2047
+la x11, -2049
+# CHECK-EXPAND: auipc a1, 1
+# CHECK-EXPAND: addi a1, a1, -1
+la x11, 4095
+# CHECK-EXPAND: auipc a1, 1048575
+# CHECK-EXPAND: addi a1, a1, 1
+la x11, -4095
+# CHECK-EXPAND: auipc a2, 1
+la x12, 4096
+# CHECK-EXPAND: auipc a2, 1048575
+la x12, -4096
+# CHECK-EXPAND: auipc a2, 1
+# CHECK-EXPAND: addi a2, a2, 1
+la x12, 4097
+# CHECK-EXPAND: auipc a2, 1048575
+# CHECK-EXPAND: addi a2, a2, -1
+la x12, -4097
+# CHECK-EXPAND: auipc a2, 524288
+# CHECK-EXPAND: addi a2, a2, -1
+la x12, 2147483647
+# CHECK-EXPAND: auipc a2, 524288
+# CHECK-EXPAND: addi a2, a2, 1
+la x12, -2147483647
+# CHECK-EXPAND: auipc a2, 524288
+la x12, -2147483648
+# CHECK-EXPAND: auipc a2, 524288
+la x12, -0x80000000
+
+# CHECK-EXPAND: auipc a2, 524288
+la x12, 0x80000000
+# CHECK-INST: addi a2, zero, -1
+# CHECK-ALIAS: li a2, -1
+la x12, 0xFFFFFFFF
+
+.equ CONST, 0x123456
+# CHECK-EXPAND: auipc a0, 291
+# CHECK-EXPAND: addi a0, a0, 1110
+la a0, CONST
+# CHECK-EXPAND: auipc a0, 291
+# CHECK-EXPAND: addi a0, a0, 1111
+la a0, CONST+1
+
+.equ CONST, 0x654321
+# CHECK-EXPAND: auipc a0, 1620
+# CHECK-EXPAND: addi a0, a0, 801
+la a0, CONST
+
 # CHECK-INST: csrrs t4, instreth, zero
 # CHECK-ALIAS: rdinstreth t4
 rdinstreth x29

llvm/test/MC/RISCV/rv64i-aliases-invalid.s

 li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand
 li t4, foo                 # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer
 
+la t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand
+
 rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}}
 rdcycleh x27   # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}}
 rdtimeh x28    # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}}

llvm/test/MC/RISCV/rv64i-aliases-valid.s

 # CHECK-EXPAND: addiw a0, a0, 801
 li a0, CONST
 
+# CHECK-INST: addiw a0, zero, 0
+# CHECK-ALIAS: sext.w  a0, zero
+la x10, 0
+# CHECK-INST: addiw a0, zero, 1
+# CHECK-ALIAS: addiw a0, zero, 1
+la x10, 1
+# CHECK-INST: addiw a0, zero, -1
+# CHECK-ALIAS: addiw a0, zero, -1
+la x10, -1
+# CHECK-INST: addiw a0, zero, 2047
+# CHECK-ALIAS: addiw a0, zero, 2047
+la x10, 2047
+# CHECK-INST: addiw a0, zero, -2047
+# CHECK-ALIAS: addiw a0, zero, -2047
+la x10, -2047
+# CHECK-INST: auipc   a1, 1
+# CHECK-INST: addiw   a1, a1, -2048
+la x11, 2048
+# CHECK-INST: addiw a1, zero, -2048
+la x11, -2048
+# CHECK-EXPAND: auipc a1, 1
+# CHECK-EXPAND: addiw a1, a1, -2047
+la x11, 2049
+# CHECK-EXPAND: auipc a1, 1048575
+# CHECK-EXPAND: addiw a1, a1, 2047
+la x11, -2049
+# CHECK-EXPAND: auipc a1, 1
+# CHECK-EXPAND: addiw a1, a1, -1
+la x11, 4095
+# CHECK-EXPAND: auipc a1, 1048575
+# CHECK-EXPAND: addiw a1, a1, 1
+la x11, -4095
+# CHECK-EXPAND: auipc a2, 1
+la x12, 4096
+# CHECK-EXPAND: auipc a2, 1048575
+la x12, -4096
+# CHECK-EXPAND: auipc a2, 1
+# CHECK-EXPAND: addiw a2, a2, 1
+la x12, 4097
+# CHECK-EXPAND: auipc a2, 1048575
+# CHECK-EXPAND: addiw a2, a2, -1
+la x12, -4097
+# CHECK-EXPAND: auipc a2, 524288
+# CHECK-EXPAND: addiw a2, a2, -1
+la x12, 2147483647
+# CHECK-EXPAND: auipc a2, 524288
+# CHECK-EXPAND: addiw a2, a2, 1
+la x12, -2147483647
+# CHECK-EXPAND: auipc a2, 524288
+la x12, -2147483648
+# CHECK-EXPAND: auipc a2, 524288
+la x12, -0x80000000
+
+# CHECK-INST: addiw a2, zero, 1
+# CHECK-INST: slli a2, a2, 31
+# CHECK-ALIAS: addiw a2, zero, 1
+# CHECK-ALIAS-NEXT: slli a2, a2, 31
+la x12, 0x80000000
+# CHECK-INST: addiw   a2, zero, 1
+# CHECK-INST-NEXT: slli a2, a2, 32
+# CHECK-INST-NEXT: addi a2, a2, -1
+la x12, 0xFFFFFFFF
+
+# CHECK-INST: addiw t0, zero, 1
+# CHECK-INST-NEXT: slli t0, t0, 32
+# CHECK-ALIAS: addiw t0, zero, 1
+# CHECK-ALIAS-NEXT: slli t0, t0, 32
+la t0, 0x100000000
+# CHECK-INST: addiw t1, zero, -1
+# CHECK-INST-NEXT: slli t1, t1, 63
+# CHECK-ALIAS: addiw t1, zero, -1
+# CHECK-ALIAS-NEXT: slli t1, t1, 63
+la t1, 0x8000000000000000
+# CHECK-INST: addiw t1, zero, -1
+# CHECK-INST-NEXT: slli t1, t1, 63
+# CHECK-ALIAS: addiw t1, zero, -1
+# CHECK-ALIAS-NEXT: slli t1, t1, 63
+la t1, -0x8000000000000000
+# CHECK-EXPAND: auipc t2, 9321
+# CHECK-EXPAND-NEXT: addiw t2, t2, -1329
+# CHECK-EXPAND-NEXT: slli t2, t2, 35
+la t2, 0x1234567800000000
+# CHECK-INST: addiw t3, zero, 7
+# CHECK-INST-NEXT: slli t3, t3, 36
+# CHECK-INST-NEXT: addi t3, t3, 11
+# CHECK-INST-NEXT: slli t3, t3, 24
+# CHECK-INST-NEXT: addi t3, t3, 15
+# CHECK-ALIAS: addiw t3, zero, 7
+# CHECK-ALIAS-NEXT: slli t3, t3, 36
+# CHECK-ALIAS-NEXT: addi t3, t3, 11
+# CHECK-ALIAS-NEXT: slli t3, t3, 24
+# CHECK-ALIAS-NEXT: addi t3, t3, 15
+la t3, 0x700000000B00000F
+# CHECK-EXPAND: auipc t4, 583
+# CHECK-EXPAND-NEXT: addiw t4, t4, -1875
+# CHECK-EXPAND-NEXT: slli t4, t4, 14
+# CHECK-EXPAND-NEXT: addi t4, t4, -947
+# CHECK-EXPAND-NEXT: slli t4, t4, 12
+# CHECK-EXPAND-NEXT: addi t4, t4, 1511
+# CHECK-EXPAND-NEXT: slli t4, t4, 13
+# CHECK-EXPAND-NEXT: addi t4, t4, -272
+la t4, 0x123456789abcdef0
+# CHECK-INST: addiw t5, zero, -1
+la t5, 0xFFFFFFFFFFFFFFFF
+# CHECK-EXPAND: auipc t6, 64
+# CHECK-EXPAND-NEXT: addiw t6, t6, 1
+# CHECK-EXPAND-NEXT: slli t6, t6, 13
+la t6, 0x80002000
+# CHECK-EXPAND: auipc t0, 64
+# CHECK-EXPAND-NEXT: addiw t0, t0, 1
+# CHECK-EXPAND-NEXT: slli t0, t0, 14
+la x5, 0x100004000
+# CHECK-EXPAND: auipc t1, 1
+# CHECK-EXPAND-NEXT: addiw t1, t1, 1
+# CHECK-EXPAND-NEXT: slli t1, t1, 32
+la x6, 0x100100000000
+# CHECK-EXPAND: addiw   t2, zero, 1
+# CHECK-EXPAND-NEXT: slli    t2, t2, 36
+# CHECK-EXPAND-NEXT: addi    t2, t2, -1
+# CHECK-EXPAND-NEXT: slli    t2, t2, 12
+# CHECK-EXPAND-NEXT: addi    t2, t2, 1
+la x7, 0xFFFFFFFFF001
+# CHECK-EXPAND: auipc s0, 65536
+# CHECK-EXPAND-NEXT: addiw   s0, s0, -1
+# CHECK-EXPAND-NEXT: slli    s0, s0, 12
+# CHECK-EXPAND-NEXT: addi    s0, s0, 1
+la x8, 0xFFFFFFF001
+# CHECK-EXPAND: auipc s1, 1
+# CHECK-EXPAND-NEXT: addiw s1, s1, 1
+# CHECK-EXPAND-NEXT: slli s1, s1, 32
+# CHECK-EXPAND-NEXT: addi s1, s1, -3
+la x9, 0x1000FFFFFFFD
+# CHECK-INST: addiw a0, zero, -1
+# CHECK-INST-NEXT: slli a0, a0, 36
+# CHECK-INST-NEXT: addi a0, a0, 1
+# CHECK-INST-NEXT: slli a0, a0, 25
+# CHECK-INST-NEXT: addi a0, a0, -1
+la x10, 0xE000000001FFFFFF
+# CHECK-INST: addiw a1, zero, -2047
+# CHECK-INST-NEXT: slli a1, a1, 27
+# CHECK-INST-NEXT: addi a1, a1, -1
+# CHECK-INST-NEXT: slli a1, a1, 12
+# CHECK-INST-NEXT: addi a1, a1, 2047
+la x11, 0xFFFC007FFFFFF7FF
+
+# CHECK-INST: auipc a2, 171
+# CHECK-INST-NEXT: addiw a2, a2, -1365
+# CHECK-INST-NEXT: slli a2, a2, 12
+# CHECK-INST-NEXT: addi    a2, a2, -1366
+la x12, 0xaaaaaaaa
+
+# CHECK-INST: auipc a3, 1048405
+# CHECK-INST-NEXT: addiw a3, a3, 1365
+# CHECK-INST-NEXT: slli a3, a3, 12
+# CHECK-INST-NEXT: addi a3, a3, 1366
+la x13, 0xffffffff55555556
+
+# CHECK-S-OBJ-NOALIAS: auipc t0, 524288
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t0, t0, -1365
+# CHECK-S-OBJ: auipc t0, 524288
+# CHECK-S-OBJ-NEXT: addiw t0, t0, -1365
+la x5, -2147485013
+
+.equ CONST, 0x123456
+# CHECK-EXPAND: auipc a0, 291
+# CHECK-EXPAND: addiw a0, a0, 1110
+la a0, CONST
+
+.equ CONST, 0x654321
+# CHECK-EXPAND: auipc a0, 1620
+# CHECK-EXPAND: addiw a0, a0, 801
+la a0, CONST
+
 # CHECK-INST: subw t6, zero, ra
 # CHECK-ALIAS: negw t6, ra
 negw x31, x1

llvm/test/MC/RISCV/rvi-pseudos-invalid.s

 lla x1, %hi(foo) # CHECK: :[[@LINE]]:9: error: operand must be a bare symbol name
 lla x1, %lo(foo) # CHECK: :[[@LINE]]:9: error: operand must be a bare symbol name
 
-la x1, 1234 # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
-la x1, %pcrel_hi(1234) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
-la x1, %pcrel_lo(1234) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
-la x1, %pcrel_hi(foo) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
-la x1, %pcrel_lo(foo) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
-la x1, %hi(1234) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
-la x1, %lo(1234) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
-la x1, %hi(foo) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
-la x1, %lo(foo) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
+la x1, %pcrel_hi(1234) # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
+la x1, %pcrel_lo(1234) # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
+la x1, %pcrel_hi(foo) # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
+la x1, %pcrel_lo(foo) # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
+la x1, %hi(1234) # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
+la x1, %lo(1234) # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
+la x1, %hi(foo) # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
+la x1, %lo(foo) # CHECK: :[[@LINE]]:8: error: operand either must be a Bare Symbol or an integer in the range [-2147483648, 4294967295]
 
 sw a2, %hi(a_symbol), a3 # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 sw a2, %lo(a_symbol), a3 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction