[RISCV] Rewrite all found class-based subroutines to functions

[wangpc]

Summary

In this patch, we rewrite all found class-based subroutines in
RISCV target to functions.

This can be considered as a test of D148915.

[• pcwang-thead]

Rewrite all found subroutines.

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

703

Typo with the '? This also happens multiple times below.

[• pcwang-thead]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

703

No, it is by design. A single quote is added before ( to solve the grammar ambiguity between DAG and function call. The design may be changed however.
Please see https://discourse.llvm.org/t/tablegen-introduce-function-and-lambda/70160#h-13-function-call-5 also. :-)

[michaelmaitland]

LGTM.

[zixuan-wu]

Is it going to commit?

[wangpc]

In D149017#4579179, @zixuan-wu wrote:

Is it going to commit?

This patch is stuck since the patch to support function/lambda is WIP (I may not work on it recently).

clang/include/clang/Basic/riscv_vector.td

 Segment indexed load intrinsic,
   Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, Mask, VL, Policy)
   Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, VL)
 
 The Vector(s) is poison when the policy behavior allows us to not care
 about any masked-off elements.
 */
 
-class PVString<int nf, bit signed> {
-  string S =
+function PVString(int nf, bit signed): string {
+  return
     !cond(!eq(nf, 2): !if(signed, "PvPv", "PUvPUv"),
           !eq(nf, 3): !if(signed, "PvPvPv", "PUvPUvPUv"),
           !eq(nf, 4): !if(signed, "PvPvPvPv", "PUvPUvPUvPUv"),
           !eq(nf, 5): !if(signed, "PvPvPvPvPv", "PUvPUvPUvPUvPUv"),
           !eq(nf, 6): !if(signed, "PvPvPvPvPvPv", "PUvPUvPUvPUvPUvPUv"),
           !eq(nf, 7): !if(signed, "PvPvPvPvPvPvPv", "PUvPUvPUvPUvPUvPUvPUv"),
           !eq(nf, 8): !if(signed, "PvPvPvPvPvPvPvPv", "PUvPUvPUvPUvPUvPUvPUvPUv"));
 }
defvar eew = !cond(!eq(type, "c") : "8",
       llvm::Value *V;
       for (unsigned I = 0; I < NF; ++I) {
         llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
         V = Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
       }
       return V;
     }
     }] in {
-          defvar PV = PVString<nf, /*signed=*/true>.S;
-          defvar PUV = PVString<nf, /*signed=*/false>.S;
+          defvar PV = PVString(nf, /*signed=*/true);
+          defvar PUV = PVString(nf, /*signed=*/false);
           def : RVVBuiltin<"v", "0" # PV # "PCe", type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0" # PUV # "PCUe", type>;
         }
       }
     }
   }
 }
defvar eew = !cond(!eq(type, "c") : "8",
         llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
         Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
       }
       // Store new_vl.
       llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {NF});
       return Builder.CreateStore(Val, Address(NewVLOperand, Val->getType(), Align));
     }
     }] in {
-          defvar PV = PVString<nf, /*signed=*/true>.S;
-          defvar PUV = PVString<nf, /*signed=*/false>.S;
+          defvar PV = PVString(nf, /*signed=*/true);
+          defvar PUV = PVString(nf, /*signed=*/false);
           def : RVVBuiltin<"v", "0" # PV # "PCe" # "Pz", type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # "Pz", type>;
         }
       }
     }
   }
 }
defvar eew = !cond(!eq(type, "c") : "8",
       llvm::Value *V;
       for (unsigned I = 0; I < NF; ++I) {
         llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
         V = Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
       }
       return V;
     }
     }] in {
-          defvar PV = PVString<nf, /*signed=*/true>.S;
-          defvar PUV = PVString<nf, /*signed=*/false>.S;
+          defvar PV = PVString(nf, /*signed=*/true);
+          defvar PUV = PVString(nf, /*signed=*/false);
           def : RVVBuiltin<"v", "0" # PV # "PCe" # "t", type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # "t", type>;
         }
       }
     }
   }
 }
foreach eew_info = EEWList in {
       llvm::Value *V;
       for (unsigned I = 0; I < NF; ++I) {
         llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
         V = Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
       }
       return V;
     }
     }] in {
-          defvar PV = PVString<nf, /*signed=*/true>.S;
-          defvar PUV = PVString<nf, /*signed=*/false>.S;
+          defvar PV = PVString(nf, /*signed=*/true);
+          defvar PUV = PVString(nf, /*signed=*/false);
           def : RVVBuiltin<"v", "0" # PV # "PCe" # eew_type # "Uv", type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # eew_type # "Uv", type>;
           }
         }
       }
     }
   }
 }
 
-class VString<int nf, bit signed> {
-  string S = !cond(!eq(nf, 2): !if(signed, "vv", "UvUv"),
-                   !eq(nf, 3): !if(signed, "vvv", "UvUvUv"),
-                   !eq(nf, 4): !if(signed, "vvvv", "UvUvUvUv"),
-                   !eq(nf, 5): !if(signed, "vvvvv", "UvUvUvUvUv"),
-                   !eq(nf, 6): !if(signed, "vvvvvv", "UvUvUvUvUvUv"),
-                   !eq(nf, 7): !if(signed, "vvvvvvv", "UvUvUvUvUvUvUv"),
-                   !eq(nf, 8): !if(signed, "vvvvvvvv", "UvUvUvUvUvUvUvUv"));
+function VString(int nf, bit signed): string {
+  return !cond(!eq(nf, 2): !if(signed, "vv", "UvUv"),
 }
 
 multiclass RVVUnitStridedSegStore<string op> {
   foreach type = TypeList in {
     defvar eew = !cond(!eq(type, "c") : "8",
                        !eq(type, "s") : "16",
                        !eq(type, "i") : "32",
                        !eq(type, "l") : "64",
defvar eew = !cond(!eq(type, "c") : "8",
         // Builtin: (ptr, val0, val1, ..., vl)
         // Intrinsic: (val0, val1, ..., ptr, vl)
         std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
         IntrinsicTypes = {Ops[0]->getType(), Ops[NF + 1]->getType()};
         assert(Ops.size() == NF + 2);
       }
     }
             }] in {
-          defvar V = VString<nf, /*signed=*/true>.S;
-          defvar UV = VString<nf, /*signed=*/false>.S;
+          defvar V = VString(nf, /*signed=*/true);
+          defvar UV = VString(nf, /*signed=*/false);
           def : RVVBuiltin<"v", "0Pe" # V, type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0PUe" # UV, type>;
         }
       }
     }
   }
 }
defvar eew = !cond(!eq(type, "c") : "8",
         // Builtin: (ptr, stride, val0, val1, ..., vl).
         // Intrinsic: (val0, val1, ..., ptr, stride, vl)
         std::rotate(Ops.begin(), Ops.begin() + 2, Ops.end() - 1);
         assert(Ops.size() == NF + 3);
       }
       IntrinsicTypes = {Ops[0]->getType(), Ops[NF + 1]->getType()};
     }
             }] in {
-          defvar V = VString<nf, /*signed=*/true>.S;
-          defvar UV = VString<nf, /*signed=*/false>.S;
+          defvar V = VString(nf, /*signed=*/true);
+          defvar UV = VString(nf, /*signed=*/false);
           def : RVVBuiltin<"v", "0Pet" # V, type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0PUet" # UV, type>;
         }
       }
     }
   }
 }
foreach eew_info = EEWList in {
         // Intrinsic: (val0, val1, ..., ptr, index, vl)
         std::rotate(Ops.begin(), Ops.begin() + 2, Ops.end() - 1);
         IntrinsicTypes = {Ops[0]->getType(),
                           Ops[NF + 1]->getType(), Ops[NF + 2]->getType()};
         assert(Ops.size() == NF + 3);
       }
     }
             }] in {
-          defvar V = VString<nf, /*signed=*/true>.S;
-          defvar UV = VString<nf, /*signed=*/false>.S;
+          defvar V = VString(nf, /*signed=*/true);
+          defvar UV = VString(nf, /*signed=*/false);
           def : RVVBuiltin<"v", "0Pe" # eew_type # "Uv" # V, type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0PUe" # eew_type # "Uv" # UV, type>;
           }
         }
       }
     }
   }

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 defvar TAIL_UNDISTURBED_MASK_UNDISTURBED = 0;
 defvar TAIL_AGNOSTIC = 1;
 defvar TA_MA = 3;
 
 //===----------------------------------------------------------------------===//
 // Utilities.
 //===----------------------------------------------------------------------===//
 
-class PseudoToVInst<string PseudoInst> {
+function PseudoToVInst(string PseudoInst): string {
   defvar AffixSubsts = [["Pseudo", ""],
                         ["_E64", ""],
                         ["_E32", ""],
                         ["_E16", ""],
                         ["_E8", ""],
                         ["_F64", "_F"],
                         ["_F32", "_F"],
                         ["_F16", "_F"],
defvar AffixSubsts = [["Pseudo", ""],
                         ["_MF8", ""],
                         ["_MF4", ""],
                         ["_MF2", ""],
                         ["_M1", ""],
                         ["_M2", ""],
                         ["_M4", ""],
                         ["_M8", ""]
                        ];
-  string VInst = !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst,
-                        !subst(AffixSubst[0], AffixSubst[1], Acc));
+  return !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst,
 }
 
 // This class describes information associated to the LMUL.
 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
                VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
   bits<3> value = lmul; // This is encoded as the vlmul field of vtype.
   VReg vrclass = regclass;
   VReg wvrclass = wregclass;

 defvar MxListVF2 = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
 
 // Use for zext/sext.vf4
 defvar MxListVF4 = [V_MF2, V_M1, V_M2, V_M4, V_M8];
 
 // Use for zext/sext.vf8
 defvar MxListVF8 = [V_M1, V_M2, V_M4, V_M8];
 
-class MxSet<int eew> {
-  list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
-                           !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
-                           !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],
-                           !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
+function MxSet(int eew): list<LMULInfo> {
+  return !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
 }
 
 class FPR_Info<RegisterClass regclass, string fx, list<LMULInfo> mxlist,
                list<LMULInfo> mxlistfw> {
   RegisterClass fprclass = regclass;
   string FX = fx;
   list<LMULInfo> MxList = mxlist;
   list<LMULInfo> MxListFW = mxlistfw;
 }
 
-def SCALAR_F16 : FPR_Info<FPR16, "F16", MxSet<16>.m, [V_MF4, V_MF2, V_M1, V_M2, V_M4]>;
-def SCALAR_F32 : FPR_Info<FPR32, "F32", MxSet<32>.m, [V_MF2, V_M1, V_M2, V_M4]>;
-def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet<64>.m, []>;
+def SCALAR_F16 : FPR_Info<FPR16, "F16", MxSet(16), [V_MF4, V_MF2, V_M1, V_M2, V_M4]>;
+def SCALAR_F32 : FPR_Info<FPR32, "F32", MxSet(32), [V_MF2, V_M1, V_M2, V_M4]>;
+def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet(64), []>;
 
 defvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64];
 
 // Used for widening instructions. It excludes F64.
 defvar FPListW = [SCALAR_F16, SCALAR_F32];
 
-class NFSet<LMULInfo m> {
-  list<int> L = !cond(!eq(m.value, V_M8.value): [],
-                      !eq(m.value, V_M4.value): [2],
-                      !eq(m.value, V_M2.value): [2, 3, 4],
-                      true: [2, 3, 4, 5, 6, 7, 8]);
+function NFSet(LMULInfo m): list<int> {
+  return !cond(!eq(m.value, V_M8.value): [],
 }
 
-class log2<int num> {
-  int val = !if(!eq(num, 1), 0, !add(1, log2<!srl(num, 1)>.val));
+function log2(int num): int {
+  return !if(!eq(num, 1), 0, !add(1, log2(!srl(num, 1))));
 }
 
-class octuple_to_str<int octuple> {
-  string ret = !cond(!eq(octuple, 1): "MF8",
-                     !eq(octuple, 2): "MF4",
-                     !eq(octuple, 4): "MF2",
-                     !eq(octuple, 8): "M1",
-                     !eq(octuple, 16): "M2",
-                     !eq(octuple, 32): "M4",
-                     !eq(octuple, 64): "M8");
+function octuple_to_str(int octuple): string {
+  return !cond(!eq(octuple, 1): "MF8",
 }
 
 def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>;
 
 // Output pattern for X0 used to represent VLMAX in the pseudo instructions.
 // We can't use X0 register becuase the AVL operands use GPRNoX0.
 // This must be kept in sync with RISCV::VLMaxSentinel.
 def VLMax : OutPatFrag<(ops), (XLenVT -1)>;
 
 // List of EEW.
 defvar EEWList = [8, 16, 32, 64];
 
-class SegRegClass<LMULInfo m, int nf> {
-  VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
-                                           !eq(m.value, V_MF4.value): V_M1.MX,
-                                           !eq(m.value, V_MF2.value): V_M1.MX,
-                                           true: m.MX));
+function SegRegClass(LMULInfo m, int nf): VReg {
+  return !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
 }
 
 //===----------------------------------------------------------------------===//
 // Vector register and vector group type information.
 //===----------------------------------------------------------------------===//
 
 class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M,
                 ValueType Scal = XLenVT, RegisterClass ScalarReg = GPR>
 {
   ValueType Vector = Vec;
   ValueType Mask = Mas;
   int SEW = Sew;
-  int Log2SEW = log2<Sew>.val;
+  int Log2SEW = log2(Sew);
   VReg RegClass = Reg;
   LMULInfo LMul = M;
   ValueType Scalar = Scal;
   RegisterClass ScalarRegClass = ScalarReg;
   // The pattern fragment which produces the AVL operand, representing the
   // "natural" vector length for this type. For scalable vectors this is VLMax.
   OutPatFrag AVL = VLMax;
 
defset list<GroupVTypeInfo> GroupFloatVectors = {
       def VF64M4: GroupVTypeInfo<vfloat64m4_t, vfloat64m1_t, vbool16_t, 64,
                                  VRM4, V_M4, f64, FPR64>;
       def VF64M8: GroupVTypeInfo<vfloat64m8_t, vfloat64m1_t, vbool8_t,  64,
                                  VRM8, V_M8, f64, FPR64>;
     }
   }
 }
 
-// This functor is used to obtain the int vector type that has the same SEW and
+// This function is used to obtain the int vector type that has the same SEW and
 // multiplier as the input parameter type
-class GetIntVTypeInfo<VTypeInfo vti>
-{
+function GetIntVTypeInfo(VTypeInfo vti): VTypeInfo {
   // Equivalent integer vector type. Eg.
   //   VI8M1 → VI8M1 (identity)
   //   VF64M4 → VI64M4
-  VTypeInfo Vti = !cast<VTypeInfo>(!subst("VF", "VI", !cast<string>(vti)));
+  return !cast<VTypeInfo>(!subst("VF", "VI", !cast<string>(vti)));
 }
 
 class MTypeInfo<ValueType Mas, LMULInfo M, string Bx> {
   ValueType Mask = Mas;
   // {SEW, VLMul} values set a valid VType to deal with this mask type.
   // we assume SEW=1 and set corresponding LMUL. vsetvli insertion will
   // look for SEW=1 to optimize based on surrounding instructions.
   int SEW = 1;

 // The definition should be consistent with `struct PseudoInfo` in
 // RISCVBaseInfo.h.
 class CONST8b<bits<8> val> {
   bits<8> V = val;
 }
 def InvalidIndex : CONST8b<0x80>;
 class RISCVVPseudo {
   Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
-  Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+  Instruction BaseInstr = !cast<Instruction>(PseudoToVInst(NAME));
 }
 
 // The actual table.
 def RISCVVPseudosTable : GenericTable {
   let FilterClass = "RISCVVPseudo";
   let CppTypeName = "PseudoInfo";
   let Fields = [ "Pseudo", "BaseInstr" ];
   let PrimaryKey = [ "Pseudo" ];

 //===----------------------------------------------------------------------===//
 // Helpers to define the different pseudo instructions.
 //===----------------------------------------------------------------------===//
 
 // The destination vector register group for a masked vector instruction cannot
 // overlap the source mask register (v0), unless the destination vector register
 // is being written with a mask value (e.g., comparisons) or the scalar result
 // of a reduction.
-class GetVRegNoV0<VReg VRegClass> {
-  VReg R = !cond(!eq(VRegClass, VR) : VRNoV0,
-                 !eq(VRegClass, VRM2) : VRM2NoV0,
-                 !eq(VRegClass, VRM4) : VRM4NoV0,
-                 !eq(VRegClass, VRM8) : VRM8NoV0,
-                 !eq(VRegClass, VRN2M1) : VRN2M1NoV0,
-                 !eq(VRegClass, VRN2M2) : VRN2M2NoV0,
-                 !eq(VRegClass, VRN2M4) : VRN2M4NoV0,
-                 !eq(VRegClass, VRN3M1) : VRN3M1NoV0,
-                 !eq(VRegClass, VRN3M2) : VRN3M2NoV0,
-                 !eq(VRegClass, VRN4M1) : VRN4M1NoV0,
-                 !eq(VRegClass, VRN4M2) : VRN4M2NoV0,
-                 !eq(VRegClass, VRN5M1) : VRN5M1NoV0,
-                 !eq(VRegClass, VRN6M1) : VRN6M1NoV0,
-                 !eq(VRegClass, VRN7M1) : VRN7M1NoV0,
-                 !eq(VRegClass, VRN8M1) : VRN8M1NoV0,
-                 true : VRegClass);
+function GetVRegNoV0(VReg VRegClass): VReg {
+  return !cond(!eq(VRegClass, VR) : VRNoV0,
 }
 
 // Join strings in list using separator and ignoring empty elements
-class Join<list<string> strings, string separator> {
-  string ret = !foldl(!head(strings), !tail(strings), a, b,
-                      !cond(
-                        !and(!empty(a), !empty(b)) : "",
-                        !empty(a) : b,
-                        !empty(b) : a,
-                        1 : a#separator#b));
+function Join(list<string> strings, string separator): string {
+  return !foldl(!head(strings), !tail(strings), a, b,
 }
 
 class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins> :
       Pseudo<outs, ins, []>, RISCVVPseudo {
   let BaseInstr = instr;
   let VLMul = m.value;
 }
 
 class VPseudoUSLoadNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
       Pseudo<(outs RetClass:$rd),
              (ins GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = DummyMask;
 }
 
 class VPseudoUSLoadNoMaskTU<VReg RetClass, int EEW> :
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
   let Constraints = "$rd = $dest";
 }
 
 class VPseudoUSLoadMask<VReg RetClass, int EEW> :
-      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-              (ins GetVRegNoV0<RetClass>.R:$merge,
+      Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+              (ins GetVRegNoV0'(RetClass):$merge,
                    GPRMem:$rs1,
                    VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
       RISCVVPseudo,
-      RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let Constraints = "$rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoUSLoadFFNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
       Pseudo<(outs RetClass:$rd, GPR:$vl),
              (ins GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+      RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = DummyMask;
 }
 
 class VPseudoUSLoadFFNoMaskTU<VReg RetClass, int EEW> :
       Pseudo<(outs RetClass:$rd, GPR:$vl),
              (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+      RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
   let Constraints = "$rd = $dest";
 }
 
 class VPseudoUSLoadFFMask<VReg RetClass, int EEW> :
-      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
-              (ins GetVRegNoV0<RetClass>.R:$merge,
+      Pseudo<(outs GetVRegNoV0'(RetClass):$rd, GPR:$vl),
+              (ins GetVRegNoV0'(RetClass):$merge,
                    GPRMem:$rs1,
                    VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy),[]>,
       RISCVVPseudo,
-      RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+      RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let Constraints = "$rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoSLoadNoMask<VReg RetClass, int EEW>:
       Pseudo<(outs RetClass:$rd),
              (ins GPRMem:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoSLoadNoMaskTU<VReg RetClass, int EEW>:
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
   let Constraints = "$rd = $dest";
 }
 
 class VPseudoSLoadMask<VReg RetClass, int EEW>:
-      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-              (ins GetVRegNoV0<RetClass>.R:$merge,
+      Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+              (ins GetVRegNoV0'(RetClass):$merge,
                    GPRMem:$rs1, GPR:$rs2,
                    VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
       RISCVVPseudo,
-      RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let Constraints = "$rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
                          bit Ordered, bit EarlyClobber>:
       Pseudo<(outs RetClass:$rd),
              (ins GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
               ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLX</*Masked*/0, /*TU*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVLX</*Masked*/0, /*TU*/0, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd", "");
 }
 
 class VPseudoILoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
                            bit Ordered, bit EarlyClobber>:
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
               ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLX</*Masked*/0, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVLX</*Masked*/0, /*TU*/1, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
   let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $dest", "$rd = $dest");
 }
 
 class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
                        bit Ordered, bit EarlyClobber>:
-      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-              (ins GetVRegNoV0<RetClass>.R:$merge,
+      Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+              (ins GetVRegNoV0'(RetClass):$merge,
                    GPRMem:$rs1, IdxClass:$rs2,
                    VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
       RISCVVPseudo,
-      RISCVVLX</*Masked*/1, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVLX</*Masked*/1, /*TU*/1, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoUSStoreNoMask<VReg StClass, int EEW, bit DummyMask = 1>:
       Pseudo<(outs),
               (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSE</*Masked*/0, /*Strided*/0, log2<EEW>.val, VLMul> {
+      RISCVVSE</*Masked*/0, /*Strided*/0, log2(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = DummyMask;
 }
 
 class VPseudoUSStoreMask<VReg StClass, int EEW>:
       Pseudo<(outs),
               (ins StClass:$rd, GPRMem:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSE</*Masked*/1, /*Strided*/0, log2<EEW>.val, VLMul> {
+      RISCVVSE</*Masked*/1, /*Strided*/0, log2(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
 }
 
 class VPseudoSStoreNoMask<VReg StClass, int EEW>:
       Pseudo<(outs),
               (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSE</*Masked*/0, /*Strided*/1, log2<EEW>.val, VLMul> {
+      RISCVVSE</*Masked*/0, /*Strided*/1, log2(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoSStoreMask<VReg StClass, int EEW>:
       Pseudo<(outs),
               (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSE</*Masked*/1, /*Strided*/1, log2<EEW>.val, VLMul> {
+      RISCVVSE</*Masked*/1, /*Strided*/1, log2(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
 }
 
 // Unary instruction that is never masked so HasDummyMask=0.
class VPseudoNullaryNoMaskTU<VReg RegClass>:
   let Constraints = "$rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
 }
 
 class VPseudoNullaryMask<VReg RegClass>:
-      Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
-             (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
+      Pseudo<(outs GetVRegNoV0'(RegClass):$rd),
+             (ins GetVRegNoV0'(RegClass):$merge, VMaskOp:$vm, AVL:$vl,
               ixlenimm:$sew, ixlenimm:$policy), []>, RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let Constraints ="$rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;

 // RetClass could be GPR or VReg.
 class VPseudoUnaryNoMaskTU<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
       Pseudo<(outs RetClass:$rd),
         (ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
 }
 
 class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
-        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-               (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
+        Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+               (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2,
                     VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoUnaryMaskTA<VReg RetClass, VReg OpClass, string Constraint = ""> :
-        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-               (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
+        Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+               (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2,
                     VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoUnaryMaskTA_NoExcept<VReg RetClass, VReg OpClass, string Constraint = ""> :
-        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-               (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, VMaskOp:$vm,
+        Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+               (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2, VMaskOp:$vm,
                     AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
   let usesCustomInserter = 1;
 }
 
 class VPseudoUnaryMaskTA_FRM<VReg RetClass, VReg OpClass, string Constraint = ""> :
-        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-               (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
+        Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+               (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2,
                     VMaskOp:$vm, ixlenimm:$frm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
   let usesCustomInserter = 1;
 }
 
class VPseudoBinaryNoMaskTU<VReg RetClass,
                             DAGOperand Op2Class,
                             string Constraint> :
         Pseudo<(outs RetClass:$rd),
                (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
 }
 
 // Special version of VPseudoBinaryNoMask where we pretend the first source is
 // tied to the destination.
 // This allows maskedoff and rs2 to be the same register.
 class VPseudoTiedBinaryNoMask<VReg RetClass,
                               DAGOperand Op2Class,
                               string Constraint> :
         Pseudo<(outs RetClass:$rd),
                (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew,
                     ixlenimm:$policy), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $rs2"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $rs2"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasVecPolicyOp = 1;
   let isConvertibleToThreeAddress = 1;
 }
 
 class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
                           bit Ordered>:
       Pseudo<(outs),
               (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSX</*Masked*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVSX</*Masked*/0, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
                         bit Ordered>:
       Pseudo<(outs),
               (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSX</*Masked*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVSX</*Masked*/1, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
 }
 
 class VPseudoBinaryMask<VReg RetClass,
                         RegisterClass Op1Class,
                         DAGOperand Op2Class,
                         string Constraint> :
-        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-                (ins GetVRegNoV0<RetClass>.R:$merge,
+        Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+                (ins GetVRegNoV0'(RetClass):$merge,
                      Op1Class:$rs2, Op2Class:$rs1,
                      VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
 }
 
 class VPseudoBinaryMaskPolicy<VReg RetClass,
                               RegisterClass Op1Class,
                               DAGOperand Op2Class,
                               string Constraint> :
-        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-                (ins GetVRegNoV0<RetClass>.R:$merge,
+        Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+                (ins GetVRegNoV0'(RetClass):$merge,
                      Op1Class:$rs2, Op2Class:$rs1,
                      VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoBinaryTailPolicy<VReg RetClass,
                               RegisterClass Op1Class,
                               DAGOperand Op2Class,
                               string Constraint> :
-        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-                (ins GetVRegNoV0<RetClass>.R:$merge,
+        Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+                (ins GetVRegNoV0'(RetClass):$merge,
                      Op1Class:$rs2, Op2Class:$rs1,
                      VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
 }
 
 // Like VPseudoBinaryMask, but output can be V0.
 class VPseudoBinaryMOutMask<VReg RetClass,
                             RegisterClass Op1Class,
                             DAGOperand Op2Class,
                             string Constraint> :
         Pseudo<(outs RetClass:$rd),
                 (ins RetClass:$merge,
                      Op1Class:$rs2, Op2Class:$rs1,
                      VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 // Special version of VPseudoBinaryMask where we pretend the first source is
 // tied to the destination so we can workaround the earlyclobber constraint.
 // This allows maskedoff and rs2 to be the same register.
 class VPseudoTiedBinaryMask<VReg RetClass,
                             DAGOperand Op2Class,
                             string Constraint> :
-        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-                (ins GetVRegNoV0<RetClass>.R:$merge,
+        Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+                (ins GetVRegNoV0'(RetClass):$merge,
                      Op2Class:$rs1,
                      VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 0; // Merge is also rs2.
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoBinaryCarryIn<VReg RetClass,
class VPseudoTiedBinaryCarryIn<VReg RetClass,
                !if(CarryIn,
                   (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, AVL:$vl,
                        ixlenimm:$sew),
                   (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew)), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $merge"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 0;
   let VLMul = MInfo.value;
 }
 
 class VPseudoTernaryNoMask<VReg RetClass,
                            RegisterClass Op1Class,
                            DAGOperand Op2Class,
                            string Constraint> :
         Pseudo<(outs RetClass:$rd),
                (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
                     AVL:$vl, ixlenimm:$sew),
                []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $rs3"], ",");
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
                                      RegisterClass Op1Class,
                                      DAGOperand Op2Class,
                                      string Constraint> :
         Pseudo<(outs RetClass:$rd),
                (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
                     AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),
                []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret;
+  let Constraints = Join([Constraint, "$rd = $rs3"], ",");
   let HasVecPolicyOp = 1;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoUSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
       Pseudo<(outs RetClass:$rd),
              (ins GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoUSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
   let Constraints = "$rd = $dest";
 }
 
 class VPseudoUSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
-      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-             (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1,
+      Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+             (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1,
                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
       RISCVVPseudo,
-      RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let Constraints = "$rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoUSSegLoadFFNoMask<VReg RetClass, int EEW, bits<4> NF>:
       Pseudo<(outs RetClass:$rd, GPR:$vl),
              (ins GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+      RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoUSSegLoadFFNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
       Pseudo<(outs RetClass:$rd, GPR:$vl),
              (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+      RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
   let Constraints = "$rd = $dest";
 }
 
 class VPseudoUSSegLoadFFMask<VReg RetClass, int EEW, bits<4> NF>:
-      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
-             (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1,
+      Pseudo<(outs GetVRegNoV0'(RetClass):$rd, GPR:$vl),
+             (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1,
                   VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy),[]>,
       RISCVVPseudo,
-      RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+      RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let Constraints = "$rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
       Pseudo<(outs RetClass:$rd),
              (ins GPRMem:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$merge, GPRMem:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
   let Constraints = "$rd = $merge";
 }
 
 class VPseudoSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
-      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-             (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1,
+      Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+             (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1,
                   GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew,
                   ixlenimm:$policy),[]>,
       RISCVVPseudo,
-      RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+      RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let Constraints = "$rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoISegLoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
                             bits<4> NF, bit Ordered>:
       Pseudo<(outs RetClass:$rd),
              (ins GPRMem:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLXSEG<NF, /*Masked*/0, /*TU*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVLXSEG<NF, /*Masked*/0, /*TU*/0, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   // For vector indexed segment loads, the destination vector register groups
   // cannot overlap the source vector register group
   let Constraints = "@earlyclobber $rd";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoISegLoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
                               bits<4> NF, bit Ordered>:
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$merge, GPRMem:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVLXSEG<NF, /*Masked*/0, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVLXSEG<NF, /*Masked*/0, /*TU*/1, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   // For vector indexed segment loads, the destination vector register groups
   // cannot overlap the source vector register group
   let Constraints = "@earlyclobber $rd, $rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let HasMergeOp = 1;
 }
 
 class VPseudoISegLoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
                           bits<4> NF, bit Ordered>:
-      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-             (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1,
+      Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+             (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1,
                   IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew,
                   ixlenimm:$policy),[]>,
       RISCVVPseudo,
-      RISCVVLXSEG<NF, /*Masked*/1, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVLXSEG<NF, /*Masked*/1, /*TU*/1, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   // For vector indexed segment loads, the destination vector register groups
   // cannot overlap the source vector register group
   let Constraints = "@earlyclobber $rd, $rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
 }
 
 class VPseudoUSSegStoreNoMask<VReg ValClass, int EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, log2<EEW>.val, VLMul> {
+      RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, log2(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoUSSegStoreMask<VReg ValClass, int EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPRMem:$rs1,
                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, log2<EEW>.val, VLMul> {
+      RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, log2(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
 }
 
 class VPseudoSSegStoreNoMask<VReg ValClass, int EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPRMem:$rs1, GPR: $offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, log2<EEW>.val, VLMul> {
+      RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, log2(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoSSegStoreMask<VReg ValClass, int EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPRMem:$rs1, GPR: $offset,
                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, log2<EEW>.val, VLMul> {
+      RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, log2(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
 }
 
 class VPseudoISegStoreNoMask<VReg ValClass, VReg IdxClass, int EEW, bits<3> LMUL,
                              bits<4> NF, bit Ordered>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
                   AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSXSEG<NF, /*Masked*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVSXSEG<NF, /*Masked*/0, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
 }
 
 class VPseudoISegStoreMask<VReg ValClass, VReg IdxClass, int EEW, bits<3> LMUL,
                            bits<4> NF, bit Ordered>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
-      RISCVVSXSEG<NF, /*Masked*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+      RISCVVSXSEG<NF, /*Masked*/1, Ordered, log2(EEW), VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let HasVLOp = 1;
   let HasSEWOp = 1;
 }
 
 multiclass VPseudoUSLoad {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
       let VLMul = lmul.value in {
         def "E" # eew # "_V_" # LInfo :
           VPseudoUSLoadNoMask<vreg, eew>,
           VLESched<LInfo>;
         def "E" # eew # "_V_" # LInfo # "_TU":
           VPseudoUSLoadNoMaskTU<vreg, eew>,
           VLESched<LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" :
           VPseudoUSLoadMask<vreg, eew>,
           RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
           VLESched<LInfo>;
       }
     }
   }
 }
 
 multiclass VPseudoFFLoad {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
       let VLMul = lmul.value in {
         def "E" # eew # "FF_V_" # LInfo:
           VPseudoUSLoadFFNoMask<vreg, eew>,
           VLFSched<LInfo>;
         def "E" # eew # "FF_V_" # LInfo # "_TU":
           VPseudoUSLoadFFNoMaskTU<vreg, eew>,
let VLMul = mti.LMul.value in {
       def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, /*EEW*/1, /*DummyMask*/0>,
         Sched<[WriteVLDM_MX, ReadVLDX]>;
     }
   }
 }
 
 multiclass VPseudoSLoad {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
       let VLMul = lmul.value in {
         def "E" # eew # "_V_" # LInfo : VPseudoSLoadNoMask<vreg, eew>,
                                         VLSSched<eew, LInfo>;
         def "E" # eew # "_V_" # LInfo # "_TU": VPseudoSLoadNoMaskTU<vreg, eew>,
                                         VLSSched<eew, LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" :
           VPseudoSLoadMask<vreg, eew>,
           RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
           VLSSched<eew, LInfo>;
       }
     }
   }
 }
 
 multiclass VPseudoILoad<bit Ordered> {
   foreach eew = EEWList in {
     foreach sew = EEWList in {
-      foreach lmul = MxSet<sew>.m in {
+      foreach lmul = MxSet(sew) in {
         defvar octuple_lmul = lmul.octuple;
         // Calculate emul = eew * lmul / sew
-        defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
+        defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2(sew));
         if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
           defvar DataLInfo = lmul.MX;
-          defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+          defvar IdxLInfo = octuple_to_str(octuple_emul);
           defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = lmul.vrclass;
           defvar IdxVreg = idx_lmul.vrclass;
           defvar HasConstraint = !ne(sew, eew);
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = lmul.value in {
             def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoILoadNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
foreach sew = EEWList in {
         }
       }
     }
   }
 }
 
 multiclass VPseudoUSStore {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
       let VLMul = lmul.value in {
         def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>,
                                         VSESched<LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>,
                                                   VSESched<LInfo>;
       }
let VLMul = mti.LMul.value in {
       def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, /*EEW*/1, /*DummyMask*/0>,
         Sched<[WriteVSTM_MX, ReadVSTX]>;
     }
   }
 }
 
 multiclass VPseudoSStore {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
       let VLMul = lmul.value in {
         def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg, eew>,
                                         VSSSched<eew, LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg, eew>,
                                                   VSSSched<eew, LInfo>;
       }
     }
   }
 }
 
 multiclass VPseudoIStore<bit Ordered> {
   foreach eew = EEWList in {
     foreach sew = EEWList in {
-      foreach lmul = MxSet<sew>.m in {
+      foreach lmul = MxSet(sew) in {
         defvar octuple_lmul = lmul.octuple;
         // Calculate emul = eew * lmul / sew
-        defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
+        defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2(sew));
         if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
           defvar DataLInfo = lmul.MX;
-          defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+          defvar IdxLInfo = octuple_to_str(octuple_emul);
           defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = lmul.vrclass;
           defvar IdxVreg = idx_lmul.vrclass;
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = lmul.value in {
             def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoIStoreNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered>,
               VSXSched<eew, Order, DataLInfo, IdxLInfo>;
let VLMul = m.value in {
                                  Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVCPR_V {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSet<mx>.val;
+    defvar sews = SchedSEWSet(mx);
     let VLMul = m.value in
       foreach e = sews in {
         defvar suffix = "_" # m.MX # "_E" # e;
         defvar WriteVCompressV_MX_E = !cast<SchedWrite>("WriteVCompressV" # suffix);
         defvar ReadVCompressV_MX_E = !cast<SchedRead>("ReadVCompressV" # suffix);
 
         def _VM # suffix : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>,
                            Sched<[WriteVCompressV_MX_E, ReadVCompressV_MX_E, ReadVCompressV_MX_E]>;

 }
 
 multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
     foreach sew = EEWList in {
       defvar octuple_lmul = m.octuple;
       // emul = lmul * eew / sew
-      defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2<sew>.val);
+      defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2(sew));
       if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
-        defvar emulMX = octuple_to_str<octuple_emul>.ret;
+        defvar emulMX = octuple_to_str(octuple_emul);
         defvar emul = !cast<LMULInfo>("V_" # emulMX);
-        defvar sews = SchedSEWSet<mx>.val;
+        defvar sews = SchedSEWSet(mx);
         foreach e = sews in {
           defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
           defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
           defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
           defm _VV : VPseudoBinaryEmul_E<m.vrclass, m.vrclass, emul.vrclass, m, e, emul, Constraint>,
                      Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, ReadVRGatherVV_index_MX_E]>;
         }
       }

 // For vadc and vsbc, the instruction encoding is reserved if the destination
 // vector register is v0.
 // For vadc and vsbc, CarryIn == 1 and CarryOut == 0
 multiclass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
                              string Constraint = ""> {
   def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
     VPseudoBinaryCarryIn<!if(CarryOut, VR,
                          !if(!and(CarryIn, !not(CarryOut)),
-                             GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+                             GetVRegNoV0(m.vrclass), m.vrclass)),
                          m.vrclass, m.vrclass, m, CarryIn, Constraint>;
 }
 
 multiclass VPseudoTiedBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
                                  string Constraint = ""> {
   def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU" :
     VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
                              !if(!and(CarryIn, !not(CarryOut)),
-                                 GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+                                 GetVRegNoV0(m.vrclass), m.vrclass)),
                              m.vrclass, m.vrclass, m, CarryIn, Constraint>;
 }
 
 multiclass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
                              string Constraint = ""> {
   def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
     VPseudoBinaryCarryIn<!if(CarryOut, VR,
                          !if(!and(CarryIn, !not(CarryOut)),
-                             GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+                             GetVRegNoV0(m.vrclass), m.vrclass)),
                          m.vrclass, GPR, m, CarryIn, Constraint>;
 }
 
 multiclass VPseudoTiedBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
                                  string Constraint = ""> {
   def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
     VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
                              !if(!and(CarryIn, !not(CarryOut)),
-                                 GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+                                 GetVRegNoV0(m.vrclass), m.vrclass)),
                              m.vrclass, GPR, m, CarryIn, Constraint>;
 }
 
 multiclass VPseudoVMRG_FM {
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
       defvar WriteVFMergeV_MX = !cast<SchedWrite>("WriteVFMergeV_" # mx);
       defvar ReadVFMergeV_MX = !cast<SchedRead>("ReadVFMergeV_" # mx);
       defvar ReadVFMergeF_MX = !cast<SchedRead>("ReadVFMergeF_" # mx);
 
       def "_V" # f.FX # "M_" # mx :
-        VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+        VPseudoBinaryCarryIn<GetVRegNoV0(m.vrclass),
                              m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">,
         Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>;
       // Tied version to allow codegen control over the tail elements
       def "_V" # f.FX # "M_" # mx # "_TU":
-        VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+        VPseudoTiedBinaryCarryIn<GetVRegNoV0(m.vrclass),
                                  m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">,
         Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
                              string Constraint = ""> {
   def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
     VPseudoBinaryCarryIn<!if(CarryOut, VR,
                          !if(!and(CarryIn, !not(CarryOut)),
-                             GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+                             GetVRegNoV0(m.vrclass), m.vrclass)),
                          m.vrclass, simm5, m, CarryIn, Constraint>;
 }
 
 multiclass VPseudoTiedBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
                                  string Constraint = ""> {
   def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
     VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
                              !if(!and(CarryIn, !not(CarryOut)),
-                                 GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+                                 GetVRegNoV0(m.vrclass), m.vrclass)),
                              m.vrclass, simm5, m, CarryIn, Constraint>;
 }
 
 multiclass VPseudoUnaryVMV_V_X_I {
   foreach m = MxList in {
     let VLMul = m.value in {
       defvar mx = m.MX;
       defvar WriteVIMovV_MX = !cast<SchedWrite>("WriteVIMovV_" # mx);
let VLMul = m.value in {
                                  Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVSQR_V {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSetF<m.MX>.val;
+    defvar sews = SchedSEWSetF(mx);
 
     let VLMul = m.value in
       foreach e = sews in {
         defvar suffix = "_" # mx # "_E" # e;
         defvar WriteVFSqrtV_MX_E = !cast<SchedWrite>("WriteVFSqrtV" # suffix);
         defvar ReadVFSqrtV_MX_E = !cast<SchedRead>("ReadVFSqrtV" # suffix);
 
         def "_V" # suffix : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
foreach m = MxList in {
     defvar ReadVRGatherVI_data_MX = !cast<SchedRead>("ReadVRGatherVI_data_" # mx);
 
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
               Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX,
                      ReadVRGatherVX_index_MX, ReadVMask]>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
               Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>;
 
-    defvar sews = SchedSEWSet<mx>.val;
+    defvar sews = SchedSEWSet(mx);
     foreach e = sews in {
       defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
       defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
       defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
       defm "" : VPseudoBinaryV_VV_E<m, e, Constraint>,
                 Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E,
                        ReadVRGatherVV_index_MX_E, ReadVMask]>;
     }
foreach m = MxList in {
     defm "" : VPseudoBinaryV_VX<m>,
               Sched<[WriteVIMulX_MX, ReadVIMulV_MX, ReadVIMulX_MX, ReadVMask]>;
   }
 }
 
 multiclass VPseudoVDIV_VV_VX {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSet<mx>.val;
+    defvar sews = SchedSEWSet(mx);
     foreach e = sews in {
       defvar WriteVIDivV_MX_E = !cast<SchedWrite>("WriteVIDivV_" # mx # "_E" # e);
       defvar WriteVIDivX_MX_E = !cast<SchedWrite>("WriteVIDivX_" # mx # "_E" # e);
       defvar ReadVIDivV_MX_E = !cast<SchedRead>("ReadVIDivV_" # mx # "_E" # e);
       defvar ReadVIDivX_MX_E = !cast<SchedRead>("ReadVIDivX_" # mx # "_E" # e);
 
       defm "" : VPseudoBinaryV_VV_E<m, e>,
                 Sched<[WriteVIDivV_MX_E, ReadVIDivV_MX_E, ReadVIDivV_MX_E, ReadVMask]>;
foreach m = f.MxList in {
                 Sched<[WriteVFMulF_MX, ReadVFMulV_MX, ReadVFMulF_MX, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVFDIV_VV_VF {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSetF<mx>.val;
+    defvar sews = SchedSEWSetF(mx);
     foreach e = sews in {
       defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
       defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
 
       defm "" : VPseudoBinaryFV_VV_E<m, e>,
                 Sched<[WriteVFDivV_MX_E, ReadVFDivV_MX_E, ReadVFDivV_MX_E, ReadVMask]>;
     }
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar sews = SchedSEWSetF<mx>.val;
+      defvar sews = SchedSEWSetF(mx);
       foreach e = sews in {
         defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
         defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
         defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
 
         defm "" : VPseudoBinaryV_VF_E<m, e, f>,
                   Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
       }
     }
   }
 }
 
 multiclass VPseudoVFRDIV_VF {
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar sews = SchedSEWSetF<mx>.val;
+      defvar sews = SchedSEWSetF(mx);
       foreach e = sews in {
         defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
         defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
         defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
 
         defm "" : VPseudoBinaryV_VF_E<m, e, f>,
                   Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
       }

 multiclass VPseudoTernaryWithTailPolicy_E<VReg RetClass,
                                           RegisterClass Op1Class,
                                           DAGOperand Op2Class,
                                           LMULInfo MInfo,
                                           string Constraint = "",
                                           bit Commutable = 0> {
   let VLMul = MInfo.value in {
     defvar mx = MInfo.MX;
-    defvar sews = SchedSEWSet<mx>.val;
+    defvar sews = SchedSEWSet(mx);
     foreach e = sews in {
       let isCommutable = Commutable in
       def "_" # mx # "_E" # e : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
       def "_" # mx # "_E" # e # "_MASK" : VPseudoBinaryTailPolicy<RetClass, Op1Class, Op2Class, Constraint>;
     }
   }
 }
 
foreach m = MxListFW in {
 
     defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
               Sched<[WriteVFNCvtFToFV_MX, ReadVFNCvtFToFV_MX, ReadVMask]>;
   }
 }
 
 multiclass VPseudoUSSegLoad {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       let VLMul = lmul.value in {
-        foreach nf = NFSet<lmul>.L in {
-          defvar vreg = SegRegClass<lmul, nf>.RC;
+        foreach nf = NFSet(lmul) in {
+          defvar vreg = SegRegClass(lmul, nf);
           def nf # "E" # eew # "_V_" # LInfo :
             VPseudoUSSegLoadNoMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_TU" :
             VPseudoUSSegLoadNoMaskTU<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" :
             VPseudoUSSegLoadMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoUSSegLoadFF {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       let VLMul = lmul.value in {
-        foreach nf = NFSet<lmul>.L in {
-          defvar vreg = SegRegClass<lmul, nf>.RC;
+        foreach nf = NFSet(lmul) in {
+          defvar vreg = SegRegClass(lmul, nf);
           def nf # "E" # eew # "FF_V_" # LInfo :
             VPseudoUSSegLoadFFNoMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
           def nf # "E" # eew # "FF_V_" # LInfo # "_TU" :
             VPseudoUSSegLoadFFNoMaskTU<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
           def nf # "E" # eew # "FF_V_" # LInfo # "_MASK" :
             VPseudoUSSegLoadFFMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoSSegLoad {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       let VLMul = lmul.value in {
-        foreach nf = NFSet<lmul>.L in {
-          defvar vreg = SegRegClass<lmul, nf>.RC;
+        foreach nf = NFSet(lmul) in {
+          defvar vreg = SegRegClass(lmul, nf);
           def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>,
                                                VLSSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_TU" : VPseudoSSegLoadNoMaskTU<vreg, eew, nf>,
                                                        VLSSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask<vreg, eew, nf>,
                                                          VLSSEGSched<nf, eew, LInfo>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoISegLoad<bit Ordered> {
   foreach idx_eew = EEWList in {
     foreach sew = EEWList in {
-      foreach val_lmul = MxSet<sew>.m in {
+      foreach val_lmul = MxSet(sew) in {
         defvar octuple_lmul = val_lmul.octuple;
         // Calculate emul = eew * lmul / sew
-        defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2<sew>.val);
+        defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2(sew));
         if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
           defvar ValLInfo = val_lmul.MX;
-          defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+          defvar IdxLInfo = octuple_to_str(octuple_emul);
           defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = val_lmul.vrclass;
           defvar IdxVreg = idx_lmul.vrclass;
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = val_lmul.value in {
-            foreach nf = NFSet<val_lmul>.L in {
-              defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
+            foreach nf = NFSet(val_lmul) in {
+              defvar ValVreg = SegRegClass(val_lmul, nf);
               def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
                 VPseudoISegLoadNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
                                       nf, Ordered>,
                 VLXSEGSched<nf, idx_eew, Order, ValLInfo>;
               def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_TU" :
                 VPseudoISegLoadNoMaskTU<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
                                         nf, Ordered>,
                 VLXSEGSched<nf, idx_eew, Order, ValLInfo>;
               def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" :
                 VPseudoISegLoadMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
                                     nf, Ordered>,
                 VLXSEGSched<nf, idx_eew, Order, ValLInfo>;
             }
           }
         }
       }
     }
   }
 }
 
 multiclass VPseudoUSSegStore {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       let VLMul = lmul.value in {
-        foreach nf = NFSet<lmul>.L in {
-          defvar vreg = SegRegClass<lmul, nf>.RC;
+        foreach nf = NFSet(lmul) in {
+          defvar vreg = SegRegClass(lmul, nf);
           def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>,
                                                VSSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew, nf>,
                                                          VSSEGSched<nf, eew, LInfo>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoSSegStore {
   foreach eew = EEWList in {
-    foreach lmul = MxSet<eew>.m in {
+    foreach lmul = MxSet(eew) in {
       defvar LInfo = lmul.MX;
       let VLMul = lmul.value in {
-        foreach nf = NFSet<lmul>.L in {
-          defvar vreg = SegRegClass<lmul, nf>.RC;
+        foreach nf = NFSet(lmul) in {
+          defvar vreg = SegRegClass(lmul, nf);
           def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>,
                                                VSSSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew, nf>,
                                                          VSSSEGSched<nf, eew, LInfo>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoISegStore<bit Ordered> {
   foreach idx_eew = EEWList in {
     foreach sew = EEWList in {
-      foreach val_lmul = MxSet<sew>.m in {
+      foreach val_lmul = MxSet(sew) in {
         defvar octuple_lmul = val_lmul.octuple;
         // Calculate emul = eew * lmul / sew
-        defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2<sew>.val);
+        defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2(sew));
         if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
           defvar ValLInfo = val_lmul.MX;
-          defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+          defvar IdxLInfo = octuple_to_str(octuple_emul);
           defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = val_lmul.vrclass;
           defvar IdxVreg = idx_lmul.vrclass;
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = val_lmul.value in {
-            foreach nf = NFSet<val_lmul>.L in {
-              defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
+            foreach nf = NFSet(val_lmul) in {
+              defvar ValVreg = SegRegClass(val_lmul, nf);
               def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
                 VPseudoISegStoreNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
                                        nf, Ordered>,
                 VSXSEGSched<nf, idx_eew, Order, ValLInfo>;
               def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" :
                 VPseudoISegStoreMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
                                      nf, Ordered>,
                 VSXSEGSched<nf, idx_eew, Order, ValLInfo>;
defm : VPatBinaryTA<intrinsic,
                         vti.Vector, vti.Vector, vti.Vector,vti.Mask,
                         vti.Log2SEW, vti.RegClass,
                         vti.RegClass, vti.RegClass>;
 }
 
 multiclass VPatBinaryV_VV_INT_E<string intrinsic, string instruction,
                           list<VTypeInfo> vtilist> {
   foreach vti = vtilist in {
-    defvar ivti = GetIntVTypeInfo<vti>.Vti;
+    defvar ivti = GetIntVTypeInfo(vti);
     defm : VPatBinaryTA<intrinsic,
                         instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
                         vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
                         vti.Log2SEW, vti.RegClass,
                         vti.RegClass, vti.RegClass>;
   }
 }
 
 multiclass VPatBinaryV_VV_INT_E_EEW<string intrinsic, string instruction,
                                   int eew, list<VTypeInfo> vtilist> {
   foreach vti = vtilist in {
     // emul = lmul * eew / sew
     defvar vlmul = vti.LMul;
     defvar octuple_lmul = vlmul.octuple;
     defvar octuple_emul = !srl(!mul(octuple_lmul, eew), vti.Log2SEW);
     if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
-      defvar emul_str = octuple_to_str<octuple_emul>.ret;
+      defvar emul_str = octuple_to_str(octuple_emul);
       defvar ivti = !cast<VTypeInfo>("VI" # eew # emul_str);
       defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
       defm : VPatBinaryTA<intrinsic, inst,
                           vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
                           vti.Log2SEW, vti.RegClass,
                           vti.RegClass, ivti.RegClass>;
     }
   }
multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat = 0> {
   }
 }
 
 multiclass VPatConversionVI_VF<string intrinsic,
                                string instruction>
 {
   foreach fvti = AllFloatVectors in
   {
-    defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+    defvar ivti = GetIntVTypeInfo(fvti);
 
     defm : VPatConversionTA<intrinsic, instruction, "V",
                             ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
                             fvti.LMul, ivti.RegClass, fvti.RegClass>;
   }
 }
 
 multiclass VPatConversionVF_VI<string intrinsic,
                                string instruction>
 {
   foreach fvti = AllFloatVectors in
   {
-    defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+    defvar ivti = GetIntVTypeInfo(fvti);
 
     defm : VPatConversionTA<intrinsic, instruction, "V",
                             fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,
                             ivti.LMul, fvti.RegClass, ivti.RegClass>;
   }
 }
 
 multiclass VPatConversionWI_VF<string intrinsic, string instruction> {
   foreach fvtiToFWti = AllWidenableFloatVectors in
   {
     defvar fvti = fvtiToFWti.Vti;
-    defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+    defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
 
     defm : VPatConversionTA<intrinsic, instruction, "V",
                             iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
                             fvti.LMul, iwti.RegClass, fvti.RegClass>;
   }
 }
 
 multiclass VPatConversionWF_VI<string intrinsic, string instruction> {
defm : VPatConversionTA<intrinsic, instruction, "W",
                             vti.LMul, vti.RegClass, fwti.RegClass>;
   }
 }
 
 multiclass VPatConversionVF_WI <string intrinsic, string instruction> {
   foreach fvtiToFWti = AllWidenableFloatVectors in
   {
     defvar fvti = fvtiToFWti.Vti;
-    defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+    defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
 
     defm : VPatConversionTA<intrinsic, instruction, "W",
                             fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,
                             fvti.LMul, fvti.RegClass, iwti.RegClass>;
   }
 }
 
 multiclass VPatConversionVF_WF <string intrinsic, string instruction> {

 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1,
     Uses = [VL] in
 def PseudoReadVL : Pseudo<(outs GPR:$rd), (ins), []>,
                    PseudoInstExpansion<(CSRRS GPR:$rd, SysRegVL.Encoding, X0)>;
 
 foreach lmul = MxList in {
-  foreach nf = NFSet<lmul>.L in {
-    defvar vreg = SegRegClass<lmul, nf>.RC;
+  foreach nf = NFSet(lmul) in {
+    defvar vreg = SegRegClass(lmul, nf);
     let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1,
         Size = !mul(4, !sub(!mul(nf, 2), 1)) in {
       def "PseudoVSPILL" # nf # "_" # lmul.MX :
         Pseudo<(outs), (ins vreg:$rs1, GPR:$rs2), []>;
     }
     let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1,
         Size = !mul(4, !sub(!mul(nf, 2), 1)) in {
       def "PseudoVRELOAD" # nf # "_" # lmul.MX :

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

foreach op = ops in
                 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
                     fti.RegClass:$rs2, fti.AVL, vti.Log2SEW)>;
   }
 }
 
 multiclass VPatConvertI2FPSDNode_V<SDPatternOperator vop,
                                    string instruction_name> {
   foreach fvti = AllFloatVectors in {
-    defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+    defvar ivti = GetIntVTypeInfo(fvti);
     def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
                   ivti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
   }
 }
 
 multiclass VPatConvertFP2ISDNode_V<SDPatternOperator vop,
                                    string instruction_name> {
   foreach fvti = AllFloatVectors in {
-    defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+    defvar ivti = GetIntVTypeInfo(fvti);
     def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
                   fvti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>;
   }
 }
 
 multiclass VPatWConvertI2FPSDNode_V<SDPatternOperator vop,
                                     string instruction_name> {
   foreach vtiToWti = AllWidenableIntToFloatVectors in {
     defvar ivti = vtiToWti.Vti;
     defvar fwti = vtiToWti.Wti;
     def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
                   ivti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>;
   }
 }
 
 multiclass VPatWConvertFP2ISDNode_V<SDPatternOperator vop,
                                     string instruction_name> {
   foreach fvtiToFWti = AllWidenableFloatVectors in {
     defvar fvti = fvtiToFWti.Vti;
-    defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+    defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
     def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
                   fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
   }
 }
 
 multiclass VPatNConvertI2FPSDNode_W<SDPatternOperator vop,
                                     string instruction_name> {
   foreach fvtiToFWti = AllWidenableFloatVectors in {
     defvar fvti = fvtiToFWti.Vti;
-    defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+    defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
     def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
                   iwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
   }
 }
 
 multiclass VPatNConvertFP2ISDNode_W<SDPatternOperator vop,
                                     string instruction_name> {

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2),
                   (fti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
   }
 }
 
 // Single width converting
 
 multiclass VPatConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> {
   foreach fvti = AllFloatVectors in {
-    defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+    defvar ivti = GetIntVTypeInfo(fvti);
     def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
                                 (fvti.Mask V0),
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
                   (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
                   (fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TA_MA)>;
   }
 }
 
 multiclass VPatConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> {
   foreach fvti = AllFloatVectors in {
-    defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+    defvar ivti = GetIntVTypeInfo(fvti);
     def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
                                 (fvti.Mask V0), (XLenVT timm:$frm),
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
                   (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
                   (fvti.Mask V0), timm:$frm, GPR:$vl, ivti.Log2SEW,
                   TA_MA)>;
   }
 }
 
 multiclass VPatConvertI2FPVL_V<SDPatternOperator vop, string instruction_name> {
   foreach fvti = AllFloatVectors in {
-    defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+    defvar ivti = GetIntVTypeInfo(fvti);
     def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
                                 (ivti.Mask V0),
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
                   (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
                   (ivti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
   }
 }
 
 multiclass VPatConvertI2FP_RM_VL_V<SDNode vop, string instruction_name> {
   foreach fvti = AllFloatVectors in {
-    defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+    defvar ivti = GetIntVTypeInfo(fvti);
     def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
                                 (ivti.Mask V0), (XLenVT timm:$frm),
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
                   (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
                   (ivti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;
   }
 }
 
 // Widening converting
 
 multiclass VPatWConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> {
   foreach fvtiToFWti = AllWidenableFloatVectors in {
     defvar fvti = fvtiToFWti.Vti;
-    defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+    defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
     def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
                                 (fvti.Mask V0),
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
                   (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
                   (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
   }
 }
 
 multiclass VPatWConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> {
   foreach fvtiToFWti = AllWidenableFloatVectors in {
     defvar fvti = fvtiToFWti.Vti;
-    defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+    defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
     def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
                                 (fvti.Mask V0), (XLenVT timm:$frm),
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
                   (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
                   (fvti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;
   }
 }
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
                   (fwti.Mask V0), timm:$frm, GPR:$vl, vti.Log2SEW, TA_MA)>;
   }
 }
 
 multiclass VPatNConvertI2FPVL_W<SDPatternOperator vop,
                                 string instruction_name> {
   foreach fvtiToFWti = AllWidenableFloatVectors in {
     defvar fvti = fvtiToFWti.Vti;
-    defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+    defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
     def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
                                 (iwti.Mask V0),
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
                   (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1,
                   (iwti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
   }
 }
 
 multiclass VPatNConvertI2FP_RM_VL_W<SDNode vop, string instruction_name> {
   foreach fvtiToFWti = AllWidenableFloatVectors in {
     defvar fvti = fvtiToFWti.Vti;
-    defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+    defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
     def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
                                 (iwti.Mask V0),  (XLenVT timm:$frm),
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
                   (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1,
                   (iwti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;
   }
 }
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2,
                  vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm,
                  (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
 
   // emul = lmul * 16 / sew
   defvar vlmul = vti.LMul;
   defvar octuple_lmul = vlmul.octuple;
   defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW);
   if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
-    defvar emul_str = octuple_to_str<octuple_emul>.ret;
+    defvar emul_str = octuple_to_str(octuple_emul);
     defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
     defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
 
     def : Pat<(vti.Vector
                (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,
                                          (ivti.Vector ivti.RegClass:$rs1),
                                          vti.RegClass:$merge,
                                          (vti.Mask V0),
def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
             (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
                 vti.RegClass:$merge, GPR:$imm, GPR:$vl, vti.Log2SEW)>;
   def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
                                            vti.ScalarRegClass:$rs1,
                                            VLOpFrag)),
             (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX)
                 vti.RegClass:$merge,
                 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
-  defvar ivti = GetIntVTypeInfo<vti>.Vti;
+  defvar ivti = GetIntVTypeInfo(vti);
 
   def : Pat<(vti.Vector
              (riscv_vrgather_vv_vl vti.RegClass:$rs2,
                                    (ivti.Vector vti.RegClass:$rs1),
                                    vti.RegClass:$merge,
                                    (vti.Mask V0),
                                    VLOpFrag)),
             (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK")
def : Pat<(vti.Vector
             (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK")
                  vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm,
                  (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
 
   defvar vlmul = vti.LMul;
   defvar octuple_lmul = vlmul.octuple;
   defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW);
   if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
-    defvar emul_str = octuple_to_str<octuple_emul>.ret;
+    defvar emul_str = octuple_to_str(octuple_emul);
     defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
     defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
 
     def : Pat<(vti.Vector
                (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,
                                          (ivti.Vector ivti.RegClass:$rs1),
                                          vti.RegClass:$merge,
                                          (vti.Mask V0),

llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

class VCIXType<bits<4> val> {
   bits<4> Val = val;
 }
 
 def VCIX_X   : VCIXType<0b0000>;
 def VCIX_XV  : VCIXType<0b0010>;
 def VCIX_XVV : VCIXType<0b1010>;
 def VCIX_XVW : VCIXType<0b1111>;
 
-class SwapVCIXIns<dag funct6, dag rd, dag rs2, dag rs1, bit swap> {
-  dag Ins = !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1);
+function SwapVCIXIns(dag funct6, dag rd, dag rs2, dag rs1, bit swap): dag {
+  return !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1);
 }
 
 class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
                       string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
class VCIXInfo<string suffix, VCIXType type, DAGOperand TyRd,
   bits<4> Funct6_hi4 = type.Val;
   bits<3> Funct3 = !cond(!eq(TyRs1, VR):    0b000,
                          !eq(TyRs1, GPR):   0b100,
                          !eq(TyRs1, FPR32): 0b101,
                          !eq(TyRs1, simm5): 0b011);
   dag Outs = !if(!not(HaveOutputDst), (outs),
                  !if(!or(!eq(type, VCIX_XVV), !eq(type, VCIX_XVW)),
                      (outs TyRd:$rd_wb), (outs TyRd:$rd)));
-  dag Ins = SwapVCIXIns<!if(!ne(TyRs1, FPR32), (ins uimm2:$funct6_lo2),
+  dag Ins = SwapVCIXIns(!if(!ne(TyRs1, FPR32), (ins uimm2:$funct6_lo2),
                                                (ins uimm1:$funct6_lo1)),
                         !if(!and(HaveOutputDst, !or(!eq(type, VCIX_X),
                                                     !eq(type, VCIX_XV))),
                             (ins), (ins TyRd:$rd)),
                         (ins TyRs2:$rs2),
                         (ins TyRs1:$rs1),
-                        !if(!eq(type, VCIX_X), 1, 0)>.Ins;
+                        !if(!eq(type, VCIX_X), 1, 0));
   string Prototype = !if(!eq(type, VCIX_X), "$funct6_lo2, $rs2, $rd, $rs1",
                          !if(!ne(TyRs1, FPR32), "$funct6_lo2, $rd, $rs2, $rs1",
                                                 "$funct6_lo1, $rd, $rs2, $rs1"));
   string Constraints = !if(!not(HaveOutputDst), "",
                            !if(!or(!eq(type, VCIX_XVV),
                                    !eq(type, VCIX_XVW)), "$rd = $rd_wb", ""));
   RISCVVConstraint RVVConstraint = !if(!or(!not(HaveOutputDst),
                                            !ne(type, VCIX_XVW)), NoConstraint,

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 
 //===----------------------------------------------------------------------===//
 // Utility classes for segment load/store.
 //===----------------------------------------------------------------------===//
 // The set of legal NF for LMUL = lmul.
 // LMUL == 1, NF = 2, 3, 4, 5, 6, 7, 8
 // LMUL == 2, NF = 2, 3, 4
 // LMUL == 4, NF = 2
-class NFList<int lmul> {
-  list<int> L = !cond(!eq(lmul, 1): [2, 3, 4, 5, 6, 7, 8],
-                      !eq(lmul, 2): [2, 3, 4],
-                      !eq(lmul, 4): [2],
-                      !eq(lmul, 8): []);
+function NFList(int lmul): list<int> {
+  return !cond(!eq(lmul, 1): [2, 3, 4, 5, 6, 7, 8],
 }
 
 // Generate [start, end) SubRegIndex list.
-class SubRegSet<int nf, int lmul> {
-  list<SubRegIndex> L = !foldl([]<SubRegIndex>,
-                               [0, 1, 2, 3, 4, 5, 6, 7],
-                               AccList, i,
-                               !listconcat(AccList,
-                                 !if(!lt(i, nf),
-                                   [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)],
-                                   [])));
+function SubRegSet(int nf, int lmul): list<SubRegIndex> {
+  return !foldl([]<SubRegIndex>,
 }
 
 // Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX.
 // When NF = 2, the valid TUPLE_INDEX is 0 and 1.
 // For example, when LMUL = 4, the potential valid indexes is
 // [8, 12, 16, 20, 24, 28, 4]. However, not all these indexes are valid under
 // NF = 2. For example, 28 is not valid under LMUL = 4, NF = 2 and TUPLE_INDEX = 0.
 // The filter is
 //   (tuple_index + i) x lmul <= (tuple_index x lmul) + 32 - (nf x lmul)
 //
 // Use START = 0, LMUL = 4 and NF = 2 as the example,
 //   i x 4 <= 24
 // The class will return [8, 12, 16, 20, 24, 4].
 // Use START = 1, LMUL = 4 and NF = 2 as the example,
 //   (1 + i) x 4 <= 28
 // The class will return [12, 16, 20, 24, 28, 8].
 //
-class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> {
-  list<int> R =
+function IndexSet(int tuple_index, int nf, int lmul, bit isV0 = false): list<int> {
+  return
     !foldl([]<int>,
               !if(isV0, [0],
                 !cond(
                   !eq(lmul, 1):
                   [8, 9, 10, 11, 12, 13, 14, 15,
                    16, 17, 18, 19, 20, 21, 22, 23,
                    24, 25, 26, 27, 28, 29, 30, 31,
                    1, 2, 3, 4, 5, 6, 7],

 }
 
 // This class returns a list of vector register collections.
 // For example, for NF = 2 and LMUL = 4,
 // it will return
 //   ([ V8M4, V12M4, V16M4, V20M4, V24M4, V4M4],
 //    [V12M4, V16M4, V20M4, V24M4, V28M4, V8M4])
 //
-class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> {
-  list<dag> L =
+function VRegList(list<dag> LIn, int start, int nf, int lmul, bit isV0): list<dag> {
+  return
     !if(!ge(start, nf),
         LIn,
         !listconcat(
           [!dag(add,
-                !foreach(i, IndexSet<start, nf, lmul, isV0>.R,
+                !foreach(i, IndexSet(start, nf, lmul, isV0),
                   !cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2",
                                                   !eq(lmul, 4): "M4",
                                                   true: ""))),
                 !listsplat("",
-                  !size(IndexSet<start, nf, lmul, isV0>.R)))],
-          VRegList<LIn, !add(start, 1), nf, lmul, isV0>.L));
+                  !size(IndexSet(start, nf, lmul, isV0))))],
+          VRegList(LIn, !add(start, 1), nf, lmul, isV0)));
 }
 
 // Vector registers
 foreach Index = 0-31 in {
   def V#Index : RISCVReg<Index, "v"#Index>, DwarfRegNum<[!add(Index, 96)]>;
 }
 
 foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,

 
 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
                           (add VTYPE, VL, VLENB)> {
   let RegInfos = XLenRI;
 }
 
 
 foreach m = [1, 2, 4] in {
-  foreach n = NFList<m>.L in {
+  foreach n = NFList(m) in {
     def "VN" # n # "M" # m # "NoV0": RegisterTuples<
-                                       SubRegSet<n, m>.L,
-                                       VRegList<[], 0, n, m, false>.L>;
+                                       SubRegSet(n, m),
+                                       VRegList([], 0, n, m, false)>;
     def "VN" # n # "M" # m # "V0" : RegisterTuples<
-                                       SubRegSet<n, m>.L,
-                                       VRegList<[], 0, n, m, true>.L>;
+                                       SubRegSet(n, m),
+                                       VRegList([], 0, n, m, true)>;
   }
 }
 
 class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
   : RegisterClass<"RISCV",
                   regTypes,
                   64, // The maximum supported ELEN is 64.
                   regList> {

 )>;
 
 // The register class is added for inline assembly for vector mask types.
 def VM : VReg<VMaskVTs,
            (add (sequence "V%u", 8, 31),
                 (sequence "V%u", 0, 7)), 1>;
 
 foreach m = LMULList.m in {
-  foreach nf = NFList<m>.L in {
+  foreach nf = NFList(m) in {
     def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
                                (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
                                     !mul(nf, m)>;
     def "VRN" # nf # "M" # m: VReg<[untyped],
                                (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"),
                                     !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
                                     !mul(nf, m)>;
   }
 }
 
 // Special registers
 def FFLAGS : RISCVReg<0, "fflags">;
 def FRM    : RISCVReg<0, "frm">;

llvm/lib/Target/RISCV/RISCVScheduleV.td

 // Used for widening and narrowing instructions as it doesn't contain M8.
 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
 // Used for floating-point as it doesn't contain MF8.
 defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
 // Used for widening floating-point Reduction as it doesn't contain MF8.
 defvar SchedMxListFWRed = SchedMxListF;
 
-class SchedSEWSet<string mx> {
-  list<int> val = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
-                        !eq(mx, "M2"):  [8, 16, 32, 64],
-                        !eq(mx, "M4"):  [8, 16, 32, 64],
-                        !eq(mx, "M8"):  [8, 16, 32, 64],
-                        !eq(mx, "MF2"): [8, 16, 32],
-                        !eq(mx, "MF4"): [8, 16],
-                        !eq(mx, "MF8"): [8]);
+function SchedSEWSet(string mx): list<int> {
+  return !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
 }
 
 // For floating-point instructions, SEW won't be 8.
-class SchedSEWSetF<string mx> {
-  list<int> val = !cond(!eq(mx, "M1"):  [16, 32, 64],
-                        !eq(mx, "M2"):  [16, 32, 64],
-                        !eq(mx, "M4"):  [16, 32, 64],
-                        !eq(mx, "M8"):  [16, 32, 64],
-                        !eq(mx, "MF2"): [16, 32],
-                        !eq(mx, "MF4"): [16]);
+function SchedSEWSetF(string mx): list<int> {
+  return !cond(!eq(mx, "M1"):  [16, 32, 64],
 }
 
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
 // a record that represents the WorseCase behavior for name.
 multiclass LMULSchedWritesImpl<string name, list<string> MxList> {
   def name # "_WorstCase" : SchedWrite;

 
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
 // a record that represents the WorseCase behavior for name.
 multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0> {
   def name # "_WorstCase" : SchedWrite;
   foreach mx = MxList in {
-    foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
+    foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in
       def name # "_" # mx # "_E" # sew : SchedWrite;
   }
 }
 multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0> {
   def name # "_WorstCase" : SchedRead;
   foreach mx = MxList in {
-    foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
+    foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in
       def name # "_" # mx # "_E" # sew : SchedRead;
   }
 }
 multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
                                bit isF = 0> {
   def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
   foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
-    foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
+    foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in
       def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
   }
 }
 multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],
                                   bit isF = 0> {
   def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
   foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
-    foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
+    foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in
       def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
   }
 }
 // Define classes to define list containing all SchedWrites for each (name, LMUL)
 // pair for each LMUL in each of the SchedMxList variants above and name in
 // argument `names`. These classes can be used to construct a list of existing
 // definitions of writes corresponding to each (name, LMUL) pair, that are needed
 // by the ReadAdvance. For example: