[RISCV] Add an option to emit the Tag_RISCV_arch attribute based on the assembler's subtarget

[craig.topper]

Summary

This adds an option to emit the command line -mattr/-march into the
attributes of an object file. This can useful to get objdump to
disassemble instructions that aren't in the base without forcing
users to add a .attribute to the assembly file.

The binutils assembler does this by default.

Similar option exists for ARM. I will wire it to a clang option in
another patch. Similar to https://reviews.llvm.org/D31813

[kito-cheng]

LGTM, this would be very useful for assembly files, since I believe most developer won't write attribute when writing assembly code, and arch attribute is also kind of hard to write it correctly by human - and it even need to sync with build system (-march option for assembler)! so I believe auto generate that is right way to go.

[asb]

LGTM, modulo my comment about testing stack align attribute behaviour.

llvm/test/MC/RISCV/default-build-attributes.s

10

As I understand it, your intent is that the stack alignment attribute isn't emitted with -riscv-add-build-attributes (which I assume matches GNU behaviuor) This file should probably test for that.

[craig.topper]

Add -NOT checks for stack align

[asb]

LGTM, thanks.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/RISCVAttributes.h"
 #include "llvm/Support/RISCVISAInfo.h"
 
 #include <limits>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-asm-parser"
 
 STATISTIC(RISCVNumInstrsCompressed,
           "Number of RISC-V Compressed instructions emitted");
 
+static cl::opt<bool> AddBuildAttributes("riscv-add-build-attributes",
+                                        cl::init(false));
+
 namespace llvm {
 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
 } // namespace llvm
 
 namespace {
 struct RISCVOperand;
 
 struct ParserOptionsSet {
#undef GET_OPERAND_DIAGNOSTIC_TYPES
   };
 
   static bool classifySymbolRef(const MCExpr *Expr,
                                 RISCVMCExpr::VariantKind &Kind);
 
   RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
                  const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, STI, MII) {
+    MCAsmParserExtension::Initialize(Parser);
+
     Parser.addAliasForDirective(".half", ".2byte");
     Parser.addAliasForDirective(".hword", ".2byte");
     Parser.addAliasForDirective(".word", ".4byte");
     Parser.addAliasForDirective(".dword", ".8byte");
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
 
     auto ABIName = StringRef(Options.ABIName);
     if (ABIName.endswith("f") && !getSTI().hasFeature(RISCV::FeatureStdExtF)) {
RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
 
     // Use computeTargetABI to check if ABIName is valid. If invalid, output
     // error message.
     RISCVABI::computeTargetABI(STI.getTargetTriple(), STI.getFeatureBits(),
                                ABIName);
 
     const MCObjectFileInfo *MOFI = Parser.getContext().getObjectFileInfo();
     ParserOptions.IsPicEnabled = MOFI->isPositionIndependent();
+
+    if (AddBuildAttributes)
+      getTargetStreamer().emitTargetAttributes(STI, /*EmitStackAlign*/ false);
   }
 };
 
 /// RISCVOperand - Instances of this class represent a parsed machine
 /// instruction
 struct RISCVOperand final : public MCParsedAsmOperand {
 
   enum class KindTy {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h

public:
   virtual void emitDirectiveOptionNoRelax();
   virtual void emitDirectiveVariantCC(MCSymbol &Symbol);
   virtual void emitAttribute(unsigned Attribute, unsigned Value);
   virtual void finishAttributeSection();
   virtual void emitTextAttribute(unsigned Attribute, StringRef String);
   virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
                                     StringRef StringValue);
 
-  void emitTargetAttributes(const MCSubtargetInfo &STI);
+  void emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign);
   void setTargetABI(RISCVABI::ABI ABI);
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
 };
 
 // This part is for ascii assembly output
 class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
   formatted_raw_ostream &OS;
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

 void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
                                                unsigned IntValue,
                                                StringRef StringValue) {}
 void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
   assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
   TargetABI = ABI;
 }
 
-void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
+void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
+                                               bool EmitStackAlign) {
   if (STI.hasFeature(RISCV::FeatureRVE))
     report_fatal_error("Codegen not yet implemented for RVE");
 
+  if (EmitStackAlign)
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
   auto ParseResult = RISCVFeatures::parseFeatureBits(
       STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
   if (!ParseResult) {
     report_fatal_error(ParseResult.takeError());
   } else {
     auto &ISAInfo = *ParseResult;
     emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

 }
 
 void RISCVAsmPrinter::emitAttributes() {
   RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
   // Use MCSubtargetInfo from TargetMachine. Individual functions may have
   // attributes that differ from other functions in the module and we have no
   // way to know which function is correct.
-  RTS.emitTargetAttributes(*TM.getMCSubtargetInfo());
+  RTS.emitTargetAttributes(*TM.getMCSubtargetInfo(), /*EmitStackAlign*/ true);
 }
 
 void RISCVAsmPrinter::emitFunctionEntryLabel() {
   const auto *RMFI = MF->getInfo<RISCVMachineFunctionInfo>();
   if (RMFI->isVectorCall()) {
     auto &RTS =
         static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
     RTS.emitDirectiveVariantCC(*CurrentFnSym);

llvm/test/MC/RISCV/attribute.s

 ## Test llvm-mc could handle .attribute correctly.
 
 # RUN: llvm-mc %s -triple=riscv32 -filetype=asm | FileCheck %s
 # RUN: llvm-mc %s -triple=riscv64 -filetype=asm | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv32 -filetype=asm -riscv-add-build-attributes \
+# RUN:   | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -filetype=asm -riscv-add-build-attributes \
+# RUN:   | FileCheck %s
 
 .attribute stack_align, 16
 # CHECK: attribute      4, 16
 
 .attribute arch, "rv32i2p1_m2p0_a2p1_c2p0"
 # CHECK: attribute      5, "rv32i2p1_m2p0_a2p1_c2p0"
 
 .attribute unaligned_access, 0

llvm/test/MC/RISCV/default-build-attributes.s

+# RUN: llvm-mc %s -triple=riscv32 -filetype=asm -riscv-add-build-attributes \
+# RUN:   | FileCheck %s --check-prefixes=RV32
+# RUN: llvm-mc %s -triple=riscv64 -filetype=asm -riscv-add-build-attributes \
+# RUN:   | FileCheck %s --check-prefixes=RV64
+# RUN: llvm-mc %s -triple=riscv32 -filetype=asm -riscv-add-build-attributes \
+# RUN:   -mattr=+m | FileCheck %s --check-prefixes=RV32M
+# RUN: llvm-mc %s -triple=riscv64 -filetype=asm -riscv-add-build-attributes \
+# RUN:   -mattr=+m | FileCheck %s --check-prefixes=RV64M
+
+# RV32-NOT: attribute 4
+# RV32: attribute 5, "rv32i2p1"
+
+# RV64-NOT: attribute 4
+# RV64: attribute 5, "rv64i2p1"
+
+# RV32M-NOT: attribute 4
+# RV32M: attribute 5, "rv32i2p1_m2p0"
+
+# RV64M-NOT: attribute 4
+# RV64M: attribute 5, "rv64i2p1_m2p0"