Clean come dead code

[XinWang10]

Summary

These codes deleted are dead code, we never go into it.

1. In AggressiveAntiDepBreaker.cpp, have assert AntiDepReg != 0.
2. IfConversion.cpp, Kind can only be one unique value, so isFalse && isRev can never be true.
3. DAGCombiner.cpp, at line 3675, we have considered the condition like

// fold (sub x, c) -> (add x, -c)
if (N1C) {
  return DAG.getNode(ISD::ADD, DL, VT, N0,
                     DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
}

4. ScheduleDAGSDNodes.cpp, we have Latency > 1 at line 663
5. MasmParser.cpp, code exists in a switch-case block which decided by the value FirstTokenKind, at line 1621, FirstTokenKind could only be one of AsmToken::Dollar, AsmToken::At and AsmToken::Identifier.

[skan]

llvm/lib/CodeGen/IfConversion.cpp

535

Should we add an assertion !(isFalse && isRev) here?

llvm/lib/MC/MCParser/MasmParser.cpp

1620

Assert FirstTokenKind != AsmToken::String?

[craig.topper]

llvm/lib/CodeGen/IfConversion.cpp

535

Does this mean DisableTriangleFR is also dead?

[XinWang10]

llvm/lib/CodeGen/IfConversion.cpp

535

No, DisableTriangleFR is a option specified by user. Perhaps we'd better just remove isFalse && isRev.

535

add an assertion !(isFalse && isRev), I think it doesn't make sense here, just add another dead code?

[skan]

llvm/lib/CodeGen/IfConversion.cpp

535

I believe assertion is ignored for dead code. But I agree with you, the assertion is useless here b/c the definitions of isRev and 'isFalse' are nearby。

[skan]

Update the summary? It's not formatted.

[XinWang10]

• update

llvm/lib/CodeGen/IfConversion.cpp

535

Does this mean DisableTriangleFR is also dead?

I get your point now, I try to search for it, seems it also die.

[XinWang10]

rebase

[XinWang10]

llvm/lib/MC/MCParser/MasmParser.cpp

1620

It's not necessary, FirstTokenKind should always be one of one of AsmToken::Dollar, AsmToken::At and AsmToken::Identifier and never be AsmToken::String. can refer to line 1580

[skan]

LGTM

[XinWang10]

rebase

[XinWang10]

rebase

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

if (!MI.isKill()) {
             AntiDepReg = 0;
             break;
           }
 
           if (AntiDepReg == 0) continue;
         }
 
         assert(AntiDepReg != 0);
-        if (AntiDepReg == 0) continue;
 
         // Determine AntiDepReg's register group.
         const unsigned GroupIndex = State->GetGroup(AntiDepReg);
         if (GroupIndex == 0) {
           LLVM_DEBUG(dbgs() << " (zero group)\n");
           continue;
         }
 

llvm/lib/CodeGen/IfConversion.cpp

 static cl::opt<bool> DisableSimpleF("disable-ifcvt-simple-false",
                                     cl::init(false), cl::Hidden);
 static cl::opt<bool> DisableTriangle("disable-ifcvt-triangle",
                                      cl::init(false), cl::Hidden);
 static cl::opt<bool> DisableTriangleR("disable-ifcvt-triangle-rev",
                                       cl::init(false), cl::Hidden);
 static cl::opt<bool> DisableTriangleF("disable-ifcvt-triangle-false",
                                       cl::init(false), cl::Hidden);
-static cl::opt<bool> DisableTriangleFR("disable-ifcvt-triangle-false-rev",
-                                       cl::init(false), cl::Hidden);
 static cl::opt<bool> DisableDiamond("disable-ifcvt-diamond",
                                     cl::init(false), cl::Hidden);
 static cl::opt<bool> DisableForkedDiamond("disable-ifcvt-forked-diamond",
                                         cl::init(false), cl::Hidden);
 static cl::opt<bool> IfCvtBranchFold("ifcvt-branch-fold",
                                      cl::init(true), cl::Hidden);
 
 STATISTIC(NumSimple,       "Number of simple if-conversions performed");
while (!Tokens.empty()) {
       case ICTriangleRev:
       case ICTriangleFalse:
       case ICTriangleFRev: {
         bool isFalse = Kind == ICTriangleFalse;
         bool isRev   = (Kind == ICTriangleRev || Kind == ICTriangleFRev);
         if (DisableTriangle && !isFalse && !isRev) break;
         if (DisableTriangleR && !isFalse && isRev) break;
         if (DisableTriangleF && isFalse && !isRev) break;
-        if (DisableTriangleFR && isFalse && isRev) break;
         LLVM_DEBUG(dbgs() << "Ifcvt (Triangle");
         if (isFalse)
           LLVM_DEBUG(dbgs() << " false");
         if (isRev)
           LLVM_DEBUG(dbgs() << " rev");
         LLVM_DEBUG(dbgs() << "): " << printMBBReference(*BBI.BB)
                           << " (T:" << BBI.TrueBB->getNumber()
                           << ",F:" << BBI.FalseBB->getNumber() << ") ");

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
           if (C->getAPIntValue() == (VT.getScalarSizeInBits() - 1))
             return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0);
     }
   }
 
   // If the relocation model supports it, consider symbol offsets.
   if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
     if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
-      // fold (sub Sym, c) -> Sym-c
-      if (N1C && GA->getOpcode() == ISD::GlobalAddress)
-        return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
-                                    GA->getOffset() -
-                                        (uint64_t)N1C->getSExtValue());
       // fold (sub Sym+c1, Sym+c2) -> c1-c2
       if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
         if (GA->getGlobal() == GB->getGlobal())
           return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
                                  DL, VT);
     }
 
   // sub X, (sextinreg Y i1) -> add X, (and Y 1)

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
   int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
   if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
       !BB->succ_empty()) {
     unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
     if (Register::isVirtualRegister(Reg))
       // This copy is a liveout value. It is likely coalesced, so reduce the
       // latency so not to penalize the def.
       // FIXME: need target specific adjustment here?
-      Latency = (Latency > 1) ? Latency - 1 : 1;
+      Latency = Latency - 1;
   }
   if (Latency >= 0)
     dep.setLatency(Latency);
 }
 
 void ScheduleDAGSDNodes::dumpNode(const SUnit &SU) const {
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
   dumpNodeName(SU);

llvm/lib/MC/MCParser/MasmParser.cpp

if (Identifier.equals_insensitive("@b") ||
       MCSymbol *Sym = getContext().getDirectionalLocalSymbol(0, Before);
       if (Before && Sym->isUndefined())
         return Error(FirstTokenLoc, "Expected @@ label before @B reference");
       Res = MCSymbolRefExpr::create(Sym, getContext());
       return false;
     }
     // Parse symbol variant.
     std::pair<StringRef, StringRef> Split;
     if (!MAI.useParensForSymbolVariant()) {
-      if (FirstTokenKind == AsmToken::String) {
-        if (Lexer.is(AsmToken::At)) {
-          Lex(); // eat @
-          SMLoc AtLoc = getLexer().getLoc();
-          StringRef VName;
-          if (parseIdentifier(VName))
-            return Error(AtLoc, "expected symbol variant after '@'");
-
-          Split = std::make_pair(Identifier, VName);
-        }
-      } else {
-        Split = Identifier.split('@');
-      }
     } else if (Lexer.is(AsmToken::LParen)) {
       Lex(); // eat '('.
       StringRef VName;
       parseIdentifier(VName);
       // eat ')'.
       if (parseToken(AsmToken::RParen,
                      "unexpected token in variant, expected ')'"))
         return true;