[VP] Change getVPForBaseOpcode to return std::optional

[luke]

Summary

In an upcoming patch we would like to check if a regular base opcode has a corresponding VP opcode, so this changes the signature to return std::nullopt instead of LLVM_UNREACHABLE.
Where we previously relied on it to be unreachable, we just manually assert has_value() instead.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

936–937

I think we're supposed to use operator* instead of value().

There were commits like this in December

[lldb] llvm::Optional::value() && => operator*/operator->
    
    std::optional::value() has undesired exception checking semantics and is
    unavailable in older Xcode (see _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS). The
    call sites block std::optional migration.

[luke]

Use has_value() instead of value()

[luke]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

936–937

Good shout. Hopefully we can still use has_value(), I've changed it to just manually assert it.

[craig.topper]

LGTM

[luke]

This is no longer needed without D148523

llvm/include/llvm/CodeGen/ISDOpcodes.h

 
 /// The operand position of the explicit vector length parameter.
 std::optional<unsigned> getVPExplicitVectorLengthIdx(unsigned Opcode);
 
 /// Translate this VP Opcode to its corresponding non-VP Opcode.
 std::optional<unsigned> getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept);
 
 /// Translate this non-VP Opcode to its corresponding VP Opcode.
-unsigned getVPForBaseOpcode(unsigned Opcode);
+std::optional<unsigned> getVPForBaseOpcode(unsigned Opcode);
 
 //===--------------------------------------------------------------------===//
 /// MemIndexedMode enum - This enum defines the load / store indexed
 /// addressing modes.
 ///
 /// UNINDEXED    "Normal" load / store. The effective address is already
 ///              computed and is available in the base pointer. The offset
 ///              operand is always undefined. In addition to producing a

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (auto VLenPos = ISD::getVPExplicitVectorLengthIdx(VPOpcode))
         return false;
     return true;
   }
 
   // Specialize based on number of operands.
   // TODO emit VP intrinsics where MaskOp/VectorLenOp != null
   // SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT) { return
   // DAG.getNode(Opcode, DL, VT); }
   SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) {
-    unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode);
-    assert(ISD::getVPMaskIdx(VPOpcode) == 1 &&
-           ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 2);
-    return DAG.getNode(VPOpcode, DL, VT,
+    auto VPOpcode = ISD::getVPForBaseOpcode(Opcode);
+    assert(VPOpcode.has_value() && ISD::getVPMaskIdx(*VPOpcode) == 1 &&
+           ISD::getVPExplicitVectorLengthIdx(*VPOpcode) == 2);
+    return DAG.getNode(*VPOpcode, DL, VT,
                        {Operand, RootMaskOp, RootVectorLenOp});
   }
 
   SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                   SDValue N2) {
-    unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode);
-    assert(ISD::getVPMaskIdx(VPOpcode) == 2 &&
-           ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 3);
-    return DAG.getNode(VPOpcode, DL, VT,
+    auto VPOpcode = ISD::getVPForBaseOpcode(Opcode);
+    assert(VPOpcode.has_value() && ISD::getVPMaskIdx(*VPOpcode) == 2 &&
+           ISD::getVPExplicitVectorLengthIdx(*VPOpcode) == 3);
+    return DAG.getNode(*VPOpcode, DL, VT,
                        {N1, N2, RootMaskOp, RootVectorLenOp});
   }
 
   SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                   SDValue N2, SDValue N3) {
-    unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode);
-    assert(ISD::getVPMaskIdx(VPOpcode) == 3 &&
-           ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 4);
-    return DAG.getNode(VPOpcode, DL, VT,
+    auto VPOpcode = ISD::getVPForBaseOpcode(Opcode);
+    assert(VPOpcode.has_value() && ISD::getVPMaskIdx(*VPOpcode) == 3 &&
+           ISD::getVPExplicitVectorLengthIdx(*VPOpcode) == 4);
+    return DAG.getNode(*VPOpcode, DL, VT,
                        {N1, N2, N3, RootMaskOp, RootVectorLenOp});
   }
 
   SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand,
                   SDNodeFlags Flags) {
-    unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode);
-    assert(ISD::getVPMaskIdx(VPOpcode) == 1 &&
-           ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 2);
-    return DAG.getNode(VPOpcode, DL, VT, {Operand, RootMaskOp, RootVectorLenOp},
-                       Flags);
+    auto VPOpcode = ISD::getVPForBaseOpcode(Opcode);
+    assert(VPOpcode.has_value() && ISD::getVPMaskIdx(*VPOpcode) == 1 &&
+           ISD::getVPExplicitVectorLengthIdx(*VPOpcode) == 2);
+    return DAG.getNode(*VPOpcode, DL, VT,
+                       {Operand, RootMaskOp, RootVectorLenOp}, Flags);
   }
 
   SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                   SDValue N2, SDNodeFlags Flags) {
-    unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode);
-    assert(ISD::getVPMaskIdx(VPOpcode) == 2 &&
-           ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 3);
-    return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp},
+    auto VPOpcode = ISD::getVPForBaseOpcode(Opcode);
+    assert(VPOpcode.has_value() && ISD::getVPMaskIdx(*VPOpcode) == 2 &&
+           ISD::getVPExplicitVectorLengthIdx(*VPOpcode) == 3);
+    return DAG.getNode(*VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp},
                        Flags);
   }
 
   SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                   SDValue N2, SDValue N3, SDNodeFlags Flags) {
-    unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode);
-    assert(ISD::getVPMaskIdx(VPOpcode) == 3 &&
-           ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 4);
-    return DAG.getNode(VPOpcode, DL, VT,
+    auto VPOpcode = ISD::getVPForBaseOpcode(Opcode);
+    assert(VPOpcode.has_value() && ISD::getVPMaskIdx(*VPOpcode) == 3 &&
+           ISD::getVPExplicitVectorLengthIdx(*VPOpcode) == 4);
+    return DAG.getNode(*VPOpcode, DL, VT,
                        {N1, N2, N3, RootMaskOp, RootVectorLenOp}, Flags);
   }
 
   bool isOperationLegalOrCustom(unsigned Op, EVT VT,
                                 bool LegalOnly = false) const {
-    unsigned VPOp = ISD::getVPForBaseOpcode(Op);
-    return TLI.isOperationLegalOrCustom(VPOp, VT, LegalOnly);
+    auto VPOp = ISD::getVPForBaseOpcode(Op);
+    assert(VPOp.has_value());
+    return TLI.isOperationLegalOrCustom(*VPOp, VT, LegalOnly);
   }
 };
 
 } // end anonymous namespace
 
 //===----------------------------------------------------------------------===//
 //  TargetLowering::DAGCombinerInfo implementation
 //===----------------------------------------------------------------------===//

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 #define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) case ISD::VPOPC:
 #define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) return ISD::SDOPC;
 #define END_REGISTER_VP_SDNODE(VPOPC) break;
 #include "llvm/IR/VPIntrinsics.def"
   }
   return std::nullopt;
 }
 
-unsigned ISD::getVPForBaseOpcode(unsigned Opcode) {
+std::optional<unsigned> ISD::getVPForBaseOpcode(unsigned Opcode) {
   switch (Opcode) {
   default:
-    llvm_unreachable("can not translate this Opcode to VP.");
+    return std::nullopt;
 #define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) break;
 #define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) case ISD::SDOPC:
 #define END_REGISTER_VP_SDNODE(VPOPC) return ISD::VPOPC;
 #include "llvm/IR/VPIntrinsics.def"
   }
 }
 
 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) {