[11/11][POC][Clang][RISCV] Define vset for tuple type

[eopXD]

Summary

For the cover letter of this patch-set, please checkout D146872.

Depends on D147916.

This is the 11th patch of the patch-set.

This patch is a proof-of-concept and will be extended to full coverage
in the future. Only vset for tuple type of NF=2, EEW=32, LMUL=1 is
defined now.

[craig.topper]

clang/include/clang/Basic/riscv_vector.td

2763

Does SemaChecking already guarantee this?

[eopXD]

Add test case for out-of-range access and guard vset correctly under SemaChecking.cpp.

[eopXD]

Rebase and resolve CI failure.

[craig.topper]

clang/include/clang/Basic/riscv_vector.td

2759

Drop this assert

2763

Does this min do anything?

I didn't think about it in the previous patch, but if you're trying to clip it should be std::min(Index, MaxIndex-1)

[eopXD]

Address comments from Craig.

[craig.topper]

LGTM

[eopXD]

Rebase.

[eopXD]

Add unsigned cast to eliminate compile warning.

clang/include/clang/Basic/riscv_vector.td

foreach nf = [2] in {
       defvar T = "(Tuple:" # nf # ")";
       def : RVVBuiltin<T # "vv", "v" # T # "vKz", "i", "v">;
     }
   }
 
   let Name = "vset_v", Log2LMUL = [0, 1, 2], MaskedPolicyScheme = NonePolicy,
       ManualCodegen = [{
       {
+        if (isa<StructType>(ResultType)) { // codegen for tuple type
+          llvm::Value *VTupleOperand = Ops[0];
+          llvm::Value *IndexOperand = Ops[1];
+          llvm::Value *VOperand = Ops[2];
+          assert(isa<ConstantInt>(IndexOperand));
+
+          unsigned Index = cast<ConstantInt>(IndexOperand)->getZExtValue();
+          unsigned MaxIndex = cast<StructType>(VTupleOperand->getType())->getNumElements();
+          Index = std::min(Index, MaxIndex);
+
+          return Builder.CreateInsertValue(VTupleOperand, VOperand, {Index});
+        }
         ID = Intrinsic::vector_insert;
         IntrinsicTypes = {ResultType, Ops[2]->getType()};
         auto *ResVecTy = cast<ScalableVectorType>(ResultType);
         auto *VecTy = cast<ScalableVectorType>(Ops[2]->getType());
         // Mask to only valid indices.
         unsigned MaxIndex = ResVecTy->getMinNumElements() / VecTy->getMinNumElements();
         assert(isPowerOf2_32(MaxIndex));
         Ops[1] = Builder.CreateZExt(Ops[1], Builder.getInt64Ty());
         Ops[1] = Builder.CreateAnd(Ops[1], MaxIndex - 1);
         Ops[1] = Builder.CreateMul(Ops[1],
                                    ConstantInt::get(Ops[1]->getType(),
                                                     VecTy->getMinNumElements()));
         std::swap(Ops[1], Ops[2]);
         return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
       }
       }] in {
     foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
       def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">;
       def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
     }
+    foreach nf = [2] in {
+      defvar T = "(Tuple:" # nf # ")";
+      def : RVVBuiltin<T # "vv", T # "v" # T # "vKzv", "i", "v">;
+    }
   }
 }

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset_tuple.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x i32>, <vscale x 2 x i32> } @test_vget_v_i32m1x2_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[DEST_COERCE0:%.*]], <vscale x 2 x i32> [[DEST_COERCE1:%.*]], i64 noundef [[INDEX:%.*]], <vscale x 2 x i32> [[VAL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } undef, <vscale x 2 x i32> [[DEST_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], <vscale x 2 x i32> [[DEST_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], <vscale x 2 x i32> [[VAL]], 0
+// CHECK-RV64-NEXT:    ret { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP2]]
+//
+vint32m1x2_t test_vget_v_i32m1x2_i32m1(vint32m1x2_t dest, size_t index, vint32m1_t val) {
+  return __riscv_vset_v_i32m1x2_i32m1(dest, 0, val);
+}