[TwoAddressInstruction] Improve tests for register killed by instruction

[foad]

Summary

Define and use a MachineOperand overload of isPlainlyKilled. This
improves codegen in a couple of tests because it catches the case where
MO does not kill Reg but another operand of the same instruction does.

[foad]

llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll

13

This mov is removed.

37

This mov is removed.

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll

34

This mov is removed.

llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll

1193

This mov is removed.

1205

This mov is removed.

[arsenm]

LGTM. Seems like an error in the kill flag insertion

[foad]

In D147167#4234159, @arsenm wrote:

LGTM. Seems like an error in the kill flag insertion

You mean all uses of reg in one instruction should be marked as killed if any of them are? I did wonder about that but I bet it would require a lot of fixups elsewhere - and hopefully kill flags will go away instead.

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
 
 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, DEBUG_TYPE,
                 "Two-Address instruction pass", false, false)
 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
 INITIALIZE_PASS_END(TwoAddressInstructionPass, DEBUG_TYPE,
                 "Two-Address instruction pass", false, false)
 
-static bool isPlainlyKilled(MachineInstr *MI, Register Reg, LiveIntervals *LIS);
-
 /// Return the MachineInstr* if it is the single def of the Reg in current BB.
 static MachineInstr *getSingleDef(Register Reg, MachineBasicBlock *BB,
                                   const MachineRegisterInfo *MRI) {
   MachineInstr *Ret = nullptr;
   for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
     if (DefMI.getParent() != BB || DefMI.isDebugValue())
       continue;
     if (!Ret)
static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
 
   IsSrcPhys = SrcReg.isPhysical();
   IsDstPhys = DstReg.isPhysical();
   return true;
 }
 
 /// Test if the given register value, which is used by the
 /// given instruction, is killed by the given instruction.
-static bool isPlainlyKilled(MachineInstr *MI, Register Reg,
+static bool isPlainlyKilled(const MachineInstr *MI, Register Reg,
                             LiveIntervals *LIS) {
   if (LIS && Reg.isVirtual() && !LIS->isNotInMIMap(*MI)) {
     // FIXME: Sometimes tryInstructionTransform() will add instructions and
     // test whether they can be folded before keeping them. In this case it
     // sets a kill before recursively calling tryInstructionTransform() again.
     // If there is no interval available, we assume that this instruction is
     // one of those. A kill flag is manually inserted on the operand so the
     // check below will handle it.
     LiveInterval &LI = LIS->getInterval(Reg);
     // This is to match the kill flag version where undefs don't have kill
     // flags.
     if (!LI.hasAtLeastOneValue())
       return false;
 
     SlotIndex useIdx = LIS->getInstructionIndex(*MI);
     LiveInterval::const_iterator I = LI.find(useIdx);
     assert(I != LI.end() && "Reg must be live-in to use.");
     return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
   }
 
   return MI->killsRegister(Reg);
 }
 
+/// Test if the register used by the given operand is killed by the operand's
+/// instruction.
+static bool isPlainlyKilled(const MachineOperand &MO, LiveIntervals *LIS) {
+  return MO.isKill() || isPlainlyKilled(MO.getParent(), MO.getReg(), LIS);
+}
+
 /// Test if the given register value, which is used by the given
 /// instruction, is killed by the given instruction. This looks through
 /// coalescable copies to see if the original value is potentially not killed.
 ///
 /// For example, in this code:
 ///
 ///   %reg1034 = copy %reg1024
 ///   %reg1035 = copy killed %reg1025
if (!MO.isReg())
       continue;
     Register MOReg = MO.getReg();
     if (!MOReg)
       continue;
     if (MO.isDef())
       Defs.push_back(MOReg);
     else {
       Uses.push_back(MOReg);
-      if (MOReg != Reg && (MO.isKill() ||
-                           (LIS && isPlainlyKilled(MI, MOReg, LIS))))
+      if (MOReg != Reg && isPlainlyKilled(MO, LIS))
         Kills.push_back(MOReg);
     }
   }
 
   // Move the copies connected to MI down as well.
   MachineBasicBlock::iterator Begin = MI;
   MachineBasicBlock::iterator AfterMI = std::next(Begin);
   MachineBasicBlock::iterator End = AfterMI;
for (const MachineOperand &MO : OtherMI.operands()) {
         if (!MO.isDead() && regOverlapsSet(Defs, MOReg, TRI))
           // May clobber a physical register def.
           // FIXME: This may be too conservative. It's ok if the instruction
           // is sunken completely below the use.
           return false;
       } else {
         if (regOverlapsSet(Defs, MOReg, TRI))
           return false;
-        bool isKill =
-            MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS));
+        bool isKill = isPlainlyKilled(MO, LIS);
         if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) ||
                              regOverlapsSet(Kills, MOReg, TRI)))
           // Don't want to extend other live ranges and update kills.
           return false;
         if (MOReg == Reg && !isKill)
           // We can't schedule across a use of the register in question.
           return false;
         // Ensure that if this is register in question, its the kill we expect.
for (const MachineOperand &MO : KillMI->operands()) {
     if (!MO.isReg())
       continue;
     Register MOReg = MO.getReg();
     if (MO.isUse()) {
       if (!MOReg)
         continue;
       if (isDefTooClose(MOReg, DI->second, MI))
         return false;
-      bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
+      bool isKill = isPlainlyKilled(MO, LIS);
       if (MOReg == Reg && !isKill)
         return false;
       Uses.push_back(MOReg);
       if (isKill && MOReg != Reg)
         Kills.push_back(MOReg);
     } else if (MOReg.isPhysical()) {
       Defs.push_back(MOReg);
       if (!MO.isDead())
for (const MachineOperand &MO : OtherMI.operands()) {
       if (MO.isUse()) {
         if (regOverlapsSet(Defs, MOReg, TRI))
           // Moving KillMI can clobber the physical register if the def has
           // not been seen.
           return false;
         if (regOverlapsSet(Kills, MOReg, TRI))
           // Don't want to extend other live ranges and update kills.
           return false;
-        if (&OtherMI != MI && MOReg == Reg &&
-            !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))))
+        if (&OtherMI != MI && MOReg == Reg && !isPlainlyKilled(MO, LIS))
           // We can't schedule across a use of the register in question.
           return false;
       } else {
         OtherDefs.push_back(MOReg);
       }
     }
 
     for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {

llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mattr=+sve -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-linux-gnu"
 
 define <4 x i32> @test(ptr %arg1, ptr %arg2) {
 ; CHECK-LABEL: test:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov x8, #8
+; CHECK-NEXT:    mov x8, #8 // =0x8
 ; CHECK-NEXT:    ptrue p0.s, vl8
-; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
 ; CHECK-NEXT:    ld1w { z2.s }, p0/z, [x0]
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    add z2.s, z2.s, z2.s
-; CHECK-NEXT:    ext z0.b, z0.b, z1.b, #16
-; CHECK-NEXT:    add z1.s, z1.s, z1.s
+; CHECK-NEXT:    add z1.s, z0.s, z0.s
+; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #16
 ; CHECK-NEXT:    dup v0.4s, v0.s[2]
+; CHECK-NEXT:    add z2.s, z2.s, z2.s
 ; CHECK-NEXT:    st1w { z1.s }, p0, [x0, x8, lsl #2]
 ; CHECK-NEXT:    st1w { z2.s }, p0, [x0]
 ; CHECK-NEXT:    ret
 entry:
   %0 = load <16 x i32>, ptr %arg1, align 256
   %1 = load <16 x i32>, ptr %arg2, align 256
   %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <4 x i32> <i32 14, i32 14, i32 14, i32 14>
   %2 = add <16 x i32> %0, %0
   store <16 x i32> %2, ptr %arg1, align 256
   ret <4 x i32> %shvec
 }
 
 define <2 x i32> @test2(ptr %arg1, ptr %arg2) {
 ; CHECK-LABEL: test2:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov x8, #8
+; CHECK-NEXT:    mov x8, #8 // =0x8
 ; CHECK-NEXT:    ptrue p0.s, vl8
-; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
 ; CHECK-NEXT:    ld1w { z2.s }, p0/z, [x0]
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    add z2.s, z2.s, z2.s
-; CHECK-NEXT:    ext z0.b, z0.b, z1.b, #24
-; CHECK-NEXT:    add z1.s, z1.s, z1.s
+; CHECK-NEXT:    add z1.s, z0.s, z0.s
+; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #24
 ; CHECK-NEXT:    dup v0.2s, v0.s[0]
+; CHECK-NEXT:    add z2.s, z2.s, z2.s
 ; CHECK-NEXT:    st1w { z1.s }, p0, [x0, x8, lsl #2]
 ; CHECK-NEXT:    st1w { z2.s }, p0, [x0]
 ; CHECK-NEXT:    ret
 entry:
   %0 = load <16 x i32>, ptr %arg1, align 256
   %1 = load <16 x i32>, ptr %arg2, align 256
   %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <2 x i32> <i32 14, i32 14>
   %2 = add <16 x i32> %0, %0
   store <16 x i32> %2, ptr %arg1, align 256
   ret <2 x i32> %shvec
 }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll

entry:
   %2 = add <16 x i32> %0, %0
   store <16 x i32> %2, ptr %arg1, align 256
   ret <4 x i32> %shvec
 }
 
 define <2 x i32> @test2(ptr %arg1, ptr %arg2) {
 ; CHECK-LABEL: test2:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldp q2, q0, [x0, #32]
-; CHECK-NEXT:    ldp q4, q5, [x0]
-; CHECK-NEXT:    mov z1.d, z0.d
-; CHECK-NEXT:    add z3.s, z0.s, z0.s
-; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #8
-; CHECK-NEXT:    mov z0.s, s1
-; CHECK-NEXT:    add z1.s, z2.s, z2.s
-; CHECK-NEXT:    stp q1, q3, [x0, #32]
-; CHECK-NEXT:    add z1.s, z4.s, z4.s
+; CHECK-NEXT:    ldp q1, q0, [x0, #32]
+; CHECK-NEXT:    add z1.s, z1.s, z1.s
+; CHECK-NEXT:    ldp q2, q3, [x0]
+; CHECK-NEXT:    add z4.s, z0.s, z0.s
+; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
+; CHECK-NEXT:    mov z0.s, s0
+; CHECK-NEXT:    stp q1, q4, [x0, #32]
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    add z2.s, z5.s, z5.s
+; CHECK-NEXT:    add z1.s, z2.s, z2.s
+; CHECK-NEXT:    add z2.s, z3.s, z3.s
 ; CHECK-NEXT:    stp q1, q2, [x0]
 ; CHECK-NEXT:    ret
 entry:
   %0 = load <16 x i32>, ptr %arg1, align 256
   %1 = load <16 x i32>, ptr %arg2, align 256
   %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <2 x i32> <i32 14, i32 14>
   %2 = add <16 x i32> %0, %0
   store <16 x i32> %2, ptr %arg1, align 256
   ret <2 x i32> %shvec
 }

llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll

 ; SDAG-CI-NEXT:    v_cvt_f32_f16_e64 v0, v0 clamp
 ; SDAG-CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SDAG-CI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GISEL-GFX900-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
 ; GISEL-GFX900:       ; %bb.0:
 ; GISEL-GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GISEL-GFX900-NEXT:    v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX900-NEXT:    v_mov_b32_e32 v4, v3
-; GISEL-GFX900-NEXT:    v_mad_mixhi_f16 v4, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX900-NEXT:    v_max_f16_e64 v0, v3, v3 clamp
-; GISEL-GFX900-NEXT:    v_bfe_u32 v0, v0, 0, 16
+; GISEL-GFX900-NEXT:    v_max_f16_e64 v4, v3, v3 clamp
+; GISEL-GFX900-NEXT:    v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX900-NEXT:    v_bfe_u32 v0, v4, 0, 16
 ; GISEL-GFX900-NEXT:    v_mov_b32_e32 v1, 0xffff0000
-; GISEL-GFX900-NEXT:    v_and_or_b32 v0, v4, v1, v0
+; GISEL-GFX900-NEXT:    v_and_or_b32 v0, v3, v1, v0
 ; GISEL-GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GISEL-GFX906-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
 ; GISEL-GFX906:       ; %bb.0:
 ; GISEL-GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GISEL-GFX906-NEXT:    v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX906-NEXT:    v_mov_b32_e32 v4, v3
-; GISEL-GFX906-NEXT:    v_fma_mixhi_f16 v4, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX906-NEXT:    v_max_f16_e64 v0, v3, v3 clamp
-; GISEL-GFX906-NEXT:    v_bfe_u32 v0, v0, 0, 16
+; GISEL-GFX906-NEXT:    v_max_f16_e64 v4, v3, v3 clamp
+; GISEL-GFX906-NEXT:    v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX906-NEXT:    v_bfe_u32 v0, v4, 0, 16
 ; GISEL-GFX906-NEXT:    v_mov_b32_e32 v1, 0xffff0000
-; GISEL-GFX906-NEXT:    v_and_or_b32 v0, v4, v1, v0
+; GISEL-GFX906-NEXT:    v_and_or_b32 v0, v3, v1, v0
 ; GISEL-GFX906-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GISEL-VI-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GISEL-VI-NEXT:    v_cvt_f32_f16_e32 v3, v0
 ; GISEL-VI-NEXT:    v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
 ; GISEL-VI-NEXT:    v_cvt_f32_f16_e32 v4, v1

llvm/test/CodeGen/AVR/shift32.ll

 define i32 @ashr_i32_22(i32 %a) {
 ; CHECK-LABEL: ashr_i32_22:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    lsl r24
 ; CHECK-NEXT:    rol r25
 ; CHECK-NEXT:    sbc r18, r18
 ; CHECK-NEXT:    lsl r24
 ; CHECK-NEXT:    rol r25
+; CHECK-NEXT:    mov r19, r18
 ; CHECK-NEXT:    mov r23, r18
 ; CHECK-NEXT:    rol r23
 ; CHECK-NEXT:    mov r22, r25
-; CHECK-NEXT:    mov r19, r18
 ; CHECK-NEXT:    movw r24, r18
 ; CHECK-NEXT:    ret
   %res = ashr i32 %a, 22
   ret i32 %res
 }
 
 define i32 @ashr_i32_23(i32 %a) {
 ; CHECK-LABEL: ashr_i32_23:

llvm/test/CodeGen/X86/pr32284.ll

 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    pushl %ebp
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %ebp, -8
 ; X86-NEXT:    movl %esp, %ebp
 ; X86-NEXT:    .cfi_def_cfa_register %ebp
 ; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
-; X86-NEXT:    movl var_13, %ecx
-; X86-NEXT:    xorl %eax, %eax
-; X86-NEXT:    testl %ecx, %ecx
-; X86-NEXT:    notl %ecx
-; X86-NEXT:    sete %al
+; X86-NEXT:    movl var_13, %eax
+; X86-NEXT:    xorl %ecx, %ecx
+; X86-NEXT:    testl %eax, %eax
+; X86-NEXT:    notl %eax
+; X86-NEXT:    sete %cl
 ; X86-NEXT:    movl var_16, %edx
-; X86-NEXT:    xorl %ecx, %edx
-; X86-NEXT:    andl %eax, %edx
-; X86-NEXT:    orl %ecx, %edx
+; X86-NEXT:    xorl %eax, %edx
+; X86-NEXT:    andl %ecx, %edx
+; X86-NEXT:    orl %eax, %edx
 ; X86-NEXT:    movl %edx, (%esp)
 ; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
-; X86-NEXT:    movl %ecx, var_46
+; X86-NEXT:    movl %eax, var_46
 ; X86-NEXT:    movl %ebp, %esp
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    .cfi_def_cfa %esp, 4
 ; X86-NEXT:    retl
 entry:
   %a = alloca i64, align 8
   %0 = load i32, ptr @var_13, align 4
   %neg = xor i32 %0, -1