[NFC] Refine tests by adding `:` to checks

[Fznamznon]

Summary

The tests can fail if working directory where the tests were launched
has a error substring in its path.

[arsenm]

Won't this just move the failure to cases with "error:" in the name? Can these change to read from stdin, or add a regex for the filename?

[jhenderson]

LGTM, but best leave it a bit in case others have comments.

llvm/test/MC/Hexagon/multiple-pc4.s

1

Not related to your change, but does this line actually run FileCheck at all? I'm pretty sure it's missing a | character somewhere... Same goes with a few other tests you've modified.

(I am not familiar with these tests though, so my comment may be incorrect).

[jhenderson]

In D144562#4144469, @arsenm wrote:

Won't this just move the failure to cases with "error:" in the name?

It does, but there are many other tests that would run into that issue already. I suspect colons in file names are very rare...

[Fznamznon]

llvm/test/MC/Hexagon/multiple-pc4.s

1

I think it runs FileCheck. In this patch I modified only tests that were complaining about "error" substring in the path.
I think the magic is hidden in combination of "2>%t" in llvm-mc command and following "<%t" in FileCheck command.

[jhenderson]

llvm/test/MC/Hexagon/multiple-pc4.s

1

Ah, I compeltely misread that line, thanks! (The normal pattern is something like 2>&1 | FileCheck ... without the <%t at the end, so I read the 2>%t; bit as that!

[Joe_Nash]

I'm fine with the patch, but it's a shame the solution isn't more robust.
Its not self-evident why runline is written like that, so I expect uses without the ':' could creep back in.

[Fznamznon]

LGTM, but best leave it a bit in case others have comments.

It's been a week, is it ok if I submit this?

[Fznamznon]

I'm fine with the patch, but it's a shame the solution isn't more robust.

I'm open for any suggestions.

[foad]

LGTM.

llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s

-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
 
 v_ceil_f16_e32 v128, 0xfe0b
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_ceil_f16_e32 v255, v1
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_ceil_f16_e32 v5, v199

llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s

-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
 
 v_add_f16_e32 v255, v1, v2
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_fmaak_f16_e32 v255, v1, v2, 0xfe0b
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_fmac_f16_e32 v255, v1, v2

llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s

-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
 
 v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
 
 v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0, 0, 1, 0]
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand

llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s

-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
 
 v_cmp_class_f16_e32 vcc, v1, v255
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_cmp_class_f16_e32 vcc, v127, v255
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_cmp_class_f16_e32 vcc, vcc_hi, v255

llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s

-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
 
 v_cmpx_class_f16_e32 v1, v255
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_cmpx_eq_f16_e32 v1, v255
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_cmpx_eq_i16_e32 v1, v255

llvm/test/MC/ARM/thumb-branches.s

 @ RUN: not llvm-mc %s -triple thumbv7-linux-gnueabi -filetype=obj -o /dev/null 2>&1 | FileCheck %s
 @ RUN: not llvm-mc %s -triple thumbv8-m.baseline-none-eabi -filetype=obj -o /dev/null 2>&1 | FileCheck %s
 @ RUN: not llvm-mc %s -triple thumbv8-m.mainline-none-eabi -filetype=obj -o /dev/null 2>&1 | FileCheck %s
 @ RUN: not llvm-mc %s -triple thumbv6m-none-eabi -filetype=obj -o /dev/null 2>&1 | FileCheck %s
 @ RUN: not llvm-mc %s -triple thumbv5-linux-gnueabi -filetype=obj -o /dev/null 2>&1 | FileCheck -check-prefix=CHECKSHORT %s
 
 // Thumb BL has range +- 4 Megabytes if CPU does not support Thumb2 or does not
 // have v8-M baseline ops, it is +- 16 Megabytes otherwise.
 
         .code 16
         bl      shortend
         .space 0x3fffff
 shortend:
-// CHECKSHORT-NOT: error
+// CHECKSHORT-NOT: error:
 // CHECKSHORT: [[@LINE+1]]:{{[0-9]}}: error: Relocation out of range
         bl      shortend2
         .space 0x400000
 shortend2:
 
 // CHECKSHORT: [[@LINE+1]]:{{[0-9]}}: error: Relocation out of range
         bl      end
         .space 0xffffff
 end:
         bl      end2
         .space 0xffffff
         .global end2
 end2:
 
         bl      end3
         .space 0x1000000
         .global end3
 end3:
 
-// CHECK-NOT: error
-// CHECKSHORT-NOT: error
+// CHECK-NOT: error:
+// CHECKSHORT-NOT: error:
 // CHECKSHORT: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
 // CHECK: [[@LINE+1]]:{{[0-9]}}: error: Relocation out of range
         bl      end4
         .space 0x1000000
 end4:
 
 shortstart1:
         .space 0x3ffffc
start2:
         .space 0xfffffc
         bl start2
 
         .global start3
 start3:
         .space 0xfffffd
         bl start3
 
-// CHECK-NOT: error
+// CHECK-NOT: error:
 start4:
         .space 0xfffffd
 // CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
 // CHECKSHORT: [[@LINE+1]]:{{[0-9]}}: error: Relocation out of range
         bl start4

llvm/test/MC/ARM/thumb2-branch-ranges.s

// branch to arm function uses relocation
         .space 0x1000000
         .global end3
         .type end3, %function
         .arm
 end3:   bx lr
         .thumb
 
 // branch to thumb function is resolved at assembly time
-// CHECK-NOT: error
+// CHECK-NOT: error:
 // CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
 // CHECK-LABEL: b.w end4
         b.w end4
         .space 0x1000000
         .thumb_func
 end4:
 
         beq.w end5
         .space 0xffffc
 end5:
 
 // conditional branch to arm function uses relocation
         beq.w end6
         .arm
         .type end6, %function
         .space 0x100000
 end6:   bx lr
         .thumb
 
 // conditional branch to thumb function resolved at assembly time
-// CHECK-NOT: error
+// CHECK-NOT: error:
 // CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
 // CHECK-LABEL: beq.w end7
         beq.w end7
         .space 0x100000
 end7:
 
 start:
         .space 0xfffffc
         b.w start
 
         .arm
         .global start2
         .type start2, %function
 start2:
         .space 0x1000000
         .thumb
 // branch to arm function uses relocation
         b.w start2
 
 start3:
         .space 0x1000000
 // branch to thumb function resolved at assembly time
-// CHECK-NOT: error
+// CHECK-NOT: error:
 // CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
 // CHECK-LABEL: b.w start3
         b.w start3
 
 start4:
         .space 0xffffc
         b.w start4
 
         .arm
         .global start5
         .type start5, %function
 start5:
         .space 0x100000
         .thumb
 // conditional branch to arm function uses relocation
         beq.w start5
 
 start6:
         .space 0x100000
 // branch to thumb function resolved at assembly time
-// CHECK-NOT: error
+// CHECK-NOT: error:
 // CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
 // CHECK-LABEL: beq.w start6
         beq.w start6
 
 start7:
 // branch to thumb function resolved at assembly time
 // CHECK: [[#@LINE+1]]:{{[0-9]}}: error: Relocation out of range
         b.w start8 - start7 + 0x1000000
 start8:

llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s

-# RUN: not llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj -o %t %s 2>&1 | FileCheck --implicit-check-not=error %s
+# RUN: not llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj -o %t %s 2>&1 | FileCheck --implicit-check-not=error: %s
 
 { v1 = v2; vshuff(v1,v3,r0) }
 # CHECK: error: register `V1' modified more than once
 
 { v4 = v3; vdeal(v6,v4,r0) }
 # CHECK: error: register `V4' modified more than once

llvm/test/MC/Hexagon/c4_newval.s

-# RUN: not llvm-mc -arch=hexagon %s 2>%t; FileCheck --implicit-check-not=error %s <%t
+# RUN: not llvm-mc -arch=hexagon %s 2>%t; FileCheck --implicit-check-not=error: %s <%t
 
 .Lfoo:
 { p3:0 = r0
   if (!p0.new) jump:t .Lfoo }
 
 # CHECK: error: register `P0' used with `.new' but not validly modified in the same packet
 
 { c4 = r0

llvm/test/MC/Hexagon/multiple-pc4.s

-# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck --implicit-check-not=error %s <%t
+# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck --implicit-check-not=error: %s <%t
 
 # Check that multiple changes to a predicate in a packet are caught.
 
   { p0 = cmp.eq (r0, r0); p3:0 = r0 }
 # CHECK: rror: register {{.+}} modified more than once
 
   { p0 = cmp.eq (r0, r0); c4 = r0 }
 # CHECK: rror: register {{.+}} modified more than once
 
   p3:0 = r9
 # CHECK-NOT: rror: register {{.+}} modified more than once
 
 # Multiple writes to the same predicate register are permitted:
 
   { p0 = cmp.eq (r0, r0); p0 = and(p1, p2) }
 # CHECK-NOT: rror: register {{.+}} modified more than once

llvm/test/MC/Hexagon/zreg-post-inc.s

-# RUN: not llvm-mc -arch=hexagon -filetype=obj -mhvx -mcpu=hexagonv66 %s 2> %t; FileCheck --implicit-check-not=error %s <%t
+# RUN: not llvm-mc -arch=hexagon -filetype=obj -mhvx -mcpu=hexagonv66 %s 2> %t; FileCheck --implicit-check-not=error: %s <%t
 
 {
   if (p0) memb(r14+#8)=r4.new
   if (p0) z=vmem(r4++#0)
 }
 
 # CHECK: error: Instruction does not have a valid new register producer

llvm/test/TableGen/GICombinerEmitter/defs-invalid.td

 // RUN: not llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
 // RUN:     -combiners=MyCombiner %s 2>&1 | \
-// RUN:     FileCheck -implicit-check-not=error %s
+// RUN:     FileCheck -implicit-check-not=error: %s
 
 include "llvm/Target/Target.td"
 include "llvm/Target/GlobalISel/Combine.td"
 
 def MyTargetISA : InstrInfo;
 def MyTarget : Target { let InstructionSet = MyTargetISA; }
 
 def dummy;

llvm/test/TableGen/GICombinerEmitter/match-invalid.td

 // RUN: not llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
 // RUN:     -combiners=MyCombiner %s 2>&1 | \
-// RUN:     FileCheck -implicit-check-not=error %s
+// RUN:     FileCheck -implicit-check-not=error: %s
 
 include "llvm/Target/Target.td"
 include "llvm/Target/GlobalISel/Combine.td"
 
 def MyTargetISA : InstrInfo;
 def MyTarget : Target { let InstructionSet = MyTargetISA; }
 
 def dummy;

llvm/test/tools/llvm-dwarfdump/X86/debug_tls_relocs.s

 # RUN: llvm-mc %s -filetype obj -triple x86_64-pc-linux -o %t.o
 # RUN: llvm-dwarfdump -v %t.o | FileCheck %s
 
-# CHECK-NOT: error
+# CHECK-NOT: error:
 # CHECK: DW_AT_location [DW_FORM_exprloc] (DW_OP_const8u 0x0, DW_OP_GNU_push_tls_address)
 # CHECK: DW_AT_location [DW_FORM_exprloc] (DW_OP_const4u 0x0, DW_OP_GNU_push_tls_address)
 
 .section .debug_str,"MS",@progbits,1
 .Linfo_string0:
  .asciz "X"
 
 .section .debug_abbrev,"",@progbits