[BOLT] RFC: support for in-place binary rewriting

[treapster]

Summary

This is a patch which adds support for binary rewriting described here.

These are all commits combined, while commit history with messages can be viewed on github. Since one of the goals of -rewrite feature is to reduce padding both in file and in address space, this patch is included here, but we can remove it if you want. Feedback and suggestions are welcome! If you like the patch in general, we'll start submitting individual changes for review.

UPD: discourse topic was taken down by antispam for mentioning @maksfb and @rafauler and will be unavailable for some time, so i'm copying description below.

The current BOLT implementation adds new optimized sections and program headers at the end of the binary, leaving old sections in-place. Such an approach significantly increases output binary size, and the output binary cannot be correctly handled by strip and objcopy tools. To address these issues, we developed an experimental -rewrite option to relocate all sections in the binary. It's intended to replace existing -use-old-text option which is rather limited. For simplicity -use-gnu-stack was also deprecated/removed but it can be fairly easily restored if we want to.

So, here are the main changes to BOLT logic when rewriting:

• Sections' outputData and outputSize are initialized with corresponding input fields by default
• All relocations are read, including those from data to data
• Relocations are additionally created for .plt, .got and .got.plt sections
• In the case of AArch64 we also create a map (symbol name -> got entry address) using relocations and values in .got. It helps to resolve GOT accesses
• We also disassemble each PLT entry for AArch64 and put instructions in a single basic block. We replace GOT references with symbol refs to then emit each PLT entry as a function.
• After optimization passes and emitting are done, we estimate the number of program headers and their size
• We place program header at default offset of 64 in the file. Then we assign addresses and offsets to allocatable sections starting from the beginning - that is, right after program headers. If some section is now bigger than it was in the input, it is no problem
• To assign addresses, we iterate over original loadable program headers and determine which sections they contained. We put the same sections in the same segments in the same order. One exception is .eh_frame_hdr, it always goes after .eh_frame, since we need to know .eh_frame address to properly generate .eh_frame_hdr.
• After assigning address to .eh_frame, we parse it to estimate the number of entries and reserve enough space for .eh_frame_hdr
• We also check if BOLT created any additional sections(like .text.injected or new .rodata) that match the flags of the segment we're currently populating and find a place for them according to segment flags. For RO/RW segments we put sections in the end, for executable we put everything after .text. But this logic can be easily changed or probably even regulated with an option.
• We put nobits sections at the end of the segment if any.
• Now RTDyld->finalizeWithMemoryManagerLocking() is called the same as before
• If we have runtime library, we simply put all its sections in 2 additional segments - RE, RW - according to their flags
• We handle more dynamic entries and update them properly
• Now that the allocatable part of the binary is determined, we iterate over the rest of the segments like DYNAMIC and GNU_EH_FRAME, look which sections they contain, and create output segments with corresponding sections but new offsets
• When emitting functions, we emit PLT for AArch64
• When it's time to write the program header, we walk over all created segments and write them to file.

With -rewrite, the resulting binary looks pretty much the same as the input but has functions reordered and optimized.
Without the rewrite option, the main approach is similar, but old sections and segments get old addresses assigned to them, PHDR is placed after original segments, and new segments are created for new sections.
Also, if we instrument but don't rewrite, we put everything in a single RWX segment the same way it was before. Whether we want to change it is up to discussion.

Notes:

• The main change to the mapping logic is that we iterate over segments, not sections, and decide which sections we'll put in them. It means that BOLT becomes more strict to the input, for example it no longer tolerates allocatable sections outside of binary address space. We had to change 15+ obj2yaml-generated tests to work around this. Technically we can ignore unmapped sections when not rewriting, but fixing the tests seems to be a better idea, because why would we accept invalid binaries?
• We analyze GOT and PLT with more scrutiny and expect to find a valid pointer or dynamic relocation for each .got.plt entry. We'll fail when we encounter references from PLT to null .got.plt entries which don't have relocations(unless referenced by PLT header).
• Instead of mapping code/data separately, we have a couple of functions which return properly sorted sections for a given input segment or by given flags(for new segments) which is neater than previous implementation. On the other hand, some other things such as .eh_frame handling or RewriteInstance::getOutputSections got a bit messier, and handling relocations for AArch64 is not very straightforward.
• Currently, PLT entries are only emitted as functions on AArch64, because X86 PLT has more variations than AArch64 and it's harder to come up with a nice matcher and patcher for instructions, especially in the context of unifying disassemblePLTSection{X86, AArch64}. But it would be great if done.
• We're really bad at producing yaml tests which can be turned into a valid binary, and often we strip important sections from it, which means a lot of tests fail if BOLT starts caring more about address space, relocations, .got and .dynamic entries. IMO making less broken tests is better than ignoring them in BOLT, even though it means longer YAML files. Here is a somewhat related discussion about obj2yaml: https://reviews.llvm.org/D144009.
• Speaking of stability, it was mainly tested on clang/lld/llvm-mc/bolt binaries on both platforms, compiled by clang and linked by both ld and lld. Mentioned binaries pass all tests after processing in both -rewrite and regular mode with standard options(-reorder-blocks, -{split,reorder}-functions, -split-eh and some others). Less rigorous tests were performed on redis and some other binaries which also worked fine after processing. That said, it's probable there are some gotchas we didn't handle, but the basic functionality seems to work well.

Looking forward for your feedback!

Revunov Denis,
Advanced Software Technology Lab, Huawei

[treapster]

clang-format

[treapster]

Returned code to put .text.cold after .text. Missed that part when refactoring.

[treapster]

Rebase

[treapster]

Hello @maksfb, @rafauler, did you have a chance to look into it?

[treapster]

Rebase + fix .got.plt handling i broke yesterday. Now tests should pass.

[rafauler]

Can you easily test this on SPEC CPU2017 for x86? I just tried this patch on BOLT optimizing perlbench, and perlbench fails with a runtime error. I'm not using the -rewrite flags, it is a regression in default BOLT.

[rafauler]

Hi @treapster, thanks for this set of patches! Interesting stuff. I hope you appreciate that this is not a trivial change, has modifications to parts of BOLT that are quite subtle and need some time to read/debug and make sure things make sense. So I still didn't have time to go through the entirety of these changes, but I would like to post some initial comments nevertheless so we can kick off this discussion sooner rather than later.

I would like to start by saying that my gut feeling, overall, is that I think it is risky to be raising BOLT's responsibilities like that as we might not be able to correctly link in some cases, e.g. when the linker needs to do anything more complicated than just patching a relocation. The cases I'm thinking about here are relocations that require linker intervention to generate extra code to handle things (e..g building PLT tables, GOT/TLS relocs and such), where it might require extra logic to reverse engineer what the linker already did and try to patch that. Note that, at a high level, we already have this burden on BOLT regarding code, since we relocate code and we need to update and be aware of any metadata that has code pointers. Under this option, we extend this burden to data as well, since we're relocating data sections. Except that, with code, when we have weird cases we don't fully understand, we can just skip this function (only when not using -use-old-text) or do some tricks to avoid touching this function, but if we're relocating an entire blob of data and the entirety of allocatable sections, we don't have the luxury of skipping weird cases. Note that you're essentially implementing something like a -r linker option, which allows the linker to relocate all sections in a second linking step, but without all the metadata that the linker has, which makes it challenging.

Now, that aside, it's probably fine to support it under an experimental option, except that right now the implementation seems broken even if we don't use -rewrite. So there's definitely work that still needs to be done here and I'm still trying to figure out what, since I just started using this patch and I'm trying to understand it better.

When emitting functions, we emit PLT for AArch64

This is the type of stuff that probably justifies invoking BOLT from the linker as an LTO step, instead of doing the opposite and bringing a bunch of linker logic inside BOLT. Imagine that maintaining that over the long term implies maintaining a linker inside BOLT and duplicating functionality from the linker.

bolt/include/bolt/Core/BinaryContext.h

347

nit: something more descriptive, such as SegmentAddressToOffsetMap or OutputSegmentAddressToOffsetMap

it can be confusing to read OutputMappings in the middle of a code inside RewriteInstance, because it can mean so many things..

715

nit: maybe LastInputAllocAddress

949

nit: maybe "isExtraSection"

bolt/include/bolt/Rewrite/RewriteInstance.h

295

nit: mapEHFrame

bolt/lib/Core/BinaryContext.cpp

52

note to self: part of https://reviews.llvm.org/D137620

bolt/lib/Rewrite/RewriteInstance.cpp

2042–2043

what's up with this symbol and its special treatment?

2507

Note: I have a failure here when processing section ".fini_array" with one of my internal binaries, not sure what's happening yet, still debugging.

3398

Don't store Twine in an l-value. See https://llvm.org/doxygen/classllvm_1_1Twine.html "A Twine is not intended for use directly and should not be stored, its implementation relies on the ability to store pointers to temporary stack objects which may be deallocated at the end of a statement. Twines should only be used accepted as const references in arguments, when an API wishes to accept possibly-concatenated strings."

6046

missing newline after this. recheck this patch because we've got a bunch of similar style issues

[treapster]

In D144560#4200843, @rafauler wrote:

Can you easily test this on SPEC CPU2017 for x86? I just tried this patch on BOLT optimizing perlbench, and perlbench fails with a runtime error. I'm not using the -rewrite flags, it is a regression in default BOLT.

Unfortunately we don't have this benchmark around, but i may try to replicate it with usual perl. Can you please share what compiler, linker and bolt options you used? Was it relocation mode? Or maybe it's possible to get the actual binary via email or something?

[treapster]

In D144560#4203548, @rafauler wrote:

I hope you appreciate that this is not a trivial change, has modifications to parts of BOLT that are quite subtle and need some time to read/debug and make sure things make sense.

Yeah absolutely, there's a lot of stuff here and a lot of work to be done to turn it from POC to the actual patchset. Thank you for initial feedback so that we can move in that direction!

I would like to start by saying that my gut feeling, overall, is that I think it is risky to be raising BOLT's responsibilities like that as we might not be able to correctly link in some cases, e.g. when the linker needs to do anything more complicated than just patching a relocation. The cases I'm thinking about here are relocations that require linker intervention to generate extra code to handle things (e..g building PLT tables, GOT/TLS relocs and such), where it might require extra logic to reverse engineer what the linker already did and try to patch that. Note that, at a high level, we already have this burden on BOLT regarding code, since we relocate code and we need to update and be aware of any metadata that has code pointers. Under this option, we extend this burden to data as well, since we're relocating data sections. Except that, with code, when we have weird cases we don't fully understand, we can just skip this function (only when not using -use-old-text) or do some tricks to avoid touching this function, but if we're relocating an entire blob of data and the entirety of allocatable sections, we don't have the luxury of skipping weird cases. Note that you're essentially implementing something like a -r linker option, which allows the linker to relocate all sections in a second linking step, but without all the metadata that the linker has, which makes it challenging.

Now, that aside, it's probably fine to support it under an experimental option, except that right now the implementation seems broken even if we don't use -rewrite. So there's definitely work that still needs to be done here and I'm still trying to figure out what, since I just started using this patch and I'm trying to understand it better.

When emitting functions, we emit PLT for AArch64

This is the type of stuff that probably justifies invoking BOLT from the linker as an LTO step, instead of doing the opposite and bringing a bunch of linker logic inside BOLT. Imagine that maintaining that over the long term implies maintaining a linker inside BOLT and duplicating functionality from the linker.

I agree that with this patch BOLT is getting even closer to being a linker and ultimately it's probably justified to use it as an LTO step, but at the same time, i wouldn't say that a lot of things changed here conceptually: the patch mostly uses existing BOLT infrastructure to create relocations and patch them during emission, we don't generate any .plt/.got from scratch as linker does, and we parsed .plt anyway - now we just additionaly relocate/re-emit it. Speaking of metadata, most of it is available to us via relocations, which may be relaxed or incorrect, but we already dealt with it before. IMO integrating BOLT with lld/LTO would be a lot more work, so i tried to extend existing functionality without changing the API too much. And such things as segment->sections mapping and address space awareness are useful even without -rewrite option because they make recreating PHDR cleaner and serve as a sanity check for the input binary. Even though a lot of things can go wrong when relocating all sections, i think practically it's possible make -rewrite stable enough to support the majority of binaries and fall back to usual mode in weird cases.

That said, there's still a ton of changes here to test, review and debug, starting from fixing non-rewrite regressions. Waiting for your feedback to reproduce them!

[treapster]

bolt/lib/Rewrite/RewriteInstance.cpp

2042–2043

Well, ideally we should detect when any symbol points to the end of section and relocate/update it accordingly. But since i haven't seen relocations against such symbols for anything but .init_array, i just special-cased it for now. I also tried to produce a binary which would use __fini_array_end symbol but failed with both ld and lld so i only handled the init case. If some of your binaries uses __fini_array_end or similar, it may be the cause of failures, i should've commented it :/. On the other hand, for non-rewrite it shouldn't be an issue, so maybe it's not the culprit here.

I'll put out a patch with proper past-end symbol handling this week.

[rafauler]

Testing status:
Our large internal binaries built with clang + lld are crashing.
SPEC CPU2017 built with norelocation mode doesn't crash. The one built with reloc mode does crash.

Somehow this patch is also changing the total number of functions reported by BOLT in some of our internal tests (decreasing it by 1)

For 600.perlbench, you may repro building it with gcc 11 toolchain (gcc + gnu as + gnu ld linker) for x86. I can't just give you a binary, because SPEC uses some test inputs to run the binary, and only then it crashes, so it is more complicated to repro. But your company very likely has license to use SPEC. It's a useful benchmark to have for testing compiler changes.

Maybe we can try to repro by building another application with GCC for x86.

[treapster]

I tried building perl with gcc 11.3.0 + binutils 2.38.50 toolchain, processing it and running tests on it, but didn't encounter any failures regardless of -rewrite.
I also used the same toolchain to build clang and in that case 18 clang tests failed, but after vanilla bolt there are 29 failing tests so it doesn't look like regression(all failed tests also fail on vanilla bolt).
I'll test more stuff with llvm toolchain and report back.
Regarding SPEC CPU, we don't have access to it right now.

[treapster]

bolt/lib/Rewrite/RewriteInstance.cpp

1353

I think this line causes NumRegularFunctions to decrease by 1, because PLT functions are skipped in PrintProgramStats::runOnFunctions, and PLT header didn't have PLT symbol before the patch. Looks like NFC.

[treapster]

Rebase + fix nits

[treapster]

Rebase, add end symbol handling + fix .text relocations creation

[treapster]

rebase

[treapster]

Hello, @rafauler, can you please test perlbench one more time with current version and provide more info on bolt/compiler options and SPEC config used? We tested a bit with perlbench but couldn't reproduce.

[treapster]

Perlbench does indeed segfault with --rewrite and i'll debug it, but without --rewrite and with --split-functions --split-all-cold --split-eh --reorder-blocks=ext-tsp it runs just fine, even instrumented.

[treapster]

Rebase + handle CALL64m relocations (fixes perlbench failure) + update dynamic relocations for end-of-section symbols.

With this version perlbench works after processing even if --rewrite is used. See github branch for commits.

[treapster]

Hello, @rafaelauler, can you please check whether failures you talked about still reproduce with current branch? I understand there's a lot going on with JITLink and RISC-V diffs, but would still appreciate your feedback.

[rafauler]

Thanks @treapster , can you try to rebase on top of current bolt now? I can't test it if the diff doesn't cleanly apply on top of what we have on trunk, and JITLink changed BOLT quite a bit.

[treapster]

@rafauler sorry for late response, i missed your message. Here is a rebase, and also there is a branch in case the diff fails to apply later. A couple of X86 tests fail because of wrong section indices in symtab, but otherwise it should be ok.

[treapster]

Fix some test failures, add got/plt handling for RISC-V
I tested RISC-V helloworld on qemu and it did fail after BOLT, but then i tried vanilla BOLT and it couldn't even process the binary, so the changes are probably fine.

[treapster]

Fix LongJMP issues by putting .plt before .text.
Compute text address in advance in non-rewrite case

[treapster]

Put stray zero-sized sections in the end of the last segment.
Previously they were assigned old address/offset, which potentially could put them out of address space and cause assertion failures.

[treapster]

Use last segment's offset+filesz as an offset for zero-sized stray sections

[treapster]

More workarounds for AArch64 + more compatibility with non-rewrite mode. Also bail out when --rewrite is passed but no relocs are present'

bolt/include/bolt/Core/BinaryContext.h

 class MCInstPrinter;
 
 using namespace object;
 
 namespace bolt {
 
 class BinaryFunction;
 
-/// Information on loadable part of the file.
-struct SegmentInfo {
-  uint64_t Address;           /// Address of the segment in memory.
-  uint64_t Size;              /// Size of the segment in memory.
-  uint64_t FileOffset;        /// Offset in the file.
-  uint64_t FileSize;          /// Size in file.
-  uint64_t Alignment;         /// Alignment of the segment.
-
+// We create a copy of ELF64LE::Phdr type because ELF64LE::Phdr uses
+// endian-aware members which use memcpy for assignments and other operations.
+// We will use this struct instead to avoid memcpy and convert to ELF64LE::Phdr
+// only before writing to file.
+struct ProgramHeader {
+  uint32_t p_type{0};
+  uint32_t p_flags{0};
+  uint64_t p_offset{0};
+  uint64_t p_vaddr{0};
+  uint64_t p_paddr{0};
+  uint64_t p_filesz{0};
+  uint64_t p_memsz{0};
+  uint64_t p_align{0};
+
+  ProgramHeader(const ELF64LE::Phdr &Hdr) {
+    p_type = Hdr.p_type;
+    p_flags = Hdr.p_flags;
+    p_offset = Hdr.p_offset;
+    p_vaddr = Hdr.p_vaddr;
+    p_paddr = Hdr.p_paddr;
+    p_filesz = Hdr.p_filesz;
+    p_memsz = Hdr.p_memsz;
+    p_align = Hdr.p_align;
+  }
+  ProgramHeader() {}
+
+  ProgramHeader(uint32_t p_type, uint32_t p_flags, uint64_t p_offset,
+                uint64_t p_vaddr, uint64_t p_paddr, uint64_t p_filesz,
+                uint64_t p_memsz, uint64_t p_align)
+      : p_type(p_type), p_flags(p_flags), p_offset(p_offset), p_vaddr(p_vaddr),
+        p_paddr(p_paddr), p_filesz(p_filesz), p_memsz(p_memsz),
+        p_align(p_align) {}
+  explicit operator ELF64LE::Phdr() const {
+    ELF64LE::Phdr Res;
+    Res.p_type = p_type;
+    Res.p_flags = p_flags;
+    Res.p_offset = p_offset;
+    Res.p_vaddr = p_vaddr;
+    Res.p_paddr = p_paddr;
+    Res.p_filesz = p_filesz;
+    Res.p_memsz = p_memsz;
+    Res.p_align = p_align;
+    return Res;
+  }
   void print(raw_ostream &OS) const {
-    OS << "SegmentInfo { Address: 0x"
-       << Twine::utohexstr(Address) << ", Size: 0x"
-       << Twine::utohexstr(Size) << ", FileOffset: 0x"
-       << Twine::utohexstr(FileOffset) << ", FileSize: 0x"
-       << Twine::utohexstr(FileSize) << ", Alignment: 0x"
-       << Twine::utohexstr(Alignment) << "}";
-  };
+    OS << "SegmentInfo { Address: 0x" << Twine::utohexstr(p_vaddr)
+       << ", Size: 0x" << Twine::utohexstr(p_memsz) << ", FileOffset: 0x"
+       << Twine::utohexstr(p_offset) << ", FileSize: 0x"
+       << Twine::utohexstr(p_filesz) << ", Alignment: 0x"
+       << Twine::utohexstr(p_align) << "}";
+  }
+  bool contains(const BinarySection &Section) const {
+    return (Section.getAddress() && Section.getInputFileOffset() &&
+            Section.getAddress() >= p_vaddr &&
+            (Section.getAddress() + !Section.isTBSS() * Section.getSize() <=
+             p_vaddr + p_memsz));
+  }
+
+  bool isTLS() const { return p_type == ELF::PT_TLS; }
+  bool isLOAD() const { return p_type == ELF::PT_LOAD; }
+  bool isExec() const { return p_flags & ELF::PF_X; }
+  // intended for loadable segments
+  unsigned getSectionFlags() const {
+    return ELF::SHF_ALLOC * (p_type == ELF::PT_LOAD) |
+           ELF::SHF_EXECINSTR * !!(p_flags & ELF::PF_X) |
+           ELF::SHF_WRITE * !!(p_flags & ELF::PF_W);
+  }
 };
 
-inline raw_ostream &operator<<(raw_ostream &OS, const SegmentInfo &SegInfo) {
+inline raw_ostream &operator<<(raw_ostream &OS, const ProgramHeader &SegInfo) {
   SegInfo.print(OS);
   return OS;
 }
 
 // AArch64-specific symbol markers used to delimit code/data in .text.
 enum class MarkerSymType : char {
   NONE = 0,
   CODE,
public:
   createBinaryContext(const ObjectFile *File, bool IsPIC,
                       std::unique_ptr<DWARFContext> DwCtx);
 
   /// Superset of compiler units that will contain overwritten code that needs
   /// new debug info. In a few cases, functions may end up not being
   /// overwritten, but it is okay to re-generate debug info for them.
   std::set<const DWARFUnit *> ProcessedCUs;
 
+  StringMap<BinarySection *> EndSymbols;
+
   // Setup MCPlus target builder
   void initializeTarget(std::unique_ptr<MCPlusBuilder> TargetBuilder) {
     MIB = std::move(TargetBuilder);
   }
 
   /// Return function fragments to skip.
   const std::unordered_set<BinaryFunction *> &getFragmentsToSkip() {
     return FragmentsToSkip;
public:
   }
 
   Expected<unsigned> getDwarfFile(StringRef Directory, StringRef FileName,
                                   unsigned FileNumber,
                                   std::optional<MD5::MD5Result> Checksum,
                                   std::optional<StringRef> Source,
                                   unsigned CUID, unsigned DWARFVersion);
 
-  /// [start memory address] -> [segment info] mapping.
-  std::map<uint64_t, SegmentInfo> SegmentMapInfo;
+  /// [start memory address] -> [program header] mapping for loadable input
+  /// segments
+  std::map<uint64_t, ProgramHeader> SegmentMapInfo;
+
+  // [address] -> [offset] mappings for output loadable segments
+  std::map<uint64_t, uint64_t> OutputAddressToOffsetMap;
+  std::vector<ProgramHeader> OutputSegments;
 
+  using SegmentIterator = decltype(OutputSegments)::iterator;
+  using FilteredSegmentIterator = FilterIterator<SegmentIterator>;
+
+  std::vector<ProgramHeader> InputSegments;
   /// Symbols that are expected to be undefined in MCContext during emission.
   std::unordered_set<MCSymbol *> UndefinedSymbols;
 
   /// [name] -> [BinaryData*] map used for global symbol resolution.
   using SymbolMapType = StringMap<BinaryData *>;
   SymbolMapType GlobalSymbols;
 
   /// [address] -> [BinaryData], ...
struct BinaryStats {
     uint64_t MissedMacroFusionExecCount{0};
 
     /// Stats for stale profile matching:
     ///   the total number of basic blocks in the profile
     uint32_t NumStaleBlocks{0};
     ///   the number of matched basic blocks
     uint32_t NumMatchedBlocks{0};
     ///   the total count of samples in the profile
     uint64_t StaleSampleCount{0};
     ///   the count of matched samples
     uint64_t MatchedSampleCount{0};
   } Stats;
 
   // Address of the first allocated segment.
   uint64_t FirstAllocAddress{std::numeric_limits<uint64_t>::max()};
 
-  /// Track next available address for new allocatable sections. RewriteInstance
-  /// sets this prior to running BOLT passes, so layout passes are aware of the
-  /// final addresses functions will have.
-  uint64_t LayoutStartAddress{0};
-
-  /// Old .text info.
+  // The end of the last loadable segment in the input
+  uint64_t InputAddressSpaceEnd{0};
   uint64_t OldTextSectionAddress{0};
-  uint64_t OldTextSectionOffset{0};
-  uint64_t OldTextSectionSize{0};
+  // Computed in advance when not using --rewrite, otherwise unused
+  uint64_t NewTextSectionAddress{0};
+  uint64_t MaxPHDRSize{0};
 
   /// Address of the code/function that is executed before any other code in
   /// the binary.
   std::optional<uint64_t> StartFunctionAddress;
 
   /// Address of the code/function that is going to be executed right before
   /// the execution of the binary is completed.
   std::optional<uint64_t> FiniFunctionAddress;
public:
   }
 
   bool isX86() const {
     return TheTriple->getArch() == llvm::Triple::x86 ||
            TheTriple->getArch() == llvm::Triple::x86_64;
   }
 
   bool isRISCV() const { return TheTriple->getArch() == llvm::Triple::riscv64; }
+  bool isRISC() const { return isRISCV() || isAArch64(); }
 
   // AArch64-specific functions to check if symbol is used to delimit
   // code/data in .text. Code is marked by $x, data by $d.
   MarkerSymType getMarkerType(const SymbolRef &Symbol) const;
   bool isMarker(const SymbolRef &Symbol) const;
 
   /// Iterate over all BinaryData.
   iterator_range<binary_data_const_iterator> getBinaryData() const {
getBinaryDataForSection(BinarySection &Section) {
     auto End = BinaryDataMap.upper_bound(Section.getEndAddress());
     auto pred = [&Section](const binary_data_iterator &Itr) -> bool {
       return Itr->second->getSection() == Section;
     };
     return make_range(FilteredBinaryDataIterator(pred, Begin, End),
                       FilteredBinaryDataIterator(pred, End, End));
   }
 
+  std::vector<BinarySection *> getNewSectionsByFlags(unsigned Flags,
+                                                     bool ROwithRX = false);
+
+  std::vector<BinarySection *> getAllNewSections() {
+
+    std::vector<BinarySection *> Result = getNewSectionsByFlags(
+        ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, /*ROwithRX*/ true);
+    std::vector<BinarySection *> RWSections =
+        getNewSectionsByFlags(ELF::SHF_ALLOC | ELF::SHF_WRITE);
+
+    Result.insert(Result.end(), RWSections.begin(), RWSections.end());
+
+    return Result;
+  }
   /// Iterate over all the sub-symbols of /p BD (if any).
   iterator_range<binary_data_iterator> getSubBinaryData(BinaryData *BD);
 
   /// Clear the global symbol address -> name(s) map.
   void clearBinaryData() {
     GlobalSymbols.clear();
     for (auto &Entry : BinaryDataMap)
       delete Entry.second;
const BinaryData *getPLTBinaryDataByName(StringRef Name) const {
     return nullptr;
   }
 
   /// Return true if \p SymbolName was generated internally and was not present
   /// in the input binary.
   bool isInternalSymbolName(const StringRef Name) {
     return Name.startswith("SYMBOLat") || Name.startswith("DATAat") ||
            Name.startswith("HOLEat");
   }
 
+  // true if a section wasn't present in the input binary
+  bool isExtra(BinarySection &Section) const {
+    return !Section.getInputFileOffset();
+  }
+
   MCSymbol *getHotTextStartSymbol() const {
     return Ctx->getOrCreateSymbol("__hot_start");
   }
 
   MCSymbol *getHotTextEndSymbol() const {
     return Ctx->getOrCreateSymbol("__hot_end");
   }
 
auto isAllocatable = [](const SectionIterator &Itr) {
       return *Itr && Itr->isAllocatable();
     };
     return make_range(
         FilteredSectionIterator(isAllocatable, Sections.begin(),
                                 Sections.end()),
         FilteredSectionIterator(isAllocatable, Sections.end(), Sections.end()));
   }
 
+  iterator_range<FilteredSegmentIterator> loadableSegments() {
+    auto IsLoad = [](const SegmentIterator &Phdr) { return Phdr->isLOAD(); };
+    return make_range(FilteredSegmentIterator(IsLoad, InputSegments.begin(),
+                                              InputSegments.end()),
+                      FilteredSegmentIterator(IsLoad, InputSegments.end(),
+                                              InputSegments.end()));
+  }
+
+  iterator_range<FilteredSegmentIterator> nonLoadableSegments() {
+    auto IsNotLoad = [](const SegmentIterator &Phdr) {
+      return !Phdr->isLOAD();
+    };
+    return make_range(FilteredSegmentIterator(IsNotLoad, InputSegments.begin(),
+                                              InputSegments.end()),
+                      FilteredSegmentIterator(IsNotLoad, InputSegments.end(),
+                                              InputSegments.end()));
+  }
+
   /// Iterate over all registered code sections.
   iterator_range<FilteredSectionIterator> textSections() {
     auto isText = [](const SectionIterator &Itr) {
       return *Itr && Itr->isAllocatable() && Itr->isText();
     };
     return make_range(
         FilteredSectionIterator(isText, Sections.begin(), Sections.end()),
         FilteredSectionIterator(isText, Sections.end(), Sections.end()));
public:
   /// mapping. Note that \p FileOffset should be page-aligned and could be
   /// different from the file offset of the segment which could be unaligned.
   /// If no segment is found that matches \p FileOffset, return std::nullopt.
   std::optional<uint64_t> getBaseAddressForMapping(uint64_t MMapAddress,
                                                    uint64_t FileOffset) const;
 
   /// Check if the address belongs to this binary's static allocation space.
   bool containsAddress(uint64_t Address) const {
-    return Address >= FirstAllocAddress && Address < LayoutStartAddress;
+    return Address >= FirstAllocAddress && Address < InputAddressSpaceEnd;
   }
 
   /// Return section name containing the given \p Address.
   ErrorOr<StringRef> getSectionNameForAddress(uint64_t Address) const;
 
   /// Print all sections.
   void printSections(raw_ostream &OS) const;
 

bolt/include/bolt/Core/BinaryFunction.h

public:
   bool hasExternalRefRelocations() const { return HasExternalRefRelocations; }
 
   /// Return true if the function has instruction(s) with unknown control flow.
   bool hasUnknownControlFlow() const { return HasUnknownControlFlow; }
 
   /// Return true if the function body is non-contiguous.
   bool isSplit() const { return isSimple() && getLayout().isSplit(); }
 
-  bool shouldPreserveNops() const { return PreserveNops; }
+  bool shouldPreserveNops() const { return isPseudo() || PreserveNops; }
 
   /// Return true if the function has exception handling tables.
   bool hasEHRanges() const { return HasEHRanges; }
 
   /// Return true if the function uses DW_CFA_GNU_args_size CFIs.
   bool usesGnuArgsSize() const { return UsesGnuArgsSize; }
 
   /// Return true if the function has more than one entry point.

 
   void handleIndirectBranch(MCInst &Instruction, uint64_t Size,
                             uint64_t Offset);
 
   // Check for linker veneers, which lack relocations and need manual
   // adjustments.
   void handleAArch64IndirectCall(MCInst &Instruction, const uint64_t Offset);
 
+  bool handlePLT();
   /// Scan function for references to other functions. In relocation mode,
   /// add relocations for external references. In non-relocation mode, detect
   /// and mark new entry points.
   ///
   /// Return true on success. False if the disassembly failed or relocations
   /// could not be created.
   bool scanExternalRefs();
 

bolt/include/bolt/Core/BinarySection.h

explicit BinarySection(BinaryContext &BC, const Twine &Name,
         Relocations(Section.Relocations),
         PendingRelocations(Section.PendingRelocations), OutputName(Name.str()),
         SectionNumber(++Count) {}
 
   BinarySection(BinaryContext &BC, SectionRef Section)
       : BC(BC), Name(getName(Section)), Section(Section),
         Contents(getContents(Section)), Address(Section.getAddress()),
         Size(Section.getSize()), Alignment(Section.getAlignment().value()),
-        OutputName(Name), SectionNumber(++Count) {
+        OutputName(Name), OutputSize(Size), OutputContents(Contents),
+        SectionNumber(++Count) {
     if (isELF()) {
       ELFType = ELFSectionRef(Section).getType();
       ELFFlags = ELFSectionRef(Section).getFlags();
       InputFileOffset = ELFSectionRef(Section).getOffset();
     } else if (isMachO()) {
       auto *O = cast<MachOObjectFile>(Section.getObject());
       InputFileOffset =
           O->is64Bit() ? O->getSection64(Section.getRawDataRefImpl()).offset
public:
   }
 
   bool operator!=(const BinarySection &Other) const {
     return !operator==(Other);
   }
 
   // Order sections by their immutable properties.
   bool operator<(const BinarySection &Other) const {
-    // Allocatable before non-allocatable.
-    if (isAllocatable() != Other.isAllocatable())
-      return isAllocatable() > Other.isAllocatable();
-
-    // Input sections take precedence.
-    if (hasSectionRef() != Other.hasSectionRef())
-      return hasSectionRef() > Other.hasSectionRef();
-
-    // Compare allocatable input sections by their address.
-    if (hasSectionRef() && getAddress() != Other.getAddress())
+    if (getAddress() != Other.getAddress())
       return getAddress() < Other.getAddress();
-    if (hasSectionRef() && getAddress() && getSize() != Other.getSize())
-      return getSize() < Other.getSize();
 
-    // Code before data.
-    if (isText() != Other.isText())
-      return isText() > Other.isText();
-
-    // Read-only before writable.
-    if (isWritable() != Other.isWritable())
-      return isWritable() < Other.isWritable();
-
-    // BSS at the end.
-    if (isBSS() != Other.isBSS())
-      return isBSS() < Other.isBSS();
+    // We want to keep tdata/tbss together to properly calculate
+    // TLS segment size, and since .tbss may have the same address
+    // as the section after it, we have this check
+    if (isTBSS() || Other.isTBSS())
+      return isTBSS() && !Other.isTBSS();
+
+    if (getSize() != Other.getSize())
+      return getSize() < Other.getSize();
 
-    // Otherwise, preserve the order of creation.
-    return SectionNumber < Other.SectionNumber;
+    return getName() < Other.getName();
   }
 
   ///
   /// Basic property access.
   ///
   BinaryContext &getBinaryContext() { return BC; }
   bool isELF() const;
   bool isMachO() const;
   StringRef getName() const { return Name; }
   uint64_t getAddress() const { return Address; }
   uint64_t getEndAddress() const { return Address + Size; }
+  uint64_t getOutputEndAddress() const { return OutputAddress + OutputSize; }
   uint64_t getSize() const { return Size; }
   uint64_t getInputFileOffset() const { return InputFileOffset; }
   Align getAlign() const { return Align(Alignment); }
   uint64_t getAlignment() const { return Alignment; }
   bool isText() const {
     if (isELF())
       return (ELFFlags & ELF::SHF_EXECINSTR);
     return hasSectionRef() && getSectionRef().isText();
public:
   bool isTLS() const { return (ELFFlags & ELF::SHF_TLS); }
   bool isTBSS() const { return isBSS() && isTLS(); }
   bool isVirtual() const { return ELFType == ELF::SHT_NOBITS; }
   bool isRela() const { return ELFType == ELF::SHT_RELA; }
   bool isRelr() const { return ELFType == ELF::SHT_RELR; }
   bool isWritable() const { return (ELFFlags & ELF::SHF_WRITE); }
   bool isAllocatable() const {
     if (isELF()) {
-      return (ELFFlags & ELF::SHF_ALLOC) && !isTBSS();
+      return (ELFFlags & ELF::SHF_ALLOC);
     } else {
       // On non-ELF assume all sections are allocatable.
       return true;
     }
   }
   bool isReordered() const { return IsReordered; }
   bool isAnonymous() const { return IsAnonymous; }
   bool isRelro() const { return IsRelro; }
public:
   }
 
   /// Does this section have any non-pending relocations?
   bool hasRelocations() const { return !Relocations.empty(); }
 
   /// Does this section have any pending relocations?
   bool hasPendingRelocations() const { return !PendingRelocations.empty(); }
 
+  bool hasDynamicRelocations() const { return !DynamicRelocations.empty(); }
+
   /// Remove non-pending relocation with the given /p Offset.
   bool removeRelocationAt(uint64_t Offset) {
     auto Itr = Relocations.find(Offset);
     if (Itr != Relocations.end()) {
       auto End = Relocations.upper_bound(Offset);
       Relocations.erase(Itr, End);
       return true;
     }
     return false;
   }
 
   void clearRelocations();
 
-  /// Add a new relocation at the given /p Offset.
   void addRelocation(uint64_t Offset, MCSymbol *Symbol, uint64_t Type,
-                     uint64_t Addend, uint64_t Value = 0,
-                     bool Pending = false) {
-    assert(Offset < getSize() && "offset not within section bounds");
-    if (!Pending) {
-      Relocations.emplace(Relocation{Offset, Symbol, Type, Addend, Value});
-    } else {
-      PendingRelocations.emplace_back(
-          Relocation{Offset, Symbol, Type, Addend, Value});
-    }
-  }
+                     uint64_t Addend, uint64_t Value = 0, bool Pending = false);
 
   /// Add a dynamic relocation at the given /p Offset.
   void addDynamicRelocation(uint64_t Offset, MCSymbol *Symbol, uint64_t Type,
                             uint64_t Addend, uint64_t Value = 0) {
     assert(Offset < getSize() && "offset not within section bounds");
     DynamicRelocations.emplace(Relocation{Offset, Symbol, Type, Addend, Value});
   }
 
public:
   BinaryPatcher *getPatcher() { return Patcher.get(); }
 
   /// Lookup the relocation (if any) at the given /p Offset.
   const Relocation *getRelocationAt(uint64_t Offset) const {
     auto Itr = Relocations.find(Offset);
     return Itr != Relocations.end() ? &*Itr : nullptr;
   }
 
-  /// Lookup the relocation (if any) at the given /p Offset.
+  uint64_t getNewEndSymbolValue(uint64_t RelocationOffset) const;
+
+  /// Lookup the dynamic relocation (if any) at the given /p Offset.
   const Relocation *getDynamicRelocationAt(uint64_t Offset) const {
     Relocation Key{Offset, 0, 0, 0, 0};
     auto Itr = DynamicRelocations.find(Key);
     return Itr != DynamicRelocations.end() ? &*Itr : nullptr;
   }
 
   uint64_t hash(const BinaryData &BD) const {
     std::map<const BinaryData *, uint64_t> Cache;

bolt/include/bolt/Core/MCPlusBuilder.h

virtual bool isSUB(const MCInst &Inst) const {
     return false;
   }
 
   virtual bool isLEA64r(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
+  virtual bool isCall64m(const MCInst &Inst) const {
+    llvm_unreachable("not implemented");
+    return false;
+  }
+
   virtual bool isLeave(const MCInst &Inst) const { return false; }
 
+  virtual bool isADD(const MCInst &Inst) const {
+    llvm_unreachable("not implemented");
+    return false;
+  }
+
   virtual bool isADRP(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
   virtual bool isADR(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
public:
   /// memory accessing instruction, this immediate is the memory address
   /// displacement. Otherwise, the target operand is the first immediate
   /// operand found in \p Inst. Return false if no imm operand found.
   virtual bool addToImm(MCInst &Inst, int64_t &Amt, MCContext *Ctx) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
+  virtual bool relaxLdrToAdd(MCInst &Inst) const {
+    llvm_unreachable("not implemented");
+    return false;
+  }
+
   /// Replace the compound memory operand of Inst with an immediate operand.
   /// The value of the immediate operand is computed by reading the \p
   /// ConstantData array starting from \p offset and assuming little-endianess.
   /// Return true on success. The given instruction is modified in place.
   virtual bool replaceMemOperandWithImm(MCInst &Inst, StringRef ConstantData,
                                         uint64_t Offset) const {
     llvm_unreachable("not implemented");
     return false;
analyzeIndirectBranch(MCInst &Instruction, InstructionIterator Begin,
                         unsigned &IndexRegNum, int64_t &DispValue,
                         const MCExpr *&DispExpr, MCInst *&PCRelBaseOut) const {
     llvm_unreachable("not implemented");
     return IndirectBranchType::UNKNOWN;
   }
 
   /// Analyze branch \p Instruction in PLT section and try to determine
   /// associated got entry address.
-  virtual uint64_t analyzePLTEntry(MCInst &Instruction,
-                                   InstructionIterator Begin,
+  virtual uint64_t analyzePLTEntry(InstructionIterator Begin,
                                    InstructionIterator End,
                                    uint64_t BeginPC) const {
     llvm_unreachable("not implemented");
     return 0;
   }
 
   virtual bool analyzeVirtualMethodCall(InstructionIterator Begin,
                                         InstructionIterator End,
virtual uint64_t matchLinkerVeneer(InstructionIterator Begin,
                                      InstructionIterator End, uint64_t Address,
                                      const MCInst &CurInst,
                                      MCInst *&TargetHiBits,
                                      MCInst *&TargetLowBits,
                                      uint64_t &Target) const {
     llvm_unreachable("not implemented");
   }
 
-  virtual bool matchAdrpAddPair(const MCInst &Adrp, const MCInst &Add) const {
+  // match adrp+add or adrp+ldr
+  virtual bool matchAdrpPair(const MCInst &Adrp, const MCInst &AddOrLdr) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
+  virtual bool patchPLTInstructions(InstructionIterator Begin,
+                                    InstructionIterator End,
+                                    const MCSymbol *Target, MCContext *Ctx,
+                                    const MCSymbol *BFSymbol) const {
+    llvm_unreachable("not implemented");
+  }
+
   virtual int getShortJmpEncodingSize() const {
     llvm_unreachable("not implemented");
   }
 
   virtual int getUncondBranchEncodingSize() const {
     llvm_unreachable("not implemented");
     return 0;
   }

bolt/include/bolt/Passes/FixRelaxationPass.h

-//===- bolt/Passes/ADRRelaxationPass.h --------------------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares the FixRelaxations class, which locates instructions with
-// wrong targets and fixes them. Such problems usually occures when linker
-// relaxes (changes) instructions, but doesn't fix relocations types properly
-// for them.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef BOLT_PASSES_FIXRELAXATIONPASS_H
-#define BOLT_PASSES_FIXRELAXATIONPASS_H
-
-#include "bolt/Passes/BinaryPasses.h"
-
-namespace llvm {
-namespace bolt {
-
-class FixRelaxations : public BinaryFunctionPass {
-  void runOnFunction(BinaryFunction &Function);
-
-public:
-  explicit FixRelaxations(const cl::opt<bool> &PrintPass)
-      : BinaryFunctionPass(PrintPass) {}
-
-  const char *getName() const override { return "fix-relaxations"; }
-
-  /// Pass entry point
-  void runOnFunctions(BinaryContext &BC) override;
-};
-
-} // namespace bolt
-} // namespace llvm
-
-#endif

bolt/include/bolt/Passes/LongJmp.h

class LongJmpPass : public BinaryFunctionPass {
 
   /// Used to quickly identify whether a BB is a stub, sharded by function
   DenseMap<const BinaryFunction *, std::set<const BinaryBasicBlock *>> Stubs;
 
   using FuncAddressesMapTy = DenseMap<const BinaryFunction *, uint64_t>;
   /// Hold tentative addresses
   FuncAddressesMapTy HotAddresses;
   FuncAddressesMapTy ColdAddresses;
+  uint64_t TentativePLTAddress{0};
   DenseMap<const BinaryBasicBlock *, uint64_t> BBAddresses;
 
   /// Used to identify the stub size
   DenseMap<const BinaryBasicBlock *, int> StubBits;
 
   /// Stats about number of stubs inserted
   uint32_t NumHotStubs{0};
   uint32_t NumColdStubs{0};

bolt/include/bolt/Rewrite/ExecutableFileMemoryManager.h

public:
 
   void allocate(const jitlink::JITLinkDylib *JD, jitlink::LinkGraph &G,
                 OnAllocatedFunction OnAllocated) override;
 
   void deallocate(std::vector<FinalizedAlloc> Allocs,
                   OnDeallocatedFunction OnDeallocated) override;
   using JITLinkMemoryManager::deallocate;
 
-  /// Section name management.
-  void setNewSecPrefix(StringRef Prefix) { NewSecPrefix = Prefix; }
-  void setOrgSecPrefix(StringRef Prefix) { OrgSecPrefix = Prefix; }
 };
 
 } // namespace bolt
 } // namespace llvm
 
 #endif

bolt/include/bolt/Rewrite/RewriteInstance.h

private:
   void printRelocationInfo(const RelocationRef &Rel, StringRef SymbolName,
                            uint64_t SymbolAddress, uint64_t Addend,
                            uint64_t ExtractedValue) const;
 
   /// Read relocations from a given section.
   void readRelocations(const object::SectionRef &Section);
 
   /// Handle one relocation.
-  void handleRelocation(const object::SectionRef &RelocatedSection,
+  void handleRelocation(BinarySection &RelocatedSection,
                         const RelocationRef &Rel);
 
   /// Mark functions that are not meant for processing as ignored.
   void selectFunctionsToProcess();
 
   /// Read information from debug sections.
   void readDebugInfo();
 
private:
   /// BinaryFunction object, preparing all information necessary for binary
   /// optimization.
   void disassembleFunctions();
 
   void buildFunctionsCFG();
 
   void postProcessFunctions();
 
-  void preregisterSections();
+  void renameAndPreregisterSections();
 
   /// Run optimizations that operate at the binary, or post-linker, level.
   void runOptimizationPasses();
 
   /// Write code and data into an intermediary object file, map virtual to real
   /// addresses and link the object file, resolving all relocations and
   /// performing final relaxation.
   void emitAndLink();
 
   /// Link additional runtime code to support instrumentation.
   void linkRuntime();
 
   /// Process metadata in special sections before CFG is built for functions.
   void processMetadataPreCFG();
 
   /// Process metadata in special sections after CFG is built for functions.
   void processMetadataPostCFG();
 
   /// Update debug and other auxiliary information in the file.
   void updateMetadata();
 
-  /// Return the list of code sections in the output order.
-  std::vector<BinarySection *> getCodeSections();
+  // Get sections within address space of a provided segment
+  std::vector<BinarySection *> getSectionsForSegment(const ProgramHeader &Phdr,
+                                                     bool IncludeNew = true);
+
+  // Put a non-load segment in the vector of output segments
+  void createNonLoadSegment(const std::vector<BinarySection *> &Sections,
+                            const unsigned p_type, const unsigned p_flags,
+                            const unsigned p_align);
+
+  // Put a load segment in the vector of output segments and
+  // create a mapping for it
+  void
+  createLoadSegment(const std::vector<BinarySection *> &Sections,
+                    BOLTLinker::SectionMapper AssignAddress,
+                    const unsigned p_flags, const unsigned p_align,
+                    const std::optional<uint64_t> ForceAddress = std::nullopt);
+
+  // Assign addresses to a group of sections, return size of nobits
+  uint64_t mapSectionGroup(const std::vector<BinarySection *> &Sections,
+                           BOLTLinker::SectionMapper AssignAddress);
+
+  void mapFunctionsNonRelocMode(BOLTLinker::SectionMapper AssignAddress);
+
+  // Assign address to a single section
+  void mapSection(BinarySection &Section);
+
+  // Assign addresses to all allocatable sections
+  void mapAllocatableSections(BOLTLinker::SectionMapper AssignAddress);
+
+  /// Assign addresses and create segments for the loadable part of executable
+  void mapLoadableSegments(BOLTLinker::SectionMapper AssignAddress);
+
+  /// Assign addresses and create segments for the runtime library if present
+  void mapRuntimeLibrary(BOLTLinker::SectionMapper AssignAddress);
+
+  // Copy segment from input to output as it is
+  void copySegment(const ProgramHeader &Segment,
+                   BOLTLinker::SectionMapper AssignAddress);
+
+  // If we don't rewrite, we remap old segments to the same addresses
+  // and copy their respective sections. Then create new segments and map
+  // new sections into them.
+  void remapLoadableSegments(BOLTLinker::SectionMapper AssignAddress);
 
-  /// Map all sections to their final addresses.
-  void mapFileSections(BOLTLinker::SectionMapper MapSection);
-
-  /// Map code sections generated by BOLT.
-  void mapCodeSections(BOLTLinker::SectionMapper MapSection);
-
-  /// Map the rest of allocatable sections.
-  void mapAllocatableSections(BOLTLinker::SectionMapper MapSection);
+  // Copy non-loadable segments to the output, updating offsets/addresses
+  void mapNonLoadableSegments();
 
   /// Update output object's values based on the final \p Layout.
   void updateOutputValues(const MCAsmLayout &Layout);
 
   /// Rewrite back all functions (hopefully optimized) that fit in the original
   /// memory footprint for that function. If the function is now larger and does
   /// not fit in the binary, reject it and preserve the original version of the
   /// function. If we couldn't understand the function for some reason in
bool analyzeRelocation(const object::RelocationRef &Rel, uint64_t &RType,
                          uint64_t &ExtractedValue, bool &Skip) const;
 
   /// Rewrite non-allocatable sections with modifications.
   void rewriteNoteSections();
 
   /// Write .eh_frame_hdr.
   void writeEHFrameHeader();
 
+  void mapEhFrameAndHeader(BOLTLinker::SectionMapper AssignAddress);
+
+  void createGOTPLTRelocations();
+
   /// Disassemble and create function entries for PLT.
   void disassemblePLT();
 
   /// Auxiliary function to create .plt BinaryFunction on \p EntryAddres
   /// with the \p EntrySize size. \p TargetAddress is the .got entry
   /// associated address.
-  void createPLTBinaryFunction(uint64_t TargetAddress, uint64_t EntryAddress,
+  BinaryFunction *createPLTBinaryFunction(uint64_t TargetAddress,
+                                          uint64_t EntryAddress,
                                           uint64_t EntrySize);
 
   /// Disassemble aarch64-specific .plt \p Section auxiliary function
   void disassemblePLTSectionAArch64(BinarySection &Section);
 
   /// Disassemble X86-specific .plt \p Section auxiliary function. \p EntrySize
   /// is the expected .plt \p Section entry function size.
   void disassemblePLTSectionX86(BinarySection &Section, uint64_t EntrySize);
 
   /// Disassemble riscv-specific .plt \p Section auxiliary function
   void disassemblePLTSectionRISCV(BinarySection &Section);
 
   /// ELF-specific part. TODO: refactor into new class.
 #define ELF_FUNCTION(TYPE, FUNC)                                               \
   template <typename ELFT> TYPE FUNC(object::ELFObjectFile<ELFT> *Obj);        \
   TYPE FUNC() {                                                                \
     if (auto *ELF32LE = dyn_cast<object::ELF32LEObjectFile>(InputFile))        \
       return FUNC(ELF32LE);                                                    \
     if (auto *ELF64LE = dyn_cast<object::ELF64LEObjectFile>(InputFile))        \
       return FUNC(ELF64LE);                                                    \
     if (auto *ELF32BE = dyn_cast<object::ELF32BEObjectFile>(InputFile))        \
       return FUNC(ELF32BE);                                                    \
     auto *ELF64BE = cast<object::ELF64BEObjectFile>(InputFile);                \
     return FUNC(ELF64BE);                                                      \
   }
 
-  /// Patch ELF book-keeping info.
-  void patchELFPHDRTable();
+  void writeELFPHDRTable();
 
   /// Create section header table.
   ELF_FUNCTION(void, patchELFSectionHeaderTable);
 
   /// Create the regular symbol table and patch dyn symbol tables.
   ELF_FUNCTION(void, patchELFSymTabs);
 
   /// Read dynamic section/segment of ELF.
   ELF_FUNCTION(Error, readELFDynamic);
 
   /// Patch dynamic section/segment of ELF.
   ELF_FUNCTION(void, patchELFDynamic);
 
-  /// Patch .got
-  ELF_FUNCTION(void, patchELFGOT);
-
   /// Patch allocatable relocation sections.
   ELF_FUNCTION(void, patchELFAllocatableRelaSections);
 
   /// Patch allocatable relr section.
   ELF_FUNCTION(void, patchELFAllocatableRelrSection);
 
   /// Finalize memory image of section header string table.
   ELF_FUNCTION(void, finalizeSectionStringTable);
 
   /// Return a list of all sections to include in the output binary.
   /// Populate \p NewSectionIndex with a map of input to output indices.
   template <typename ELFT>
   std::vector<typename object::ELFObjectFile<ELFT>::Elf_Shdr>
   getOutputSections(object::ELFObjectFile<ELFT> *File,
                     std::vector<uint32_t> &NewSectionIndex);
 
   /// Return true if \p Section should be stripped from the output binary.
   template <typename ELFShdrTy>
   bool shouldStrip(const ELFShdrTy &Section, StringRef SectionName);
+  bool shouldStrip(const BinarySection &Section);
 
   /// Write ELF symbol table using \p Write and \p AddToStrTab functions
   /// based on the input file symbol table passed in \p SymTabSection.
   /// \p IsDynSym is set to true for dynamic symbol table since we
   /// are updating it in-place with minimal modifications.
   template <typename ELFT, typename WriteFuncTy, typename StrTabFuncTy>
   void updateELFSymbolTable(
       object::ELFObjectFile<ELFT> *File, bool IsDynSym,
#define ELF_FUNCTION(TYPE, FUNC)                                               \
   /// Loop over now emitted functions to write translation maps
   void encodeBATSection();
 
   /// Update the ELF note section containing the binary build-id to reflect
   /// a new build-id, so tools can differentiate between the old and the
   /// rewritten binary.
   void patchBuildID();
 
-  /// Return file offset corresponding to a given virtual address.
-  uint64_t getFileOffsetFor(uint64_t Address) {
-    assert(Address >= NewTextSegmentAddress &&
-           "address in not in the new text segment");
-    return Address - NewTextSegmentAddress + NewTextSegmentOffset;
-  }
-
   /// Return file offset corresponding to a virtual \p Address.
   /// Return 0 if the address has no mapping in the file, including being
   /// part of .bss section.
-  uint64_t getFileOffsetForAddress(uint64_t Address) const;
-
+  uint64_t getFileOffsetForAddress(const uint64_t Address) const;
+  uint64_t getOutputFileOffsetForAddress(const uint64_t Address) const;
   /// Return true if we will overwrite contents of the section instead
   /// of appending contents to it.
   bool willOverwriteSection(StringRef SectionName);
 
 public:
   /// Standard ELF sections we overwrite.
   static constexpr const char *SectionsToOverwrite[] = {
       ".shstrtab",
private:
   static StringRef getOrgSecPrefix() { return ".bolt.org"; }
 
   /// Section name used for extra BOLT code in addition to .text.
   static StringRef getBOLTTextSectionName() { return ".bolt.text"; }
 
   /// Common section names.
   static StringRef getEHFrameSectionName() { return ".eh_frame"; }
 
+  static StringRef getEHFrameHeaderSectionName() { return ".eh_frame_hdr"; }
   /// An instance of the input binary we are processing, externally owned.
   llvm::object::ELFObjectFileBase *InputFile;
 
   /// Command line args used to process binary.
   const int Argc;
   const char *const *Argv;
   StringRef ToolPath;
 
   std::unique_ptr<ProfileReaderBase> ProfileReader;
 
   std::unique_ptr<BinaryContext> BC;
   std::unique_ptr<CFIReaderWriter> CFIRdWrt;
 
   // Run ExecutionEngine linker with custom memory manager and symbol resolver.
   std::unique_ptr<BOLTLinker> Linker;
 
   /// Output file where we mix original code from the input binary and
   /// optimized code for selected functions.
   std::unique_ptr<ToolOutputFile> Out;
 
   /// Offset in the input file where non-allocatable sections start.
   uint64_t FirstNonAllocatableOffset{0};
-
   /// Information about program header table.
   uint64_t PHDRTableAddress{0};
   uint64_t PHDRTableOffset{0};
-  unsigned Phnum{0};
-
-  /// New code segment info.
-  uint64_t NewTextSegmentAddress{0};
-  uint64_t NewTextSegmentOffset{0};
-  uint64_t NewTextSegmentSize{0};
-
-  /// New writable segment info.
-  uint64_t NewWritableSegmentAddress{0};
-  uint64_t NewWritableSegmentSize{0};
-
+  uint64_t BaseAddress{0};
+  bool HasProgramHeaderSegment{false};
+  bool HasReadOnlySegment{false};
   /// Track next available address for new allocatable sections.
   uint64_t NextAvailableAddress{0};
 
   /// Location and size of dynamic relocations.
   std::optional<uint64_t> DynamicRelocationsAddress;
   uint64_t DynamicRelocationsSize{0};
   uint64_t DynamicRelativeRelocationsCount{0};
 
   // Location and size of .relr.dyn relocations.
   std::optional<uint64_t> DynamicRelrAddress;
   uint64_t DynamicRelrSize{0};
   uint64_t DynamicRelrEntrySize{0};
 
   /// PLT relocations are special kind of dynamic relocations stored separately.
   std::optional<uint64_t> PLTRelocationsAddress;
   uint64_t PLTRelocationsSize{0};
 
   /// True if relocation of specified type came from .rela.plt
   DenseMap<uint64_t, bool> IsJmpRelocation;
 
   /// Index of specified symbol in the dynamic symbol table. NOTE Currently it
   /// is filled and used only with the relocations-related symbols.
   std::unordered_map<const MCSymbol *, uint32_t> SymbolIndex;
 
+  // A map to get GOT entry address by symbol name for AArch64.
+  // Used to resolve non-relaxed GOT accesses.
+  // It is not strictly GOT and may include entries from init_array
+  // or similar sections since references to them use GOT-typed relocations.
+  std::unordered_map<std::string, uint64_t> GOTSymbolsByName;
+
   /// Store all non-zero symbols in this map for a quick address lookup.
   std::map<uint64_t, llvm::object::SymbolRef> FileSymRefs;
 
   std::unique_ptr<DWARFRewriter> DebugInfoRewriter;
 
   std::unique_ptr<BoltAddressTranslation> BAT;
 
   /// Number of local symbols in newly written symbol table.

bolt/include/bolt/Utils/CommandLineOpts.h

 // The format to use with -o in aggregation mode (perf2bolt)
 enum ProfileFormatKind { PF_Fdata, PF_YAML };
 
 extern llvm::cl::opt<ProfileFormatKind> ProfileFormat;
 extern llvm::cl::opt<bool> SplitEH;
 extern llvm::cl::opt<bool> StrictMode;
 extern llvm::cl::opt<bool> TimeOpts;
 extern llvm::cl::opt<bool> UseOldText;
+extern llvm::cl::opt<bool> Rewrite;
 extern llvm::cl::opt<bool> UpdateDebugSections;
 
 // The default verbosity level (0) is pretty terse, level 1 is fairly
 // verbose and usually prints some informational message for every
 // function processed.  Level 2 is for the noisiest of messages and
 // often prints a message per basic block.
 // Error messages should never be suppressed by the verbosity level.
 // Only warnings and info messages should be affected.

bolt/lib/Core/BinaryContext.cpp

 
 using namespace llvm;
 
 #undef  DEBUG_TYPE
 #define DEBUG_TYPE "bolt"
 
 namespace opts {
 
-cl::opt<bool> NoHugePages("no-huge-pages",
+cl::opt<bool> NoHugePages("no-huge-pages", cl::init(true),
                           cl::desc("use regular size pages for code alignment"),
                           cl::Hidden, cl::cat(BoltCategory));
 
 static cl::opt<bool>
 PrintDebugInfo("print-debug-info",
   cl::desc("print debug info when printing functions"),
   cl::Hidden,
   cl::ZeroOrMore,

 BinaryContext::getSubBinaryData(BinaryData *BD) {
   auto Start = std::next(BinaryDataMap.find(BD->getAddress()));
   auto End = Start;
   while (End != BinaryDataMap.end() && BD->isAncestorOf(End->second))
     ++End;
   return make_range(Start, End);
 }
 
+std::vector<BinarySection *>
+BinaryContext::getNewSectionsByFlags(unsigned Flags, bool ROwithRX) {
+  std::vector<BinarySection *> Result;
+  for (BinarySection &Section : allocatableSections()) {
+    if (!isExtra(Section))
+      continue;
+    if (Section.getOutputAddress() || !Section.hasValidSectionID())
+      continue;
+
+    const unsigned SecFlags = Section.getELFFlags();
+    if (SecFlags == Flags || (ROwithRX && SecFlags == ELF::SHF_ALLOC &&
+                              Flags == (ELF::SHF_ALLOC | ELF::SHF_EXECINSTR)))
+      Result.push_back(&Section);
+  }
+
+  if (Flags & ELF::SHF_EXECINSTR) {
+
+    auto CompareSections = [&](const BinarySection *A, const BinarySection *B) {
+      // executable first
+      if (A->isText() != B->isText())
+        return A->isText() > B->isText();
+      // non-executable last
+      if (!A->isText())
+        return false;
+      // Place movers before anything else.
+      if (A->getName() == getHotTextMoverSectionName())
+        return true;
+      if (B->getName() == getHotTextMoverSectionName())
+        return false;
+
+      // Depending on the option, put main text at the beginning or at the end.
+      if (opts::HotFunctionsAtEnd)
+        return B->getName() == getMainCodeSectionName();
+      else
+        return A->getName() == getMainCodeSectionName();
+    };
+    llvm::stable_sort(Result, CompareSections);
+  }
+  return Result;
+}
+
 std::pair<const MCSymbol *, uint64_t>
 BinaryContext::handleAddressRef(uint64_t Address, BinaryFunction &BF,
                                 bool IsPCRel) {
   if (isAArch64()) {
     // Check if this is an access to a constant island and create bookkeeping
     // to keep track of it and emit it later as part of this function.
     if (MCSymbol *IslandSym = BF.getOrCreateIslandAccess(Address))
       return std::make_pair(IslandSym, 0);
void BinaryContext::printInstruction(raw_ostream &OS, const MCInst &Instruction,
   }
 }
 
 std::optional<uint64_t>
 BinaryContext::getBaseAddressForMapping(uint64_t MMapAddress,
                                         uint64_t FileOffset) const {
   // Find a segment with a matching file offset.
   for (auto &KV : SegmentMapInfo) {
-    const SegmentInfo &SegInfo = KV.second;
-    if (alignDown(SegInfo.FileOffset, SegInfo.Alignment) == FileOffset) {
+    const ProgramHeader &SegInfo = KV.second;
+    if (alignDown(SegInfo.p_offset, SegInfo.p_align) == FileOffset) {
       // Use segment's aligned memory offset to calculate the base address.
-      const uint64_t MemOffset = alignDown(SegInfo.Address, SegInfo.Alignment);
+      const uint64_t MemOffset = alignDown(SegInfo.p_vaddr, SegInfo.p_align);
       return MMapAddress - MemOffset;
     }
   }
 
   return std::nullopt;
 }
 
 ErrorOr<BinarySection &> BinaryContext::getSectionForAddress(uint64_t Address) {

bolt/lib/Core/BinaryData.cpp

 
 void BinaryData::setSection(BinarySection &NewSection) {
   if (OutputSection == Section)
     OutputSection = &NewSection;
   Section = &NewSection;
 }
 
 bool BinaryData::isMoved() const {
-  return (getOffset() != OutputOffset || OutputSection != Section);
+  assert(OutputSection && Section);
+  return (getOffset() != OutputOffset ||
+          OutputSection->getOutputAddress() != Section->getAddress());
 }
 
 void BinaryData::print(raw_ostream &OS) const { printBrief(OS); }
 
 void BinaryData::printBrief(raw_ostream &OS) const {
   OS << "(";
 
   if (isJumpTable())

bolt/lib/Core/BinaryEmitter.cpp

 
 private:
   /// Emit function code.
   void emitFunctions();
 
   /// Emit a single function.
   bool emitFunction(BinaryFunction &BF, FunctionFragment &FF);
 
+  void emitPLTFunction(BinaryFunction &BF);
   /// Helper for emitFunctionBody to write data inside a function
   /// (used for AArch64)
   void emitConstantIslands(BinaryFunction &BF, bool EmitColdPart,
                            BinaryFunction *OnBehalfOf = nullptr);
 
   /// Emit jump tables for the function.
   void emitJumpTables(const BinaryFunction &BF);
 
void BinaryEmitter::emitAll(StringRef OrgSecPrefix) {
   if (opts::UpdateDebugSections) {
     emitDebugLineInfoForOriginalFunctions();
     DwarfLineTable::emit(BC, Streamer);
   }
 
   emitDataSections(OrgSecPrefix);
 }
 
+void BinaryEmitter::emitPLTFunction(BinaryFunction &BF) {
+  assert(BF.begin() + 1 == BF.end());
+  MCSection *Section = BC.getCodeSection(BF.getOriginSection()->getName());
+  Streamer.switchSection(Section);
+  Section->setAlignment(Align(BF.getOriginSection()->getAlignment()));
+  Section->setHasInstructions(true);
+  Streamer.emitLabel(BF.getSymbol());
+  for (auto &BB : BF)
+    for (auto Instr : BB)
+      Streamer.emitInstruction(Instr, *BC.STI);
+}
+
 void BinaryEmitter::emitFunctions() {
   auto emit = [&](const std::vector<BinaryFunction *> &Functions) {
     const bool HasProfile = BC.NumProfiledFuncs > 0;
     const bool OriginalAllowAutoPadding = Streamer.getAllowAutoPadding();
     for (BinaryFunction *Function : Functions) {
-      if (!BC.shouldEmit(*Function))
+      if (!BC.shouldEmit(*Function) &&
+          !(Function->isPLTFunction() && opts::Rewrite && BC.isRISC()))
         continue;
 
       LLVM_DEBUG(dbgs() << "BOLT: generating code for function \"" << *Function
                         << "\" : " << Function->getFunctionNumber() << '\n');
 
       // Was any part of the function emitted.
       bool Emitted = false;
 
       // Turn off Intel JCC Erratum mitigation for cold code if requested
-      if (HasProfile && opts::X86AlignBranchBoundaryHotOnly &&
-          !Function->hasValidProfile())
+      if ((HasProfile && opts::X86AlignBranchBoundaryHotOnly &&
+           !Function->hasValidProfile()) ||
+          Function->isPLTFunction())
         Streamer.setAllowAutoPadding(false);
 
+      if (Function->isPLTFunction()) {
+        emitPLTFunction(*Function);
+        Function->setEmitted(/*KeepCFG=*/false);
+        Streamer.setAllowAutoPadding(OriginalAllowAutoPadding);
+        continue;
+      }
+
       FunctionLayout &Layout = Function->getLayout();
       Emitted |= emitFunction(*Function, Layout.getMainFragment());
 
       if (Function->isSplit()) {
         if (opts::X86AlignBranchBoundaryHotOnly)
           Streamer.setAllowAutoPadding(false);
 
         assert((Layout.fragment_size() == 1 || Function->isSimple()) &&
void BinaryEmitter::emitLSDA(BinaryFunction &BF, const FunctionFragment &FF) {
   const BinaryFunction::LSDATypeTableTy &TypeTable =
       (TTypeEncoding & dwarf::DW_EH_PE_indirect) ? BF.getLSDATypeAddressTable()
                                                  : BF.getLSDATypeTable();
   assert(TypeTable.size() == BF.getLSDATypeTable().size() &&
          "indirect type table size mismatch");
 
   for (int Index = TypeTable.size() - 1; Index >= 0; --Index) {
     const uint64_t TypeAddress = TypeTable[Index];
+    const MCSymbol *TypeSymbol =
+        BC.getOrCreateGlobalSymbol(TypeAddress, "TI", 0, TTypeAlignment);
     switch (TTypeEncoding & 0x70) {
     default:
       llvm_unreachable("unsupported TTypeEncoding");
     case dwarf::DW_EH_PE_absptr:
-      Streamer.emitIntValue(TypeAddress, TTypeEncodingSize);
+      Streamer.emitSymbolValue(TypeSymbol, TTypeEncodingSize);
       break;
     case dwarf::DW_EH_PE_pcrel: {
       if (TypeAddress) {
-        const MCSymbol *TypeSymbol =
-            BC.getOrCreateGlobalSymbol(TypeAddress, "TI", 0, TTypeAlignment);
         MCSymbol *DotSymbol = BC.Ctx->createNamedTempSymbol();
         Streamer.emitLabel(DotSymbol);
         const MCBinaryExpr *SubDotExpr = MCBinaryExpr::createSub(
             MCSymbolRefExpr::create(TypeSymbol, *BC.Ctx),
             MCSymbolRefExpr::create(DotSymbol, *BC.Ctx), *BC.Ctx);
         Streamer.emitValue(SubDotExpr, TTypeEncodingSize);
       } else {
         Streamer.emitIntValue(0, TTypeEncodingSize);
void BinaryEmitter::emitDebugLineInfoForUnprocessedCUs() {
   }
 }
 
 void BinaryEmitter::emitDataSections(StringRef OrgSecPrefix) {
   for (BinarySection &Section : BC.sections()) {
     if (!Section.hasRelocations())
       continue;
 
-    StringRef Prefix = Section.hasSectionRef() ? OrgSecPrefix : "";
-    Section.emitAsData(Streamer, Prefix + Section.getName());
+    assert(Section.getOutputName() != BC.getMainCodeSectionName() &&
+           Section.getOutputName() !=
+               (OrgSecPrefix + BC.getMainCodeSectionName()).str() &&
+           ".text should not have relocations!");
+
+    Section.emitAsData(Streamer, Section.getOutputName());
+    // because dynamic relocations usually contain addresses without symbols,
+    // we neeed to preserve usual relocations to detect end-of section
+    // references
+    if (!Section.hasDynamicRelocations())
       Section.clearRelocations();
   }
 }
 
 namespace llvm {
 namespace bolt {
 
 void emitBinaryContext(MCStreamer &Streamer, BinaryContext &BC,
                        StringRef OrgSecPrefix) {

bolt/lib/Core/BinaryFunction.cpp

 //===----------------------------------------------------------------------===//
 
 #include "bolt/Core/BinaryFunction.h"
 #include "bolt/Core/BinaryBasicBlock.h"
 #include "bolt/Core/BinaryDomTree.h"
 #include "bolt/Core/DynoStats.h"
 #include "bolt/Core/HashUtilities.h"
 #include "bolt/Core/MCPlusBuilder.h"
+#include "bolt/Utils/CommandLineOpts.h"
 #include "bolt/Utils/NameResolver.h"
 #include "bolt/Utils/NameShortener.h"
 #include "bolt/Utils/Utils.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Demangle/Demangle.h"
for (auto It = std::prev(Instructions.end()); Count != 0;
       MIB->addAnnotation(It->second, "AArch64Veneer", true);
     }
 
     BC.addAdrpAddRelocAArch64(*this, *TargetLowBits, *TargetHiBits,
                               TargetAddress);
   }
 }
 
+bool BinaryFunction::handlePLT() {
+  assert(BasicBlocks.size() == 1);
+  return BC.MIB->patchPLTInstructions(BasicBlocks[0]->begin(),
+                                      BasicBlocks[0]->end(), getPLTSymbol(),
+                                      BC.Ctx.get(), getSymbol());
+}
+
 bool BinaryFunction::disassemble() {
   NamedRegionTimer T("disassemble", "Disassemble function", "buildfuncs",
                      "Build Binary Functions", opts::TimeBuild);
   ErrorOr<ArrayRef<uint8_t>> ErrorOrFunctionData = getData();
   assert(ErrorOrFunctionData && "function data is not available");
   ArrayRef<uint8_t> FunctionData = *ErrorOrFunctionData;
   assert(FunctionData.size() == getMaxSize() &&
          "function size does not match raw data size");
if (MIB->isBranch(Instruction) || MIB->isCall(Instruction)) {
       } else {
         // Could not evaluate branch. Should be an indirect call or an
         // indirect branch. Bail out on the latter case.
         if (MIB->isIndirectBranch(Instruction))
           handleIndirectBranch(Instruction, Size, Offset);
         // Indirect call. We only need to fix it if the operand is RIP-relative.
         if (IsSimple && MIB->hasPCRelOperand(Instruction))
           handlePCRelOperand(Instruction, AbsoluteInstrAddr, Size);
-
-        if (BC.isAArch64())
+        else if (opts::Rewrite && BC.isX86() &&
+                 BC.MIB->isCall64m(Instruction)) {
+          // Indirect call with possible absolute immediate. Here we assume
+          // that a relocation is present if we have such immediate and replace
+          // the immediate with symbol ref.
+          if (const Relocation *Rel =
+                  getRelocationInRange(Offset, Offset + Size)) {
+            assert(Rel->Symbol && "Indirect call without referenced symbol!");
+            int64_t Value = Rel->Value;
+            bool Ok = BC.MIB->replaceImmWithSymbolRef(Instruction, Rel->Symbol,
+                                                      Rel->Addend, Ctx.get(),
+                                                      Value, Rel->Type);
+            assert(Ok && "Failed to replace immediate with symbol ref!");
+          }
+        } else if (BC.isAArch64()) {
           handleAArch64IndirectCall(Instruction, Offset);
         }
+      }
     } else if (BC.isAArch64() || BC.isRISCV()) {
       // Check if there's a relocation associated with this instruction.
       bool UsedReloc = false;
-      for (auto Itr = Relocations.lower_bound(Offset),
-                ItrE = Relocations.lower_bound(Offset + Size);
-           Itr != ItrE; ++Itr) {
+      if (auto Itr = Relocations.find(Offset); Itr != Relocations.end()) {
         const Relocation &Relocation = Itr->second;
+        bool Result = false;
+
+        bool TLSAccessNotHandled =
+            Relocation.Type == ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
+        enum AccessType { Default, RelaxedGOTAccess, TLSGOT };
+
+        AccessType Type = [&]() {
+          if (!Instructions.size() || Itr == Relocations.begin())
+            return Default;
+          if (std::prev(Itr)->second.Type == ELF::R_AARCH64_ADR_GOT_PAGE &&
+              Relocation.Type == ELF::R_AARCH64_ADD_ABS_LO12_NC &&
+              BC.MIB->matchAdrpPair(Instructions.rbegin()->second, Instruction))
+            return RelaxedGOTAccess;
+
+          // We usually can't determine .got address for such relocations,
+          // so we assert that instructions and relocations are consecutive
+          // and extract address from instructions.
+          if (Relocation.Type == ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
+            assert(std::prev(Itr)->second.Type ==
+                       ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 &&
+                   "Couldn't find the corresponding ADRP relocation for "
+                   "R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC");
+            assert(BC.MIB->matchAdrpPair(Instructions.rbegin()->second,
+                                         Instruction) &&
+                   "Can't match TLS access instructions");
+            return TLSGOT;
+          }
+          return Default;
+        }();
+        if (Type != Default) {
+
+          const uint64_t PageAddress = std::prev(Itr)->second.Value;
+          const uint64_t PageOffset = Relocation.Value;
+
+          assert((PageAddress & 0xfff) == 0 && "Invalid ADRP operand");
+          assert((PageOffset & 0xfff) == PageOffset &&
+                 "Invalid ADD/LDR operand");
+
+          const uint64_t TargetAddress = PageAddress + PageOffset;
+
+          assert(TargetAddress && "ADRP + ADD/LDR references zero");
+
+          const MCSymbol *Symbol = [&]() -> const MCSymbol * {
+            if (Type == RelaxedGOTAccess) {
+              assert(Relocation.Symbol && "ADRP+ADD references unknown symbol");
+              return Relocation.Symbol;
+            }
+            return BC.getOrCreateGlobalSymbol(TargetAddress, "DATAat");
+          }();
+
+          Result = BC.MIB->setOperandToSymbolRef(
+              Instructions.rbegin()->second, /*OpNum*/ 1, Symbol, 0,
+              BC.Ctx.get(), ELF::R_AARCH64_ADR_PREL_PG_HI21);
+
+          Result =
+              BC.MIB->setOperandToSymbolRef(Instruction, /*OpNum*/ 2, Symbol, 0,
+                                            BC.Ctx.get(), Relocation.Type) &&
+              Result;
+          TLSAccessNotHandled = false;
+        } else {
+
           int64_t Value = Relocation.Value;
-        const bool Result = BC.MIB->replaceImmWithSymbolRef(
-            Instruction, Relocation.Symbol, Relocation.Addend, Ctx.get(), Value,
-            Relocation.Type);
+          Result = BC.MIB->replaceImmWithSymbolRef(
+              Instruction, Relocation.Symbol, Relocation.Addend, Ctx.get(),
+              Value, Relocation.Type);
+          if (Relocation.Type == ELF::R_AARCH64_ADD_ABS_LO12_NC &&
+              BC.MIB->isLoad(Instruction)) {
+            // if we see ldr with add-related relocation, it means we
+            // couldn't find the .got entry for referneced symbol during
+            // relocation processing. In that case we have to load symbol
+            // address directly, avoiding .got access altogether. It usually
+            // happens with linker-inserted symbols such as
+            // __{section}_{start,end} and shouldn't cause problems.
+            BC.MIB->relaxLdrToAdd(Instruction);
+          }
+        }
         (void)Result;
         assert(Result && "cannot replace immediate with relocation");
-
+        assert(!TLSAccessNotHandled &&
+               "Unhandled R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC");
+        (void)TLSAccessNotHandled;
         // For aarch64, if we replaced an immediate with a symbol from a
         // relocation, we mark it so we do not try to further process a
         // pc-relative operand. All we need is the symbol.
         UsedReloc = true;
       }
 
       if (!BC.isRISCV() && MIB->hasPCRelOperand(Instruction) && !UsedReloc)
         handlePCRelOperand(Instruction, AbsoluteInstrAddr, Size);
+    } else if (const Relocation *Rel =
+                   getRelocationInRange(Offset, Offset + Size)) {
+      if (auto *Sym = Rel->Symbol)
+        if (auto It = BC.EndSymbols.find(Sym->getName());
+            It != BC.EndSymbols.end()) {
+          int64_t Value;
+          LLVM_DEBUG(
+              dbgs() << formatv(
+                  "BOLT-INFO: end symbol {0} referenced in {1} + {2:x}\n",
+                  Sym->getName(), getOneName(), Offset););
+          BC.MIB->replaceImmWithSymbolRef(Instruction, Sym, Rel->Addend,
+                                          Ctx.get(), Value, Rel->Type);
+        }
     }
 
 add_instruction:
     if (getDWARFLineTable()) {
       Instruction.setLoc(findDebugLineInformationForInstructionAt(
           AbsoluteInstrAddr, getDWARFUnit(), getDWARFLineTable()));
     }
 
for (BinaryLoop::Edge &Exit : ExitEdges) {
         }
         ++BI;
       }
     }
   }
 }
 
 void BinaryFunction::updateOutputValues(const MCAsmLayout &Layout) {
+  if (isPLTFunction()) {
+    const uint64_t Offset = getAddress() - OriginSection->getAddress();
+    setOutputAddress(OriginSection->getOutputAddress() + Offset);
+    return;
+  }
   if (!isEmitted()) {
     assert(!isInjected() && "injected function should be emitted");
     setOutputAddress(getAddress());
     setOutputSize(getSize());
     return;
   }
 
   const uint64_t BaseAddress = getCodeSection()->getOutputAddress();

bolt/lib/Core/BinarySection.cpp

 } // namespace opts
 
 uint64_t BinarySection::Count = 0;
 
 bool BinarySection::isELF() const { return BC.isELF(); }
 
 bool BinarySection::isMachO() const { return BC.isMachO(); }
 
+// If there is a Relocation at Offset which references end-of-section symbol,
+// return the new value for it
+uint64_t BinarySection::getNewEndSymbolValue(uint64_t RelocationOffset) const {
+  if (const Relocation *R = getRelocationAt(RelocationOffset))
+    if (auto *Sym = R->Symbol)
+      if (auto BSecIt = BC.EndSymbols.find(Sym->getName());
+          BSecIt != BC.EndSymbols.end()) {
+        BinarySection *BSec = BSecIt->second;
+        assert(BSec->getOutputAddress() && "Unmapped section!");
+        uint64_t NewValue = BSec->getOutputEndAddress();
+        return NewValue;
+      }
+  return 0;
+}
+
+/// Add a new relocation at the given /p Offset.
+void BinarySection::addRelocation(uint64_t Offset, MCSymbol *Symbol,
+                                  uint64_t Type, uint64_t Addend,
+                                  uint64_t Value, bool Pending) {
+  if (Name == BC.getMainCodeSectionName()) {
+    errs() << formatv(
+        "BOLT-ERROR: Adding reloc to .text at {0:x}, symbol {1}\n", Offset,
+        Symbol ? Symbol->getName() : "");
+    // assert false for stacktrace
+    assert(false &&
+           "Relocations for .text should be handled by BinaryFunction!");
+    exit(1);
+  }
+  assert(Offset < getSize() && "offset not within section bounds");
+  if (!Pending) {
+    Relocations.emplace(Relocation{Offset, Symbol, Type, Addend, Value});
+  } else {
+    PendingRelocations.emplace_back(
+        Relocation{Offset, Symbol, Type, Addend, Value});
+  }
+}
+
 uint64_t
 BinarySection::hash(const BinaryData &BD,
                     std::map<const BinaryData *, uint64_t> &Cache) const {
   auto Itr = Cache.find(&BD);
   if (Itr != Cache.end())
     return Itr->second;
 
   hash_code Hash =
if (PendingRelocations.empty() && Patches.empty())
     return;
 
   const uint64_t SectionAddress = getAddress();
 
   // We apply relocations to original section contents. For allocatable sections
   // this means using their input file offsets, since the output file offset
   // could change (e.g. for new instance of .text). For non-allocatable
   // sections, the output offset should always be a valid one.
-  const uint64_t SectionFileOffset =
-      isAllocatable() ? getInputFileOffset() : getOutputFileOffset();
+  const uint64_t SectionFileOffset = getOutputFileOffset();
   LLVM_DEBUG(
       dbgs() << "BOLT-DEBUG: flushing pending relocations for section "
              << getName() << '\n'
              << "  address: 0x" << Twine::utohexstr(SectionAddress) << '\n'
              << "  offset: 0x" << Twine::utohexstr(SectionFileOffset) << '\n');
 
   for (BinaryPatch &Patch : Patches)
     OS.pwrite(Patch.Bytes.data(), Patch.Bytes.size(),

bolt/lib/Core/Relocation.cpp

static bool isSupportedRISCV(uint64_t Type) {
   case ELF::R_RISCV_RELAX:
   case ELF::R_RISCV_GOT_HI20:
   case ELF::R_RISCV_PCREL_HI20:
   case ELF::R_RISCV_PCREL_LO12_I:
   case ELF::R_RISCV_RVC_JUMP:
   case ELF::R_RISCV_RVC_BRANCH:
   case ELF::R_RISCV_ADD32:
   case ELF::R_RISCV_SUB32:
+  case ELF::R_RISCV_64:
     return true;
   }
 }
 
 static size_t getSizeForTypeX86(uint64_t Type) {
   switch (Type) {
   default:
     errs() << object::getELFRelocationTypeName(ELF::EM_X86_64, Type) << '\n';
static size_t getSizeForTypeRISCV(uint64_t Type) {
   case ELF::R_RISCV_PCREL_LO12_I:
   case ELF::R_RISCV_32_PCREL:
   case ELF::R_RISCV_CALL:
   case ELF::R_RISCV_CALL_PLT:
   case ELF::R_RISCV_ADD32:
   case ELF::R_RISCV_SUB32:
     return 4;
   case ELF::R_RISCV_GOT_HI20:
+  case ELF::R_RISCV_64:
     // See extractValueRISCV for why this is necessary.
     return 8;
   }
 }
 
 static bool skipRelocationTypeX86(uint64_t Type) {
   return Type == ELF::R_X86_64_NONE;
 }
 
 static bool skipRelocationTypeAArch64(uint64_t Type) {
-  return Type == ELF::R_AARCH64_NONE || Type == ELF::R_AARCH64_LD_PREL_LO19;
+  return Type == ELF::R_AARCH64_NONE || Type == ELF::R_AARCH64_LD_PREL_LO19 ||
+         Type == ELF::R_AARCH64_TLSDESC_CALL;
 }
 
 static bool skipRelocationTypeRISCV(uint64_t Type) {
   switch (Type) {
   default:
     return false;
   case ELF::R_RISCV_NONE:
   case ELF::R_RISCV_RELAX:
static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) {
   // The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP
   switch (Type) {
   default:
     break;
   case ELF::R_AARCH64_ADR_PREL_PG_HI21:
   case ELF::R_AARCH64_ADD_ABS_LO12_NC:
   case ELF::R_AARCH64_ADR_GOT_PAGE:
   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
-    if (IsAdr(Contents))
-      return true;
+    if (IsAdr(Contents)) {
+      Type = ELF::R_AARCH64_ADR_PREL_LO21;
+      return false;
+    }
   }
 
   return false;
 }
 
 static bool skipRelocationProcessRISCV(uint64_t &Type, uint64_t Contents) {
   return false;
 }
static uint64_t extractValueAArch64(uint64_t Type, uint64_t Contents,
   case ELF::R_AARCH64_ABS64:
     return Contents;
   case ELF::R_AARCH64_PREL16:
     return static_cast<int64_t>(PC) + SignExtend64<16>(Contents & 0xffff);
   case ELF::R_AARCH64_PREL32:
     return static_cast<int64_t>(PC) + SignExtend64<32>(Contents & 0xffffffff);
   case ELF::R_AARCH64_PREL64:
     return static_cast<int64_t>(PC) + Contents;
-  case ELF::R_AARCH64_TLSDESC_CALL:
   case ELF::R_AARCH64_JUMP26:
   case ELF::R_AARCH64_CALL26:
     // Immediate goes in bits 25:0 of B and BL.
     Contents &= ~0xfffffffffc000000ULL;
     return static_cast<int64_t>(PC) + SignExtend64<28>(Contents << 2);
   case ELF::R_AARCH64_TSTBR14:
     // Immediate:15:2 goes in bits 18:5 of TBZ, TBNZ
     Contents &= ~0xfffffffffff8001fULL;
static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents,
   case ELF::R_RISCV_PCREL_LO12_I:
     return extractIImmRISCV(Contents);
   case ELF::R_RISCV_RVC_JUMP:
     return SignExtend64<11>(Contents >> 2);
   case ELF::R_RISCV_RVC_BRANCH:
     return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0));
   case ELF::R_RISCV_ADD32:
   case ELF::R_RISCV_SUB32:
+  case ELF::R_RISCV_64:
     return Contents;
   }
 }
 
 static bool isGOTX86(uint64_t Type) {
   switch (Type) {
   default:
     return false;

 }
 
 static bool isPCRelativeRISCV(uint64_t Type) {
   switch (Type) {
   default:
     llvm_unreachable("Unknown relocation type");
   case ELF::R_RISCV_ADD32:
   case ELF::R_RISCV_SUB32:
+  case ELF::R_RISCV_64:
     return false;
   case ELF::R_RISCV_JAL:
   case ELF::R_RISCV_CALL:
   case ELF::R_RISCV_CALL_PLT:
   case ELF::R_RISCV_BRANCH:
   case ELF::R_RISCV_GOT_HI20:
   case ELF::R_RISCV_PCREL_HI20:
   case ELF::R_RISCV_PCREL_LO12_I:
bool Relocation::isPCRelative(uint64_t Type) {
   if (Arch == Triple::riscv64)
     return isPCRelativeRISCV(Type);
   return isPCRelativeX86(Type);
 }
 
 uint64_t Relocation::getAbs64() {
   if (Arch == Triple::aarch64)
     return ELF::R_AARCH64_ABS64;
+  if (Arch == Triple::riscv64)
+    return ELF::R_RISCV_64;
   return ELF::R_X86_64_64;
 }
 
 uint64_t Relocation::getRelative() {
   if (Arch == Triple::aarch64)
     return ELF::R_AARCH64_RELATIVE;
   return ELF::R_X86_64_RELATIVE;
 }

bolt/lib/Passes/CMakeLists.txt

 add_llvm_library(LLVMBOLTPasses
   ADRRelaxationPass.cpp
   Aligner.cpp
   AllocCombiner.cpp
   AsmDump.cpp
   BinaryPasses.cpp
   BinaryFunctionCallGraph.cpp
   CMOVConversion.cpp
   CacheMetrics.cpp
   CallGraph.cpp
   CallGraphWalker.cpp
   DataflowAnalysis.cpp
   DataflowInfoManager.cpp
   FrameAnalysis.cpp
   FrameOptimizer.cpp
-  FixRelaxationPass.cpp
   FixRISCVCallsPass.cpp
   HFSort.cpp
   HFSortPlus.cpp
   Hugify.cpp
   IdenticalCodeFolding.cpp
   IndirectCallPromotion.cpp
   Inliner.cpp
   Instrumentation.cpp

bolt/lib/Passes/FixRelaxationPass.cpp

-#include "bolt/Passes/FixRelaxationPass.h"
-#include "bolt/Core/ParallelUtilities.h"
-
-using namespace llvm;
-
-namespace llvm {
-namespace bolt {
-
-// This function finds ADRP+ADD instruction sequences that originally before
-// linker relaxations were ADRP+LDR. We've modified LDR/ADD relocation properly
-// during relocation reading, so its targeting right symbol. As for ADRP its
-// target is wrong before this pass since we won't be able to recognize and
-// properly change R_AARCH64_ADR_GOT_PAGE relocation to
-// R_AARCH64_ADR_PREL_PG_HI21 during relocation reading. Now we're searching for
-// ADRP+ADD sequences, checking that ADRP points to the GOT-table symbol and the
-// target of ADD is another symbol. When found change ADRP symbol reference to
-// the ADDs one.
-void FixRelaxations::runOnFunction(BinaryFunction &BF) {
-  BinaryContext &BC = BF.getBinaryContext();
-  for (BinaryBasicBlock &BB : BF) {
-    for (auto II = BB.begin(); II != BB.end(); ++II) {
-      MCInst &Adrp = *II;
-      if (BC.MIB->isPseudo(Adrp) || !BC.MIB->isADRP(Adrp))
-        continue;
-
-      const MCSymbol *AdrpSymbol = BC.MIB->getTargetSymbol(Adrp);
-      if (!AdrpSymbol || AdrpSymbol->getName() != "__BOLT_got_zero")
-        continue;
-
-      auto NextII = std::next(II);
-      if (NextII == BB.end())
-        continue;
-
-      const MCInst &Add = *NextII;
-      if (!BC.MIB->matchAdrpAddPair(Adrp, Add))
-        continue;
-
-      const MCSymbol *Symbol = BC.MIB->getTargetSymbol(Add);
-      if (!Symbol || AdrpSymbol == Symbol)
-        continue;
-
-      auto L = BC.scopeLock();
-      const int64_t Addend = BC.MIB->getTargetAddend(Add);
-      BC.MIB->setOperandToSymbolRef(Adrp, /*OpNum*/ 1, Symbol, Addend,
-                                    BC.Ctx.get(), ELF::R_AARCH64_NONE);
-    }
-  }
-}
-
-void FixRelaxations::runOnFunctions(BinaryContext &BC) {
-  if (!BC.isAArch64() || !BC.HasRelocations)
-    return;
-
-  ParallelUtilities::WorkFuncTy WorkFun = [&](BinaryFunction &BF) {
-    runOnFunction(BF);
-  };
-
-  ParallelUtilities::runOnEachFunction(
-      BC, ParallelUtilities::SchedulingPolicy::SP_INST_LINEAR, WorkFun, nullptr,
-      "FixRelaxations");
-}
-
-} // namespace bolt
-} // namespace llvm

bolt/lib/Passes/LongJmp.cpp

 #define DEBUG_TYPE "longjmp"
 
 using namespace llvm;
 
 namespace opts {
 extern cl::OptionCategory BoltOptCategory;
 extern llvm::cl::opt<unsigned> AlignText;
 extern cl::opt<unsigned> AlignFunctions;
-extern cl::opt<bool> UseOldText;
+extern cl::opt<bool> Rewrite;
 extern cl::opt<bool> HotFunctionsAtEnd;
 
 static cl::opt<bool> GroupStubs("group-stubs",
                                 cl::desc("share stubs across functions"),
                                 cl::init(true), cl::cat(BoltOptCategory));
 }
 
 namespace llvm {
uint64_t LongJmpPass::tentativeLayoutRelocMode(
   for (BinaryFunction *Func : SortedFunctions)
     tentativeBBLayout(*Func);
 
   return DotAddress;
 }
 
 void LongJmpPass::tentativeLayout(
     const BinaryContext &BC, std::vector<BinaryFunction *> &SortedFunctions) {
-  uint64_t DotAddress = BC.LayoutStartAddress;
+  uint64_t DotAddress = BC.NewTextSectionAddress;
 
   if (!BC.HasRelocations) {
     for (BinaryFunction *Func : SortedFunctions) {
       HotAddresses[Func] = Func->getAddress();
       DotAddress = alignTo(DotAddress, ColdFragAlign);
       ColdAddresses[Func] = DotAddress;
       if (Func->isSplit())
         DotAddress += Func->estimateColdSize();
       tentativeBBLayout(*Func);
     }
 
     return;
   }
 
   // Relocation mode
-  uint64_t EstimatedTextSize = 0;
-  if (opts::UseOldText) {
-    EstimatedTextSize = tentativeLayoutRelocMode(BC, SortedFunctions, 0);
-
-    // Initial padding
-    if (EstimatedTextSize <= BC.OldTextSectionSize) {
-      DotAddress = BC.OldTextSectionAddress;
-      uint64_t Pad =
-          offsetToAlignment(DotAddress, llvm::Align(opts::AlignText));
-      if (Pad + EstimatedTextSize <= BC.OldTextSectionSize) {
-        DotAddress += Pad;
-      }
-    }
-  }
+  if (opts::Rewrite) {
 
-  if (!EstimatedTextSize || EstimatedTextSize > BC.OldTextSectionSize)
-    DotAddress = alignTo(BC.LayoutStartAddress, opts::AlignText);
+    DotAddress = alignTo(BC.OldTextSectionAddress, opts::AlignText);
+    auto PLTSec = BC.getUniqueSectionByName(".plt");
 
+    if (PLTSec) {
+      // PLT Section is always put before .text when we rewrite.
+      // If we don't do that, we won't be able to estimate PLT position
+      // relative to .text, which means we won't be able to insert stubs
+      // for PLT calls properly. Also, having PLT just before .text ensures
+      // that we have minimal amount of stubs inserted in hot text,
+      // unless -hot-functions-at-end is used.
+      // If PLT was after text previously, move estimated text address forward
+      // by it's size with alignment. The real text address will likely be
+      // different after linking, but it doesn't matter for us because we only
+      // care about relative positions in the executable segment.
+      if (PLTSec->getAddress() > BC.OldTextSectionAddress)
+        DotAddress = alignTo(BC.OldTextSectionAddress + PLTSec->getSize(),
+                             opts::AlignText);
+
+      // alignTo(PLTSec->getSize(), opts::AlignText) is the most
+      // conservative estimation for distance between start of PLT and start of
+      // text. It cannot be more far away than that, so it should work for stub
+      // insertion.
+      TentativePLTAddress =
+          DotAddress - alignTo(PLTSec->getSize(), opts::AlignText);
+    }
+  }
+  assert(DotAddress && "No tentative text address!");
   tentativeLayoutRelocMode(BC, SortedFunctions, DotAddress);
 }
 
 bool LongJmpPass::usesStub(const BinaryFunction &Func,
                            const MCInst &Inst) const {
   const MCSymbol *TgtSym = Func.getBinaryContext().MIB->getTargetSymbol(Inst);
   const BinaryBasicBlock *TgtBB = Func.getBasicBlockForLabel(TgtSym);
   auto Iter = Stubs.find(&Func);
   if (Iter != Stubs.end())
     return Iter->second.count(TgtBB);
   return false;
 }
 
 uint64_t LongJmpPass::getSymbolAddress(const BinaryContext &BC,
                                        const MCSymbol *Target,
                                        const BinaryBasicBlock *TgtBB) const {
   if (TgtBB) {
     auto Iter = BBAddresses.find(TgtBB);
     assert(Iter != BBAddresses.end() && "Unrecognized BB");
     return Iter->second;
   }
   uint64_t EntryID = 0;
   const BinaryFunction *TargetFunc = BC.getFunctionForSymbol(Target, &EntryID);
+  if (opts::Rewrite && TargetFunc->isPLTFunction()) {
+    uint64_t Offset =
+        TargetFunc->getAddress() - TargetFunc->getOriginSection()->getAddress();
+    assert(TentativePLTAddress && "No PLT address!");
+    return TentativePLTAddress + Offset;
+  }
+
   auto Iter = HotAddresses.find(TargetFunc);
   if (Iter == HotAddresses.end() || (TargetFunc && EntryID)) {
     // Look at BinaryContext's resolution for this symbol - this is a symbol not
     // mapped to a BinaryFunction
     ErrorOr<uint64_t> ValueOrError = BC.getSymbolValue(*Target);
     assert(ValueOrError && "Unrecognized symbol");
     return *ValueOrError;
   }
void LongJmpPass::runOnFunctions(BinaryContext &BC) {
   bool Modified;
   uint32_t Iterations = 0;
   do {
     ++Iterations;
     Modified = false;
     tentativeLayout(BC, Sorted);
     updateStubGroups();
     for (BinaryFunction *Func : Sorted) {
+      if (Func->isPLTFunction())
+        continue;
       if (relax(*Func)) {
         // Don't ruin non-simple functions, they can't afford to have the layout
         // changed.
         if (Func->isSimple())
           Func->fixBranches();
         Modified = true;
       }
     }
   } while (Modified);
   outs() << "BOLT-INFO: Inserted " << NumHotStubs
          << " stubs in the hot area and " << NumColdStubs
          << " stubs in the cold area. Shared " << NumSharedStubs
          << " times, iterated " << Iterations << " times.\n";
 }
 } // namespace bolt
 } // namespace llvm

bolt/lib/Passes/ReorderData.cpp

if (!opts::ReorderInplace || FoundUnmoveable) {
       if (opts::ReorderInplace && FoundUnmoveable)
         outs() << "BOLT-INFO: Found unmoveable symbols in "
                << Section->getName() << " falling back to splitting "
                << "instead of in-place reordering.\n";
 
       // Rename sections.
       BinarySection &Hot =
           BC.registerSection(Section->getName() + ".hot", *Section);
-      Hot.setOutputName(Section->getName());
-      Section->setOutputName(".bolt.org" + Section->getName());
-
       // Reorder contents of original section.
       setSectionOrder(BC, Hot, Order.begin(), SplitPoint);
 
       // This keeps the original data from thinking it has been moved.
       for (std::pair<const uint64_t, BinaryData *> &Entry :
            BC.getBinaryDataForSection(*Section)) {
         if (!Entry.second->isMoved()) {
           Entry.second->setSection(*Section);

bolt/lib/Passes/ReorderFunctions.cpp

for (const NodeId FuncId : Cluster.targets()) {
       FuncAddr[FuncId] = TotalSize;
       TotalSize += Cg.size(FuncId);
     }
   }
 
   // Assign valid index for functions with valid profile.
   for (auto &It : BFs) {
     BinaryFunction &BF = It.second;
-    if (!BF.hasValidIndex() && BF.hasValidProfile())
+    if (!BF.hasValidIndex() && BF.hasValidProfile() && !BF.isPseudo())
       BF.setIndex(Index++);
   }
 
   if (opts::ReorderFunctions == RT_NONE)
     return;
 
   printStats(Clusters, FuncAddr);
 }

 void ReorderFunctions::runOnFunctions(BinaryContext &BC) {
   auto &BFs = BC.getBinaryFunctions();
   if (opts::ReorderFunctions != RT_NONE &&
       opts::ReorderFunctions != RT_EXEC_COUNT &&
       opts::ReorderFunctions != RT_USER) {
     Cg = buildCallGraph(
         BC,
         [](const BinaryFunction &BF) {
-          if (!BF.hasProfile())
+          if (!BF.hasProfile() || BF.isPseudo())
             return true;
           if (BF.getState() != BinaryFunction::State::CFG)
             return true;
           return false;
         },
         opts::CgFromPerfData,
         /*IncludeSplitCalls=*/false, opts::ReorderFunctionsUseHotSize,
         opts::CgUseSplitHotSize, opts::UseEdgeCounts,
llvm::stable_sort(SortedFunctions,
                         if (!A->hasProfile())
                           return false;
                         if (!B->hasProfile())
                           return true;
                         return A->getExecutionCount() > B->getExecutionCount();
                       });
     uint32_t Index = 0;
     for (BinaryFunction *BF : SortedFunctions)
-      if (BF->hasProfile()) {
+      if (BF->hasProfile() || !BF->isPseudo()) {
         BF->setIndex(Index++);
         LLVM_DEBUG(if (opts::Verbosity > 1) {
           dbgs() << "BOLT-INFO: hot func " << BF->getPrintName() << " ("
                  << BF->getExecutionCount() << ")\n";
         });
       }
   } break;
   case RT_HFSORT:
for (const std::string &Function : readFunctionOrderFile()) {
         BinaryFunction *BF = BC.getFunctionForSymbol(FuncBD->getSymbol());
         if (!BF) {
           if (opts::Verbosity >= 1)
             errs() << "BOLT-WARNING: Reorder functions: can't find function "
                    << "for " << Function << "\n";
           ++InvalidEntries;
           break;
         }
-        if (!BF->hasValidIndex())
+        if (!BF->hasValidIndex() && !BF->isPseudo())
           BF->setIndex(Index++);
         else if (opts::Verbosity > 0)
           errs() << "BOLT-WARNING: Duplicate reorder entry for " << Function
                  << "\n";
       }
     }
     if (InvalidEntries)
       errs() << "BOLT-WARNING: Reorder functions: can't find functions for "

bolt/lib/Profile/DataAggregator.cpp

std::error_code DataAggregator::parseMMapEvents() {
   }
 
   auto Range = GlobalMMapInfo.equal_range(NameToUse);
   for (MMapInfo &MMapInfo : llvm::make_second_range(make_range(Range))) {
     if (BC->HasFixedLoadAddress && MMapInfo.MMapAddress) {
       // Check that the binary mapping matches one of the segments.
       bool MatchFound = llvm::any_of(
           llvm::make_second_range(BC->SegmentMapInfo),
-          [&](SegmentInfo &SegInfo) {
+          [&](ProgramHeader &SegInfo) {
             // The mapping is page-aligned and hence the MMapAddress could be
             // different from the segment start address. We cannot know the page
             // size of the mapping, but we know it should not exceed the segment
             // alignment value. Hence we are performing an approximate check.
-            return SegInfo.Address >= MMapInfo.MMapAddress &&
-                   SegInfo.Address - MMapInfo.MMapAddress < SegInfo.Alignment;
+            return SegInfo.p_vaddr >= MMapInfo.MMapAddress &&
+                   SegInfo.p_vaddr - MMapInfo.MMapAddress < SegInfo.p_align;
           });
       if (!MatchFound) {
         errs() << "PERF2BOLT-WARNING: ignoring mapping of " << NameToUse
                << " at 0x" << Twine::utohexstr(MMapInfo.MMapAddress) << '\n';
         continue;
       }
     }
 

bolt/lib/Rewrite/BinaryPassManager.cpp

 //===- bolt/Rewrite/BinaryPassManager.cpp - Binary-level pass manager -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "bolt/Rewrite/BinaryPassManager.h"
 #include "bolt/Passes/ADRRelaxationPass.h"
 #include "bolt/Passes/Aligner.h"
 #include "bolt/Passes/AllocCombiner.h"
 #include "bolt/Passes/AsmDump.h"
 #include "bolt/Passes/CMOVConversion.h"
 #include "bolt/Passes/FixRISCVCallsPass.h"
-#include "bolt/Passes/FixRelaxationPass.h"
 #include "bolt/Passes/FrameOptimizer.h"
 #include "bolt/Passes/Hugify.h"
 #include "bolt/Passes/IdenticalCodeFolding.h"
 #include "bolt/Passes/IndirectCallPromotion.h"
 #include "bolt/Passes/Inliner.h"
 #include "bolt/Passes/Instrumentation.h"
 #include "bolt/Passes/JTFootprintReduction.h"
 #include "bolt/Passes/LongJmp.h"
static cl::opt<bool>
     PrintSplit("print-split", cl::desc("print functions after code splitting"),
                cl::Hidden, cl::cat(BoltOptCategory));
 
 static cl::opt<bool>
     PrintStoke("print-stoke", cl::desc("print functions after stoke analysis"),
                cl::cat(BoltOptCategory));
 
 static cl::opt<bool>
-    PrintFixRelaxations("print-fix-relaxations",
-                        cl::desc("print functions after fix relaxations pass"),
-                        cl::cat(BoltOptCategory));
-
-static cl::opt<bool>
     PrintFixRISCVCalls("print-fix-riscv-calls",
                        cl::desc("print functions after fix RISCV calls pass"),
                        cl::cat(BoltOptCategory));
 
 static cl::opt<bool> PrintVeneerElimination(
     "print-veneer-elimination",
     cl::desc("print functions after veneer elimination pass"),
     cl::cat(BoltOptCategory));
void BinaryFunctionPassManager::runAllPasses(BinaryContext &BC) {
 
   const DynoStats InitialDynoStats =
       getDynoStats(BC.getBinaryFunctions(), BC.isAArch64());
 
   Manager.registerPass(std::make_unique<AsmDumpPass>(),
                        opts::AsmDump.getNumOccurrences());
 
   if (BC.isAArch64()) {
-    Manager.registerPass(std::make_unique<FixRelaxations>(PrintFixRelaxations));
-
     Manager.registerPass(
         std::make_unique<VeneerElimination>(PrintVeneerElimination));
   }
 
   if (BC.isRISCV()) {
     Manager.registerPass(
         std::make_unique<FixRISCVCallsPass>(PrintFixRISCVCalls));
   }
void BinaryFunctionPassManager::runAllPasses(BinaryContext &BC) {
 
   Manager.registerPass(
       std::make_unique<RetpolineInsertion>(PrintRetpolineInsertion));
 
   // Assign each function an output section.
   Manager.registerPass(std::make_unique<AssignSections>());
 
   // Patch original function entries
-  if (BC.HasRelocations)
+  if (BC.HasRelocations && !opts::Rewrite)
     Manager.registerPass(std::make_unique<PatchEntries>());
 
   // This pass turns tail calls into jumps which makes them invisible to
   // function reordering. It's unsafe to use any CFG or instruction analysis
   // after this point.
   Manager.registerPass(
       std::make_unique<InstructionLowering>(PrintAfterLowering));
 

bolt/lib/Rewrite/ExecutableFileMemoryManager.cpp

if (BC.isELF()) {
               SectionName == "__fini" || SectionName == "__setup" ||
               SectionName == "__cstring" || SectionName == "__literal16") &&
              "Unexpected section in the instrumentation library");
       // Sections coming from the instrumentation runtime are prefixed with "I".
       SectionName = ("I" + Twine(SectionName)).toStringRef(Buf);
     }
   }
 
-  BinarySection *Section = nullptr;
-  if (!OrgSecPrefix.empty() && SectionName.startswith(OrgSecPrefix)) {
-    // Update the original section contents.
-    ErrorOr<BinarySection &> OrgSection =
-        BC.getUniqueSectionByName(SectionName.substr(OrgSecPrefix.length()));
-    assert(OrgSection && OrgSection->isAllocatable() &&
-           "Original section must exist and be allocatable.");
-
-    Section = &OrgSection.get();
-    Section->updateContents(Contents, Size);
-  } else {
-    // If the input contains a section with the section name, rename it in the
-    // output file to avoid the section name conflict and emit the new section
-    // under a unique internal name.
-    ErrorOr<BinarySection &> OrgSection =
-        BC.getUniqueSectionByName(SectionName);
-    bool UsePrefix = false;
-    if (OrgSection && OrgSection->hasSectionRef()) {
-      OrgSection->setOutputName(OrgSecPrefix + SectionName);
-      UsePrefix = true;
-    }
-
-    // Register the new section under a unique name to avoid name collision with
-    // sections in the input file.
-    BinarySection &NewSection = BC.registerOrUpdateSection(
-        UsePrefix ? NewSecPrefix + SectionName : SectionName, ELF::SHT_PROGBITS,
-        BinarySection::getFlags(IsReadOnly, IsCode, true), Contents, Size,
-        Alignment);
-    if (UsePrefix)
-      NewSection.setOutputName(SectionName);
-    Section = &NewSection;
-  }
+  BinarySection *Section = &BC.registerOrUpdateSection(
+      SectionName, ELF::SHT_PROGBITS,
+      BinarySection::getFlags(IsReadOnly, IsCode, true), Contents, Size, Alignment);
+  assert(Section->isAllocatable() &&
+         "verify that allocatable is marked as allocatable");
 
   LLVM_DEBUG({
     dbgs() << "BOLT: allocating "
            << (IsCode ? "code" : (IsReadOnly ? "read-only data" : "data"))
            << " section : " << Section->getOutputName() << " ("
            << Section->getName() << ")"
            << " with size " << Size << ", alignment " << Alignment << " at "
            << Contents << ", ID = " << SectionID << "\n";

bolt/lib/Rewrite/JITLinkLinker.cpp

struct JITLinkLinker::Context : jitlink::JITLinkContext {
   lookup(const LookupMap &Symbols,
          std::unique_ptr<jitlink::JITLinkAsyncLookupContinuation> LC) override {
     jitlink::AsyncLookupResult AllResults;
 
     for (const auto &Symbol : Symbols) {
       std::string SymName = Symbol.first.str();
       LLVM_DEBUG(dbgs() << "BOLT: looking for " << SymName << "\n");
 
+      if (auto BSecIt = Linker.BC.EndSymbols.find(SymName);
+          BSecIt != Linker.BC.EndSymbols.end()) {
+        BinarySection *BSec = BSecIt->second;
+        assert(BSec->getOutputAddress() && "Unmapped section!");
+        uint64_t Address = BSec->getOutputEndAddress();
+        AllResults[Symbol.first] = orc::ExecutorSymbolDef(
+            orc::ExecutorAddr(Address), JITSymbolFlags());
+        LLVM_DEBUG(
+            dbgs() << formatv("Resolved {0} as the end of {1} at {2:x}\n",
+                              SymName, BSec->getOutputName(), Address););
+        continue;
+      }
+
       if (auto Address = Linker.lookupSymbol(SymName)) {
         LLVM_DEBUG(dbgs() << "Resolved to address 0x"
                           << Twine::utohexstr(*Address) << "\n");
         AllResults[Symbol.first] = orc::ExecutorSymbolDef(
             orc::ExecutorAddr(*Address), JITSymbolFlags());
         continue;
       }
 

bolt/lib/Rewrite/MachORewriteInstance.cpp

std::unique_ptr<object::ObjectFile> Obj = cantFail(
       object::ObjectFile::createObjectFile(ObjectMemBuffer->getMemBufferRef()),
       "error creating in-memory object");
   assert(Obj && "createObjectFile cannot return nullptr");
 
   MCAsmLayout FinalLayout(
       static_cast<MCObjectStreamer *>(Streamer.get())->getAssembler());
 
   auto EFMM = std::make_unique<ExecutableFileMemoryManager>(*BC);
-  EFMM->setNewSecPrefix(getNewSecPrefix());
-  EFMM->setOrgSecPrefix(getOrgSecPrefix());
 
   Linker = std::make_unique<JITLinkLinker>(*BC, std::move(EFMM));
   Linker->loadObject(ObjectMemBuffer->getMemBufferRef(),
                      [this](auto MapSection) {
                        // Assign addresses to all sections. If key corresponds
                        // to the object created by ourselves, call our regular
                        // mapping function. If we are loading additional objects
                        // as part of runtime libraries for instrumentation,

bolt/lib/Rewrite/RewriteInstance.cpp

 //===- bolt/Rewrite/RewriteInstance.cpp - ELF rewriter --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "bolt/Rewrite/RewriteInstance.h"
 #include "bolt/Core/BinaryContext.h"
 #include "bolt/Core/BinaryEmitter.h"
 #include "bolt/Core/BinaryFunction.h"
+#include "bolt/Core/BinarySection.h"
 #include "bolt/Core/DebugData.h"
 #include "bolt/Core/Exceptions.h"
 #include "bolt/Core/FunctionLayout.h"
 #include "bolt/Core/MCPlusBuilder.h"
 #include "bolt/Core/ParallelUtilities.h"
 #include "bolt/Core/Relocation.h"
 #include "bolt/Passes/CacheMetrics.h"
 #include "bolt/Passes/ReorderFunctions.h"
 #include "bolt/Profile/BoltAddressTranslation.h"
 #include "bolt/Profile/DataAggregator.h"
 #include "bolt/Profile/DataReader.h"
 #include "bolt/Profile/YAMLProfileReader.h"
 #include "bolt/Profile/YAMLProfileWriter.h"
 #include "bolt/Rewrite/BinaryPassManager.h"
 #include "bolt/Rewrite/DWARFRewriter.h"
 #include "bolt/Rewrite/ExecutableFileMemoryManager.h"
 #include "bolt/Rewrite/JITLinkLinker.h"
 #include "bolt/Rewrite/MetadataRewriters.h"
 #include "bolt/RuntimeLibs/HugifyRuntimeLibrary.h"
 #include "bolt/RuntimeLibs/InstrumentationRuntimeLibrary.h"
 #include "bolt/Utils/CommandLineOpts.h"
 #include "bolt/Utils/Utils.h"
 #include "llvm/ADT/AddressRanges.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/DebugInfo/DWARF/DWARFContext.h"
 #include "llvm/DebugInfo/DWARF/DWARFDebugFrame.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCAsmLayout.h"
 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
 #include "llvm/MC/MCObjectStreamer.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/Alignment.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/DataExtractor.h"
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/ManagedStatic.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/Regex.h"
 #include "llvm/Support/Timer.h"
 #include "llvm/Support/ToolOutputFile.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
+#include <cstdint>
 #include <fstream>
 #include <memory>
 #include <optional>
 #include <system_error>
 
 #undef  DEBUG_TYPE
 #define DEBUG_TYPE "bolt"
 
TrapOldCode("trap-old-code",
   cl::cat(BoltCategory));
 
 static cl::opt<std::string> DWPPathName("dwp",
                                         cl::desc("Path and name to DWP file."),
                                         cl::Hidden, cl::init(""),
                                         cl::cat(BoltCategory));
 
 static cl::opt<bool>
     UseGnuStack("use-gnu-stack",
-  cl::desc("use GNU_STACK program header for new segment (workaround for "
+                cl::desc("deprecated and not supported anymore: use GNU_STACK "
+                         "program header for new segment (workaround for "
                          "issues with strip/objcopy)"),
-  cl::ZeroOrMore,
-  cl::cat(BoltCategory));
+                cl::ZeroOrMore, cl::cat(BoltCategory),
+                cl::callback([](const bool &Option) {
+                  errs() << "BOLT-WARNING: use-gnu-stack is deprecated, please "
+                            "use -rewrite to "
+                            "avoid stripping issues\n";
+                }));
 
 static cl::opt<bool>
     TimeRewrite("time-rewrite",
                 cl::desc("print time spent in rewriting passes"), cl::Hidden,
                 cl::cat(BoltCategory));
 
 static cl::opt<bool>
 SequentialDisassembly("sequential-disassembly",
Error RewriteInstance::discoverStorage() {
   NamedRegionTimer T("discoverStorage", "discover storage", TimerGroupName,
                      TimerGroupDesc, opts::TimeRewrite);
 
   auto ELF64LEFile = cast<ELF64LEObjectFile>(InputFile);
   const ELFFile<ELF64LE> &Obj = ELF64LEFile->getELFFile();
 
   BC->StartFunctionAddress = Obj.getHeader().e_entry;
 
-  NextAvailableAddress = 0;
-  uint64_t NextAvailableOffset = 0;
   Expected<ELF64LE::PhdrRange> PHsOrErr = Obj.program_headers();
   if (Error E = PHsOrErr.takeError())
     return E;
 
   ELF64LE::PhdrRange PHs = PHsOrErr.get();
+  unsigned Phnum = PHs.end() - PHs.begin();
+  uint64_t FirstAllocOffset = ~0ULL;
+  uint64_t EndOfLoadablePartOffset = 0;
   for (const ELF64LE::Phdr &Phdr : PHs) {
     switch (Phdr.p_type) {
     case ELF::PT_LOAD:
       BC->FirstAllocAddress = std::min(BC->FirstAllocAddress,
                                        static_cast<uint64_t>(Phdr.p_vaddr));
-      NextAvailableAddress = std::max(NextAvailableAddress,
-                                      Phdr.p_vaddr + Phdr.p_memsz);
-      NextAvailableOffset = std::max(NextAvailableOffset,
-                                     Phdr.p_offset + Phdr.p_filesz);
-
-      BC->SegmentMapInfo[Phdr.p_vaddr] = SegmentInfo{Phdr.p_vaddr,
-                                                     Phdr.p_memsz,
-                                                     Phdr.p_offset,
-                                                     Phdr.p_filesz,
-                                                     Phdr.p_align};
+      FirstAllocOffset =
+          std::min(FirstAllocOffset, static_cast<uint64_t>(Phdr.p_offset));
+      BC->InputAddressSpaceEnd =
+          std::max(BC->InputAddressSpaceEnd,
+                   alignTo(Phdr.p_vaddr + Phdr.p_memsz, BC->PageAlign));
+      EndOfLoadablePartOffset =
+          std::max(EndOfLoadablePartOffset,
+                   alignTo(Phdr.p_offset + Phdr.p_memsz, BC->PageAlign));
+      BC->SegmentMapInfo[Phdr.p_vaddr] = ProgramHeader(Phdr);
+      if (Phdr.p_flags == ELF::PF_R)
+        HasReadOnlySegment = true;
       break;
     case ELF::PT_INTERP:
       BC->HasInterpHeader = true;
       break;
+    case ELF::PT_PHDR:
+      HasProgramHeaderSegment = true;
+      break;
     }
+    BC->InputSegments.push_back(Phdr);
   }
 
+  // Address of a first byte in a first segment (usually beginning of a file)
+  BaseAddress = BC->FirstAllocAddress - FirstAllocOffset;
   for (const SectionRef &Section : InputFile->sections()) {
     Expected<StringRef> SectionNameOrErr = Section.getName();
     if (Error E = SectionNameOrErr.takeError())
       return E;
     StringRef SectionName = SectionNameOrErr.get();
     if (SectionName == ".text") {
       BC->OldTextSectionAddress = Section.getAddress();
-      BC->OldTextSectionSize = Section.getSize();
-
-      Expected<StringRef> SectionContentsOrErr = Section.getContents();
-      if (Error E = SectionContentsOrErr.takeError())
-        return E;
-      StringRef SectionContents = SectionContentsOrErr.get();
-      BC->OldTextSectionOffset =
-          SectionContents.data() - InputFile->getData().data();
     }
 
     if (!opts::HeatmapMode &&
         !(opts::AggregateOnly && BAT->enabledFor(InputFile)) &&
         (SectionName.startswith(getOrgSecPrefix()) ||
          SectionName == getBOLTTextSectionName()))
       return createStringError(
           errc::function_not_supported,
           "BOLT-ERROR: input file was processed by BOLT. Cannot re-optimize");
   }
 
-  if (!NextAvailableAddress || !NextAvailableOffset)
-    return createStringError(errc::executable_format_error,
-                             "no PT_LOAD pheader seen");
-
   outs() << "BOLT-INFO: first alloc address is 0x"
          << Twine::utohexstr(BC->FirstAllocAddress) << '\n';
 
-  FirstNonAllocatableOffset = NextAvailableOffset;
-
-  NextAvailableAddress = alignTo(NextAvailableAddress, BC->PageAlign);
-  NextAvailableOffset = alignTo(NextAvailableOffset, BC->PageAlign);
-
-  // Hugify: Additional huge page from left side due to
-  // weird ASLR mapping addresses (4KB aligned)
-  if (opts::Hugify && !BC->HasFixedLoadAddress)
-    NextAvailableAddress += BC->PageAlign;
-
-  if (!opts::UseGnuStack) {
-    // This is where the black magic happens. Creating PHDR table in a segment
-    // other than that containing ELF header is tricky. Some loaders and/or
-    // parts of loaders will apply e_phoff from ELF header assuming both are in
-    // the same segment, while others will do the proper calculation.
-    // We create the new PHDR table in such a way that both of the methods
-    // of loading and locating the table work. There's a slight file size
-    // overhead because of that.
-    //
-    // NB: bfd's strip command cannot do the above and will corrupt the
-    //     binary during the process of stripping non-allocatable sections.
+  if (!opts::Rewrite && !opts::UseOldText) {
+    // when not rewriting, compute the new text section and segment addresses in
+    // advance. Needed for LongJMP.
+    FirstNonAllocatableOffset = EndOfLoadablePartOffset;
+    uint64_t NextAvailableOffset = EndOfLoadablePartOffset;
+    NextAvailableAddress = BC->InputAddressSpaceEnd;
     if (NextAvailableOffset <= NextAvailableAddress - BC->FirstAllocAddress)
       NextAvailableOffset = NextAvailableAddress - BC->FirstAllocAddress;
     else
       NextAvailableAddress = NextAvailableOffset + BC->FirstAllocAddress;
 
     assert(NextAvailableOffset ==
                NextAvailableAddress - BC->FirstAllocAddress &&
            "PHDR table address calculation error");
 
-    outs() << "BOLT-INFO: creating new program header table at address 0x"
-           << Twine::utohexstr(NextAvailableAddress) << ", offset 0x"
-           << Twine::utohexstr(NextAvailableOffset) << '\n';
+    BC->OutputAddressToOffsetMap[NextAvailableAddress] = NextAvailableOffset;
+
+    unsigned MaxPhnum = Phnum + !HasProgramHeaderSegment + 2;
+
+    BC->MaxPHDRSize = MaxPhnum * sizeof(ELF64LE::Phdr);
 
     PHDRTableAddress = NextAvailableAddress;
     PHDRTableOffset = NextAvailableOffset;
+    NextAvailableAddress += BC->MaxPHDRSize;
+    NextAvailableOffset += BC->MaxPHDRSize;
 
-    // Reserve space for 3 extra pheaders.
-    unsigned Phnum = Obj.getHeader().e_phnum;
-    Phnum += 3;
-
-    NextAvailableAddress += Phnum * sizeof(ELF64LEPhdrTy);
-    NextAvailableOffset += Phnum * sizeof(ELF64LEPhdrTy);
+    NextAvailableAddress = alignTo(
+        NextAvailableAddress, std::max(opts::AlignText, opts::AlignFunctions));
+    BC->NewTextSectionAddress = NextAvailableAddress;
+    outs() << "BOLT-INFO: creating new program header table at address 0x"
+           << Twine::utohexstr(PHDRTableAddress) << ", offset 0x"
+           << Twine::utohexstr(PHDRTableOffset) << '\n';
   }
-
-  // Align at cache line.
-  NextAvailableAddress = alignTo(NextAvailableAddress, 64);
-  NextAvailableOffset = alignTo(NextAvailableOffset, 64);
-
-  NewTextSegmentAddress = NextAvailableAddress;
-  NewTextSegmentOffset = NextAvailableOffset;
-  BC->LayoutStartAddress = NextAvailableAddress;
-
   // Tools such as objcopy can strip section contents but leave header
   // entries. Check that at least .text is mapped in the file.
   if (!getFileOffsetForAddress(BC->OldTextSectionAddress))
     return createStringError(errc::executable_format_error,
                              "BOLT-ERROR: input binary is not a valid ELF "
                              "executable as its text section is not "
                              "mapped to a valid segment");
   return Error::success();
void RewriteInstance::patchBuildID() {
   raw_fd_ostream &OS = Out->os();
 
   if (BuildID.empty())
     return;
 
   size_t IDOffset = BuildIDSection->getContents().rfind(BuildID);
   assert(IDOffset != StringRef::npos && "failed to patch build-id");
 
-  uint64_t FileOffset = getFileOffsetForAddress(BuildIDSection->getAddress());
+  uint64_t FileOffset =
+      getOutputFileOffsetForAddress(BuildIDSection->getOutputAddress());
   if (!FileOffset) {
     errs() << "BOLT-WARNING: Non-allocatable build-id will not be updated.\n";
     return;
   }
 
   char LastIDByte = BuildID[BuildID.size() - 1];
   LastIDByte ^= 1;
   OS.pwrite(&LastIDByte, 1, FileOffset + IDOffset + BuildID.size() - 1);
Error RewriteInstance::run() {
   outs() << "BOLT-INFO: BOLT version: " << BoltRevision << "\n";
 
   if (Error E = discoverStorage())
     return E;
   if (Error E = readSpecialSections())
     return E;
   adjustCommandLineOptions();
   discoverFileObjects();
-
   preprocessProfileData();
 
   // Skip disassembling if we have a translation table and we are running an
   // aggregation job.
   if (opts::AggregateOnly && BAT->enabledFor(InputFile)) {
     processProfileData();
     return Error::success();
   }
Error RewriteInstance::run() {
 
   postProcessFunctions();
 
   processMetadataPostCFG();
 
   if (opts::DiffOnly)
     return Error::success();
 
-  preregisterSections();
+  renameAndPreregisterSections();
 
   runOptimizationPasses();
 
   emitAndLink();
 
   updateMetadata();
 
   if (opts::LinuxKernelMode) {
auto registerName = [&](uint64_t FinalSize) {
                                 SymbolFlags);
       if (!AlternativeName.empty())
         BC->registerNameAtAddress(AlternativeName, Address, FinalSize,
                                   SymbolAlignment, SymbolFlags);
     };
 
     section_iterator Section =
         cantFail(Symbol.getSection(), "cannot get symbol section");
-    if (Section == InputFile->section_end()) {
+    if (Section == InputFile->section_end() || !Section->getName()) {
       // Could be an absolute symbol. Used on RISC-V for __global_pointer$ so we
       // need to record it to handle relocations against it. For other instances
       // of absolute symbols, we record for pretty printing.
       LLVM_DEBUG(if (opts::Verbosity > 1) {
         dbgs() << "BOLT-INFO: absolute sym " << UniqueName << "\n";
       });
       registerName(SymbolSize);
       continue;
     }
 
     LLVM_DEBUG(dbgs() << "BOLT-DEBUG: considering symbol " << UniqueName
                       << " for function\n");
 
-    if (Address == Section->getAddress() + Section->getSize()) {
+    if (SymbolType != SymbolRef::ST_Debug &&
+        Address == Section->getAddress() + Section->getSize()) {
       assert(SymbolSize == 0 &&
-             "unexpect non-zero sized symbol at end of section");
+             "unexpected non-zero sized symbol at end of section");
+
+      if (auto BSec =
+              BC->getUniqueSectionByName(cantFail(Section->getName()))) {
+        // we don't register name because it can collide with data from the next
+        // section on the same address. We'll instead create local MCSymbols
+        // when we encounter relocations against such symbols
+        BC->EndSymbols[Name] = &*BSec;
+        LLVM_DEBUG(dbgs() << formatv("BOLT-INFO: {0} is in the end of {1}\n",
+                                     Name, BSec->getName()));
+      } else {
         LLVM_DEBUG(
             dbgs()
-          << "BOLT-DEBUG: rejecting as symbol points to end of its section\n");
-      registerName(SymbolSize);
+            << "BOLT-INFO: rejecting as symbol points to end of its section\n");
+      }
       continue;
     }
 
     if (!Section->isText()) {
       assert(SymbolType != SymbolRef::ST_Function &&
              "unexpected function inside non-code section");
       LLVM_DEBUG(dbgs() << "BOLT-DEBUG: rejecting as symbol is not in code\n");
       registerName(SymbolSize);
for (const BinarySection &Section : BC->allocatableSections()) {
           BF->markIslandDynamicRelocationAtAddress(RelAddress);
         }
       }
     }
   }
 
   if (!opts::LinuxKernelMode) {
     // Read all relocations now that we have binary functions mapped.
+    createGOTPLTRelocations();
     processRelocations();
   }
 
   registerFragments();
 }
 
 void RewriteInstance::registerFragments() {
   if (!BC->HasSplitFunctions)
for (auto &BFI : BC->getBinaryFunctions()) {
     if (!ParentsFound) {
       errs() << "BOLT-ERROR: parent function not found for " << Function
              << '\n';
       exit(1);
     }
   }
 }
 
-void RewriteInstance::createPLTBinaryFunction(uint64_t TargetAddress,
+BinaryFunction *RewriteInstance::createPLTBinaryFunction(uint64_t TargetAddress,
                                                          uint64_t EntryAddress,
                                                          uint64_t EntrySize) {
   if (!TargetAddress)
-    return;
+    return nullptr;
 
   auto setPLTSymbol = [&](BinaryFunction *BF, StringRef Name) {
     const unsigned PtrSize = BC->AsmInfo->getCodePointerSize();
     MCSymbol *TargetSymbol = BC->registerNameAtAddress(
         Name.str() + "@GOT", TargetAddress, PtrSize, PtrSize);
     BF->setPLTSymbol(TargetSymbol);
+    BF->setPseudo(true);
+    BF->setIgnored();
   };
 
   BinaryFunction *BF = BC->getBinaryFunctionAtAddress(EntryAddress);
   if (BF && BC->isAArch64()) {
     // Handle IFUNC trampoline
     setPLTSymbol(BF, BF->getOneName());
-    return;
+    return BF;
   }
 
+  MCSymbol *Symbol = [&]() -> MCSymbol * {
     const Relocation *Rel = BC->getDynamicRelocationAt(TargetAddress);
-  if (!Rel || !Rel->Symbol)
-    return;
+    if (Rel && Rel->Symbol)
+      return Rel->Symbol;
+    if (auto Addr =
+            BC->getUnsignedValueAtAddress(TargetAddress, sizeof(uint64_t))) {
+      if (auto *Data = BC->getBinaryDataAtAddress(*Addr))
+        return Data->getSymbol();
+    }
+    return nullptr;
+  }();
 
   ErrorOr<BinarySection &> Section = BC->getSectionForAddress(EntryAddress);
   assert(Section && "cannot get section for address");
+  if (!Symbol) {
+    assert(EntryAddress == Section->getAddress() &&
+           "Unknown PLT entry after PLT header");
     if (!BF)
-    BF = BC->createBinaryFunction(Rel->Symbol->getName().str() + "@PLT",
+      BF = BC->createBinaryFunction("__BOLT_PSEUDO_" + Section->getName().str(),
                                     *Section, EntryAddress, 0, EntrySize,
                                     Section->getAlignment());
+    BF->setPseudo(true);
+    BF->setIgnored();
+    BF->setPLTSymbol(BC->getOrCreateGlobalSymbol(TargetAddress, "DATAat"));
+    return BF;
+  }
+  if (!BF)
+    BF = BC->createBinaryFunction(Symbol->getName().str() + "@PLT", *Section,
+                                  EntryAddress, 0, EntrySize,
+                                  Section->getAlignment());
   else
-    BF->addAlternativeName(Rel->Symbol->getName().str() + "@PLT");
-  setPLTSymbol(BF, Rel->Symbol->getName());
+    BF->addAlternativeName(Symbol->getName().str() + "@PLT");
+  setPLTSymbol(BF, Symbol->getName());
+  return BF;
 }
 
 void RewriteInstance::disassemblePLTSectionAArch64(BinarySection &Section) {
   const uint64_t SectionAddress = Section.getAddress();
   const uint64_t SectionSize = Section.getSize();
   StringRef PLTContents = Section.getContents();
   ArrayRef<uint8_t> PLTData(
       reinterpret_cast<const uint8_t *>(PLTContents.data()), SectionSize);
while (InstrOffset < SectionSize) {
     MCInst Instruction;
     uint64_t EntryOffset = InstrOffset;
     uint64_t EntrySize = 0;
     uint64_t InstrSize;
     // Loop through entry instructions
     while (InstrOffset < SectionSize) {
       disassembleInstruction(InstrOffset, Instruction, InstrSize);
       EntrySize += InstrSize;
-      if (!BC->MIB->isIndirectBranch(Instruction)) {
-        Instructions.emplace_back(Instruction);
-        InstrOffset += InstrSize;
-        continue;
-      }
-
-      const uint64_t EntryAddress = SectionAddress + EntryOffset;
-      const uint64_t TargetAddress = BC->MIB->analyzePLTEntry(
-          Instruction, Instructions.begin(), Instructions.end(), EntryAddress);
-
+      if (BC->MIB->isIndirectBranch(Instruction)) {
+        break;
+      }
+        Instructions.begin(), Instructions.end(), EntryAddress);
+    BinaryFunction *BF =
         createPLTBinaryFunction(TargetAddress, EntryAddress, EntrySize);
-      break;
+    assert(BF && "Failed to create PLT function");
+    if (opts::Rewrite) {
+      assert(BF && BF->empty());
+      BF->setSize(EntrySize);
+      BF->updateState(BinaryFunction::State::Disassembled);
+      BinaryBasicBlock *BB = BF->addBasicBlockAt(0, BF->getSymbol());
+      for (auto &Inst : Instructions) {
+        BB->addInstruction(Inst);
+      }
+      bool Ok = BF->handlePLT();
+      assert(Ok && "Failed to handle PLT entry");
+      (void)Ok;
+      BF->updateState(BinaryFunction::State::CFG);
     }
 
-    // Branch instruction
-    InstrOffset += InstrSize;
-
     // Skip nops if any
     while (InstrOffset < SectionSize) {
       disassembleInstruction(InstrOffset, Instruction, InstrSize);
       if (!BC->MIB->isNoop(Instruction))
         break;
 
       InstrOffset += InstrSize;
+      if (opts::Rewrite) {
+        BF->getBasicBlockAtOffset(0)->addInstruction(Instruction);
+        BF->setSize(BF->getSize() + InstrSize);
+      }
+    }
+  }
+}
+
+void RewriteInstance::createGOTPLTRelocations() {
+  const uint64_t RelType = Relocation::getAbs64();
+  auto CreateRelocations = [this, RelType](BinarySection &Section, bool IsGot) {
+    DataExtractor DE(Section.getContents(), BC->AsmInfo->isLittleEndian(),
+                     BC->AsmInfo->getCodePointerSize());
+    const uint64_t Size = Section.getSize();
+    assert(Size % BC->AsmInfo->getCodePointerSize() == 0 && "Invalid GOT size");
+    for (uint64_t DataOffset = 0; DataOffset < Size;) {
+      const uint64_t Offset = DataOffset;
+      const uint64_t Address = DE.getU64(&DataOffset);
+      if (Address == 0 || Address == ~0ULL)
+        continue;
+      MCSymbol *Sym = BC->getOrCreateGlobalSymbol(Address, "SYMBOLat");
+      Section.addRelocation(Offset, Sym, RelType, 0);
+      if (!opts::Rewrite || !IsGot || !BC->isRISC())
+        continue;
+      if (BinaryData *BD = BC->getBinaryDataAtAddress(Address)) {
+        for (auto *Sym : BD->getSymbols()) {
+          StringRef Name = Sym->getName();
+          Name = Name.substr(0, Name.find('/'));
+          if (Name.empty())
+            continue;
+          GOTSymbolsByName[Name.str()] = Section.getAddress() + Offset;
+
+          LLVM_DEBUG(
+              outs() << formatv(
+                  "BOLT-INFO: BD {0} with address {1:x} at got entry {2:x}\n",
+                  Sym->getName(), Address, Section.getAddress() + Offset););
+        }
       }
     }
+  };
+
+  auto GOTPLTSection = BC->getUniqueSectionByName(".got.plt");
+  if (opts::Rewrite && GOTPLTSection)
+    CreateRelocations(*GOTPLTSection, false);
+  auto GOTSection = BC->getUniqueSectionByName(".got");
+  if (GOTSection)
+    CreateRelocations(*GOTSection, true);
 }
 
+
 void RewriteInstance::disassemblePLTSectionRISCV(BinarySection &Section) {
   const uint64_t SectionAddress = Section.getAddress();
   const uint64_t SectionSize = Section.getSize();
   StringRef PLTContents = Section.getContents();
   ArrayRef<uint8_t> PLTData(
       reinterpret_cast<const uint8_t *>(PLTContents.data()), SectionSize);
 
   auto disassembleInstruction = [&](uint64_t InstrOffset, MCInst &Instruction,
                                     uint64_t &InstrSize) {
     const uint64_t InstrAddr = SectionAddress + InstrOffset;
     if (!BC->DisAsm->getInstruction(Instruction, InstrSize,
                                     PLTData.slice(InstrOffset), InstrAddr,
                                     nulls())) {
       errs() << "BOLT-ERROR: unable to disassemble instruction in PLT section "
              << Section.getName() << " at offset 0x"
              << Twine::utohexstr(InstrOffset) << '\n';
       exit(1);
     }
   };
 
-  // Skip the first special entry since no relocation points to it.
-  uint64_t InstrOffset = 32;
+  uint64_t InstrOffset = 0;
 
   while (InstrOffset < SectionSize) {
     InstructionListType Instructions;
     MCInst Instruction;
     const uint64_t EntryOffset = InstrOffset;
-    const uint64_t EntrySize = 16;
+    uint64_t EntrySize = EntryOffset == 0 ? 32 : 16;
     uint64_t InstrSize;
 
     while (InstrOffset < EntryOffset + EntrySize) {
       disassembleInstruction(InstrOffset, Instruction, InstrSize);
       Instructions.emplace_back(Instruction);
       InstrOffset += InstrSize;
     }
 
     const uint64_t EntryAddress = SectionAddress + EntryOffset;
     const uint64_t TargetAddress = BC->MIB->analyzePLTEntry(
-        Instruction, Instructions.begin(), Instructions.end(), EntryAddress);
+        Instructions.begin(), Instructions.end(), EntryAddress);
 
+    BinaryFunction *BF =
         createPLTBinaryFunction(TargetAddress, EntryAddress, EntrySize);
+    assert(BF && "Failed to create PLT function");
+    if (opts::Rewrite) {
+      assert(BF && BF->empty());
+      BF->setSize(EntrySize);
+      BF->updateState(BinaryFunction::State::Disassembled);
+      BinaryBasicBlock *BB = BF->addBasicBlockAt(0, BF->getSymbol());
+      for (auto &Inst : Instructions) {
+        BB->addInstruction(Inst);
+      }
+      bool Ok = BF->handlePLT();
+      assert(Ok && "Failed to handle PLT entry");
+      (void)Ok;
+      BF->updateState(BinaryFunction::State::CFG);
+    }
+    // Skip nops if any
+    while (InstrOffset < SectionSize) {
+      disassembleInstruction(InstrOffset, Instruction, InstrSize);
+      if (!BC->MIB->isNoop(Instruction))
+        break;
+
+      InstrOffset += InstrSize;
+      if (opts::Rewrite) {
+        BF->getBasicBlockAtOffset(0)->addInstruction(Instruction);
+        BF->setSize(BF->getSize() + InstrSize);
+      }
+    }
   }
 }
 
 void RewriteInstance::disassemblePLTSectionX86(BinarySection &Section,
                                                uint64_t EntrySize) {
   const uint64_t SectionAddress = Section.getAddress();
   const uint64_t SectionSize = Section.getSize();
   StringRef PLTContents = Section.getContents();
auto disassembleInstruction = [&](uint64_t InstrOffset, MCInst &Instruction,
     }
   };
 
   for (uint64_t EntryOffset = 0; EntryOffset + EntrySize <= SectionSize;
        EntryOffset += EntrySize) {
     MCInst Instruction;
     uint64_t InstrSize, InstrOffset = EntryOffset;
     while (InstrOffset < EntryOffset + EntrySize) {
+      uint64_t TargetAddress = 0;
       disassembleInstruction(InstrOffset, Instruction, InstrSize);
       // Check if the entry size needs adjustment.
       if (EntryOffset == 0 && BC->MIB->isTerminateBranch(Instruction) &&
           EntrySize == 8)
         EntrySize = 16;
 
-      if (BC->MIB->isIndirectBranch(Instruction))
-        break;
-
-      InstrOffset += InstrSize;
+      if (BC->MIB->hasPCRelOperand(Instruction)) {
+        bool Ok = BC->MIB->evaluateMemOperandTarget(
+            Instruction, TargetAddress, SectionAddress + InstrOffset,
+            InstrSize);
+        assert(Ok && "Failed to evaluate PLT operand!");
+        (void)Ok;
+        if (opts::Rewrite) {
+          MCSymbol *Sym = BC->getOrCreateGlobalSymbol(TargetAddress, "DATAat");
+          // This is a hack to work around the fact that we don't actually
+          // disassemble plt. We bluntly assume immediate size of 4 and create
+          // addend because the address is relative to the next instruction
+          // This should be properly done by disassembling plt, replacing the
+          // operand with symbol ref and emitting it back, but it's harder to
+          // do on X86 because entries may terminate differently depending on
+          // PLT type, so we just patch immediates - at least for now.
+          const uint64_t SizeOfImm = 4;
+          assert(InstrSize > SizeOfImm);
+          const uint64_t OffsetOfImm = InstrOffset + InstrSize - SizeOfImm;
+          const uint64_t Addend = -SizeOfImm;
+          Section.addRelocation(OffsetOfImm, Sym, ELF::R_X86_64_PC32, Addend);
         }
-
-    if (InstrOffset + InstrSize > EntryOffset + EntrySize)
-      continue;
-
-    uint64_t TargetAddress;
-    if (!BC->MIB->evaluateMemOperandTarget(Instruction, TargetAddress,
-                                           SectionAddress + InstrOffset,
-                                           InstrSize)) {
-      errs() << "BOLT-ERROR: error evaluating PLT instruction at offset 0x"
-             << Twine::utohexstr(SectionAddress + InstrOffset) << '\n';
-      exit(1);
       }
-
-    createPLTBinaryFunction(TargetAddress, SectionAddress + EntryOffset,
-                            EntrySize);
+      if (BC->MIB->isIndirectBranch(Instruction)) {
+        assert(TargetAddress);
+        const uint64_t EntryAddress = SectionAddress + EntryOffset;
+        BinaryFunction *BF =
+            createPLTBinaryFunction(TargetAddress, EntryAddress, EntrySize);
+        assert(BF && "Failed to create PLT function");
+      }
+      InstrOffset += InstrSize;
+    }
   }
 }
 
 void RewriteInstance::disassemblePLT() {
   auto analyzeOnePLTSection = [&](BinarySection &Section, uint64_t EntrySize) {
     if (BC->isAArch64())
       return disassemblePLTSectionAArch64(Section);
     if (BC->isRISCV())
       return disassemblePLTSectionRISCV(Section);
     return disassemblePLTSectionX86(Section, EntrySize);
   };
 
   for (BinarySection &Section : BC->allocatableSections()) {
     const PLTSectionInfo *PLTSI = getPLTSectionInfo(Section.getName());
     if (!PLTSI)
       continue;
 
     analyzeOnePLTSection(Section, PLTSI->EntrySize);
 
     BinaryFunction *PltBF;
     auto BFIter = BC->getBinaryFunctions().find(Section.getAddress());
-    if (BFIter != BC->getBinaryFunctions().end()) {
-      PltBF = &BFIter->second;
-    } else {
-      // If we did not register any function at the start of the section,
-      // then it must be a general PLT entry. Add a function at the location.
-      PltBF = BC->createBinaryFunction(
-          "__BOLT_PSEUDO_" + Section.getName().str(), Section,
-          Section.getAddress(), 0, PLTSI->EntrySize, Section.getAlignment());
-    }
+    assert(BFIter != BC->getBinaryFunctions().end() &&
+           "Failed to create PLT header function");
     PltBF->setPseudo(true);
   }
 }
 
 void RewriteInstance::adjustFunctionBoundaries() {
   for (auto BFI = BC->getBinaryFunctions().begin(),
             BFE = BC->getBinaryFunctions().end();
        BFI != BFE; ++BFI) {
void RewriteInstance::adjustCommandLineOptions() {
   }
 
   if (opts::HotText && opts::HotTextMoveSections.getNumOccurrences() == 0) {
     opts::HotTextMoveSections.addValue(".stub");
     opts::HotTextMoveSections.addValue(".mover");
     opts::HotTextMoveSections.addValue(".never_hugify");
   }
 
-  if (opts::UseOldText && !BC->OldTextSectionAddress) {
-    errs() << "BOLT-WARNING: cannot use old .text as the section was not found"
-              "\n";
-    opts::UseOldText = false;
+  if (opts::Hugify) {
+    opts::AlignText = BinaryContext::HugePageSize;
+    BC->PageAlign = BinaryContext::HugePageSize;
   }
-  if (opts::UseOldText && !BC->HasRelocations) {
-    errs() << "BOLT-WARNING: cannot use old .text in non-relocation mode\n";
+
+  if (opts::AlignText < opts::AlignFunctions)
+    opts::AlignText = (unsigned)opts::AlignFunctions;
+
+  if (opts::UseOldText) {
+    errs() << "BOLT-WARNING: '-use-old-text' is deprecated, "
+              "using -rewrite instead.\n";
     opts::UseOldText = false;
+    opts::Rewrite = true;
   }
 
-  if (!opts::AlignText.getNumOccurrences())
-    opts::AlignText = BC->PageAlign;
+  if (opts::Rewrite && !BC->HasRelocations) {
+    errs() << "BOLT-ERROR: cannot rewrite in non-relocation mode\n";
+    exit(1);
+  }
 
   if (opts::AlignText < opts::AlignFunctions)
     opts::AlignText = (unsigned)opts::AlignFunctions;
 
   if (BC->isX86() && opts::Lite.getNumOccurrences() == 0 && !opts::StrictMode &&
-      !opts::UseOldText)
+      !opts::Rewrite)
     opts::Lite = true;
 
-  if (opts::Lite && opts::UseOldText) {
-    errs() << "BOLT-WARNING: cannot combine -lite with -use-old-text. "
-              "Disabling -use-old-text.\n";
-    opts::UseOldText = false;
-  }
-
   if (opts::Lite && opts::StrictMode) {
     errs() << "BOLT-ERROR: -strict and -lite cannot be used at the same time\n";
     exit(1);
   }
 
+  if (opts::Lite && opts::Rewrite) {
+    errs() << "BOLT-ERROR: cannot combine -lite with -rewrite.\n";
+    exit(1);
+  }
+
   if (opts::Lite)
     outs() << "BOLT-INFO: enabling lite mode\n";
 
   if (!opts::SaveProfile.empty() && BAT->enabledFor(InputFile)) {
     errs() << "BOLT-ERROR: unable to save profile in YAML format for input "
               "file processed by BOLT. Please remove -w option and use branch "
               "profile.\n";
     exit(1);
case ELF::SHT_RELA: {
     Addend = RelA->r_addend;
     break;
   }
   }
 
   return Addend;
 }
 
 int64_t getRelocationAddend(const ELFObjectFileBase *Obj,
                             const RelocationRef &Rel) {
   return getRelocationAddend(cast<ELF64LEObjectFile>(Obj), Rel);
 }
 
 template <typename ELFT>
 uint32_t getRelocationSymbol(const ELFObjectFile<ELFT> *Obj,
                              const RelocationRef &RelRef) {
   using ELFShdrTy = typename ELFT::Shdr;
   uint32_t Symbol = 0;
bool RewriteInstance::analyzeRelocation(
 
   const bool IsAArch64 = BC->isAArch64();
 
   const size_t RelSize = Relocation::getSizeForType(RType);
 
   ErrorOr<uint64_t> Value =
       BC->getUnsignedValueAtAddress(Rel.getOffset(), RelSize);
   assert(Value && "failed to extract relocated value");
-  if ((Skip = Relocation::skipRelocationProcess(RType, *Value)))
+  Skip = Relocation::skipRelocationProcess(RType, *Value);
+  if (Skip)
     return true;
-
   ExtractedValue = Relocation::extractValue(RType, *Value, Rel.getOffset());
   Addend = getRelocationAddend(InputFile, Rel);
 
   const bool IsPCRelative = Relocation::isPCRelative(RType);
   const uint64_t PCRelOffset = IsPCRelative && !IsAArch64 ? Rel.getOffset() : 0;
   bool SkipVerification = false;
+
   auto SymbolIter = Rel.getSymbol();
   if (SymbolIter == InputFile->symbol_end()) {
     SymbolAddress = ExtractedValue - Addend + PCRelOffset;
     MCSymbol *RelSymbol =
         BC->getOrCreateGlobalSymbol(SymbolAddress, "RELSYMat");
     SymbolName = std::string(RelSymbol->getName());
     IsSectionRelocation = false;
   } else {
     const SymbolRef &Symbol = *SymbolIter;
     SymbolName = std::string(cantFail(Symbol.getName()));
+
     SymbolAddress = cantFail(Symbol.getAddress());
     SkipVerification = (cantFail(Symbol.getType()) == SymbolRef::ST_Other);
     // Section symbols are marked as ST_Debug.
     IsSectionRelocation = (cantFail(Symbol.getType()) == SymbolRef::ST_Debug);
     // Check for PLT entry registered with symbol name
-    if (!SymbolAddress && (IsAArch64 || BC->isRISCV())) {
+    if (opts::Rewrite && Relocation::isGOT(RType) && BC->isRISC()) {
+      std::string StrippedName = SymbolName.substr(0, SymbolName.find("@"));
+      if (auto It = GOTSymbolsByName.find(StrippedName);
+          It != GOTSymbolsByName.end()) {
+        SymbolAddress = It->second;
+      } else {
+        // we can't determine which .got entry is referenced by that
+        // instruction, so we have to relax .got access to direct access. For
+        // adrp it is enough to just change relocation type to load page address
+        // of the symbol itself, while LDR will be handled during disassembly -
+        // we'll change LDR to ADD when we see ldr with
+        // R_AARCH64_ADD_ABS_LO12_NC relocation.
+        switch (RType) {
+        case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+        case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+          // for TLS relocs, we'll match instructions during disassembly to
+          // determine .got entry.
+          break;
+        case ELF::R_AARCH64_ADR_GOT_PAGE:
+          outs() << formatv("BOLT-WARNING: cannot find .got entry for symbol "
+                            "{0} referenced by R_AARCH64_ADR_GOT_PAGE at {1:x}. Will relax to adrp+add\n",
+                            StrippedName, Rel.getOffset());
+          RType = ELF::R_AARCH64_ADR_PREL_PG_HI21;
+          break;
+        case ELF::R_AARCH64_LD64_GOT_LO12_NC:
+          outs() << formatv("BOLT-WARNING: cannot find .got entry for symbol "
+                            "{0} referenced by R_AARCH64_LD64_GOT_LO12_NC at {1:x}. Will relax to adrp+add\n",
+                            StrippedName, Rel.getOffset());
+          RType = ELF::R_AARCH64_ADD_ABS_LO12_NC;
+          break;
+        default:
+          errs() << formatv("BOLT-ERROR: Unexpected .got access relocation at {0:x}: can't find .got entry for {1}!\n",
+                            Rel.getOffset(), StrippedName);
+          exit(1);
+        }
+      }
+    }
+    if (!SymbolAddress && IsAArch64) {
       const BinaryData *BD = BC->getPLTBinaryDataByName(SymbolName);
       SymbolAddress = BD ? BD->getAddress() : 0;
     }
   }
   // For PIE or dynamic libs, the linker may choose not to put the relocation
   // result at the address if it is a X86_64_64 one because it will emit a
   // dynamic relocation (X86_RELATIVE) for the dynamic linker and loader to
   // resolve it at run time. The static relocation result goes as the addend
bool RewriteInstance::analyzeRelocation(
 
   // If no symbol has been found or if it is a relocation requiring the
   // creation of a GOT entry, do not link against the symbol but against
   // whatever address was extracted from the instruction itself. We are
   // not creating a GOT entry as this was already processed by the linker.
   // For GOT relocs, do not subtract addend as the addend does not refer
   // to this instruction's target, but it refers to the target in the GOT
   // entry.
-  if (Relocation::isGOT(RType)) {
+  if (Relocation::isGOT(RType) && (BC->isX86() || !opts::Rewrite)) {
     Addend = 0;
     SymbolAddress = ExtractedValue + PCRelOffset;
   } else if (Relocation::isTLS(RType)) {
     SkipVerification = true;
   } else if (!SymbolAddress) {
     assert(!IsSectionRelocation);
     if (ExtractedValue || Addend == 0 || IsPCRelative) {
       SymbolAddress =
if (ExtractedValue || Addend == 0 || IsPCRelative) {
       return true;
     }
   }
 
   auto verifyExtractedValue = [&]() {
     if (SkipVerification)
       return true;
 
-    if (IsAArch64 || BC->isRISCV())
+    if (BC->isRISC())
       return true;
 
     if (SymbolName == "__hot_start" || SymbolName == "__hot_end")
       return true;
 
     if (RType == ELF::R_X86_64_PLT32)
       return true;
 
for (const RelocationRef &Rel : Section.relocations()) {
     );
 
     if (IsJmpRel)
       IsJmpRelocation[RType] = true;
 
     if (Symbol)
       SymbolIndex[Symbol] = getRelocationSymbol(InputFile, Rel);
 
+    auto IsGotLikeReloc = [this](const uint64_t RType) {
+      return ((BC->isAArch64() && (RType == ELF::R_AARCH64_GLOB_DAT ||
+                                   RType == ELF::R_AARCH64_RELATIVE ||
+                                   RType == ELF::R_AARCH64_TLS_TPREL64)) ||
+              (BC->isRISCV() && RType == ELF::R_RISCV_64));
+    };
+
+    if (opts::Rewrite && IsGotLikeReloc(RType)) {
+      if (Symbol && !SymbolName.empty()) {
+        GOTSymbolsByName[SymbolName.str()] = Rel.getOffset();
+        LLVM_DEBUG(dbgs() << formatv("BOLT-INFO: GOT entry at {0:x} contains "
+                                     "symbol {1} with address {2:x}\n",
+                                     Rel.getOffset(), SymbolName, Addend););
+      } else if (BinaryData *BD = BC->getBinaryDataAtAddress(Addend)) {
+        LLVM_DEBUG(outs() << formatv("BOLT-INFO: GOT entry at {0:x} contains "
+                                     "symbol {1} with address {2:x}\n",
+                                     Rel.getOffset(), BD->getName(), Addend););
+
+        for (MCSymbol *Sym : BD->getSymbols()) {
+          StringRef Name = Sym->getName().substr(0, Sym->getName().find('/'));
+          if (Name.empty())
+            continue;
+          GOTSymbolsByName[Name.str()] = Rel.getOffset();
+        }
+      }
+    }
     BC->addDynamicRelocation(Rel.getOffset(), Symbol, RType, Addend);
   }
 }
 
 void RewriteInstance::readDynamicRelrRelocations(BinarySection &Section) {
   assert(Section.isAllocatable() && "allocatable expected");
 
   LLVM_DEBUG({
void RewriteInstance::readRelocations(const SectionRef &Section) {
   }
   section_iterator SecIter = cantFail(Section.getRelocatedSection());
   assert(SecIter != InputFile->section_end() && "relocated section expected");
   SectionRef RelocatedSection = *SecIter;
 
   StringRef RelocatedSectionName = cantFail(RelocatedSection.getName());
   LLVM_DEBUG(dbgs() << "BOLT-DEBUG: relocated section is "
                     << RelocatedSectionName << '\n');
-
-  if (!BinarySection(*BC, RelocatedSection).isAllocatable()) {
+  auto RelocatedBinarySectionOrErr =
+      BC->getUniqueSectionByName(RelocatedSectionName);
+  assert(RelocatedBinarySectionOrErr);
+  BinarySection &RelocatedBinarySection = *RelocatedBinarySectionOrErr;
+  if (!RelocatedBinarySection.isAllocatable()) {
     LLVM_DEBUG(dbgs() << "BOLT-DEBUG: ignoring relocations against "
                       << "non-allocatable section\n");
     return;
   }
   const bool SkipRelocs = StringSwitch<bool>(RelocatedSectionName)
                               .Cases(".plt", ".rela.plt", ".got.plt",
                                      ".eh_frame", ".gcc_except_table", true)
                               .Default(false);
   if (SkipRelocs) {
     LLVM_DEBUG(
         dbgs() << "BOLT-DEBUG: ignoring relocations against known section\n");
     return;
   }
 
   for (const RelocationRef &Rel : Section.relocations())
-    handleRelocation(RelocatedSection, Rel);
+    handleRelocation(RelocatedBinarySection, Rel);
 }
 
-void RewriteInstance::handleRelocation(const SectionRef &RelocatedSection,
+void RewriteInstance::handleRelocation(BinarySection &RelocatedSection,
                                        const RelocationRef &Rel) {
   const bool IsAArch64 = BC->isAArch64();
   const bool IsFromCode = RelocatedSection.isText();
 
   SmallString<16> TypeName;
   Rel.getTypeName(TypeName);
   uint64_t RType = Rel.getType();
   if (Relocation::skipRelocationType(RType))
     return;
 
   // Adjust the relocation type as the linker might have skewed it.
   if (BC->isX86() && (RType & ELF::R_X86_64_converted_reloc_bit)) {
     if (opts::Verbosity >= 1)
       dbgs() << "BOLT-WARNING: ignoring R_X86_64_converted_reloc_bit\n";
     RType &= ~ELF::R_X86_64_converted_reloc_bit;
   }
-
   if (Relocation::isTLS(RType)) {
     // No special handling required for TLS relocations on X86.
     if (BC->isX86())
       return;
 
     // The non-got related TLS relocations on AArch64 also could be skipped.
     if (!Relocation::isGOT(RType))
       return;
   }
 
-  if (!IsAArch64 && BC->getDynamicRelocationAt(Rel.getOffset())) {
-    LLVM_DEBUG({
-      dbgs() << formatv("BOLT-DEBUG: address {0:x} has a ", Rel.getOffset())
-             << "dynamic relocation against it. Ignoring static relocation.\n";
-    });
-    return;
-  }
 
   std::string SymbolName;
   uint64_t SymbolAddress;
   int64_t Addend;
   uint64_t ExtractedValue;
   bool IsSectionRelocation;
   bool Skip;
   if (!analyzeRelocation(Rel, RType, SymbolName, IsSectionRelocation,
if (!IsAArch64 && !ContainingBF->containsAddress(Rel.getOffset())) {
                           *ContainingBF);
       ContainingBF->setSize(ContainingBF->getMaxSize());
       ContainingBF->setSimple(false);
       return;
     }
   }
 
   MCSymbol *ReferencedSymbol = nullptr;
-  if (!IsSectionRelocation)
+  bool IsToSectionEnd = false;
+  if (auto It = BC->EndSymbols.find(SymbolName); It != BC->EndSymbols.end()) {
+    // We need to create local symbol because using registerName will collide
+    // with the next section if it's on the same address. This requires us to
+    // check for EndSymbols in a lot of places, but what else can we do?
+    ReferencedSymbol = BC->Ctx->getOrCreateSymbol(SymbolName);
+    IsToSectionEnd = true;
+  } else if (!IsSectionRelocation)
     if (BinaryData *BD = BC->getBinaryDataByName(SymbolName))
       ReferencedSymbol = BD->getSymbol();
 
   ErrorOr<BinarySection &> ReferencedSection{std::errc::bad_address};
   symbol_iterator SymbolIter = Rel.getSymbol();
   if (SymbolIter != InputFile->symbol_end()) {
     SymbolRef Symbol = *SymbolIter;
     section_iterator Section =
if (!IsFromCode && IsToCode) {
       // table analysis.
       BC->addPCRelativeDataRelocation(Rel.getOffset());
     } else if (ContainingBF && !IsSectionRelocation && ReferencedSymbol) {
       // If we know the referenced symbol, register the relocation from
       // the code. It's required  to properly handle cases where
       // "symbol + addend" references an object different from "symbol".
       ContainingBF->addRelocation(Rel.getOffset(), ReferencedSymbol, RType,
                                   Addend, ExtractedValue);
+    } else if (opts::Rewrite && !IsToCode && !IsFromCode) {
+      if (!ReferencedSymbol) {
+        ReferencedSymbol =
+            BC->getOrCreateGlobalSymbol(SymbolAddress, "SYMBOLat");
+      }
+
+      RelocatedSection.addRelocation(
+          Rel.getOffset() - RelocatedSection.getAddress(), ReferencedSymbol,
+          RType, Addend, ExtractedValue);
+      LLVM_DEBUG({
+        dbgs() << formatv("BOLT-DEBUG: creating PC-relative data relocation at "
+                          "{0:x} for {1}\n",
+                          Rel.getOffset(), SymbolName);
+      });
     } else {
       LLVM_DEBUG({
-        dbgs() << "BOLT-DEBUG: not creating PC-relative relocation at"
-               << formatv("{0:x} for {1}\n", Rel.getOffset(), SymbolName);
+        dbgs() << formatv("BOLT-DEBUG: ignoring PC-relative relocation at "
+                          "{0:x} for {1}\n",
+                          Rel.getOffset(), SymbolName);
       });
     }
 
     return;
   }
 
   bool ForceRelocation = BC->forceSymbolRelocations(SymbolName);
   if ((BC->isAArch64() || BC->isRISCV()) && Relocation::isGOT(RType))
if (const BinaryFunction *RogueBF =
                   "bug: -1 addend used with non-pc-relative relocation against "
                << formatv("function {0} in function {1}\n", *RogueBF,
                           *ContainingBF);
         return;
       }
     }
   }
 
-  if (ForceRelocation) {
-    std::string Name =
-        Relocation::isGOT(RType) ? "__BOLT_got_zero" : SymbolName;
-    ReferencedSymbol = BC->registerNameAtAddress(Name, 0, 0, 0);
-    SymbolAddress = 0;
-    if (Relocation::isGOT(RType))
+  if (IsToSectionEnd) {
+    // do nothing, add it as it is later
+  } else if (ForceRelocation) {
+    std::string Name = SymbolName;
+    if (Relocation::isGOT(RType)) {
+      if (opts::Rewrite) {
+        Name = SymbolName + "@GOT";
+      } else {
         Addend = Address;
-    LLVM_DEBUG(dbgs() << "BOLT-DEBUG: forcing relocation against symbol "
-                      << SymbolName << " with addend " << Addend << '\n');
+        SymbolAddress = 0;
+        Name = "__BOLT_got_zero";
+      }
+    }
+    ReferencedSymbol = BC->registerNameAtAddress(Name, SymbolAddress, 0, 0);
+    LLVM_DEBUG(
+        dbgs() << formatv("BOLT-DEBUG: forcing relocation against symbol {0} "
+                          "with addend {1:x} and address {2:x}\n",
+                          SymbolName, Addend, SymbolAddress));
   } else if (ReferencedBF) {
     ReferencedSymbol = ReferencedBF->getSymbol();
     uint64_t RefFunctionOffset = 0;
 
     // Adjust the point of reference to a code location inside a function.
     if (ReferencedBF->containsAddress(Address, /*UseMaxSize = */ true)) {
       RefFunctionOffset = Address - ReferencedBF->getAddress();
       if (RefFunctionOffset) {
         if (ContainingBF && ContainingBF != ReferencedBF) {
           ReferencedSymbol =
               ReferencedBF->addEntryPointAtOffset(RefFunctionOffset);
         } else {
           ReferencedSymbol =
               ReferencedBF->getOrCreateLocalLabel(Address,
                                                   /*CreatePastEnd =*/true);
 
           // If ContainingBF != nullptr, it equals ReferencedBF (see
           // if-condition above) so we're handling a relocation from a function
           // to itself. RISC-V uses such relocations for branches, for example.
           // These should not be registered as externally references offsets.
           if (!ContainingBF)
             ReferencedBF->registerReferencedOffset(RefFunctionOffset);
         }
-        if (opts::Verbosity > 1 &&
-            BinarySection(*BC, RelocatedSection).isWritable())
+        if (opts::Verbosity > 1 && RelocatedSection.isWritable())
           errs() << "BOLT-WARNING: writable reference into the middle of the "
                  << formatv("function {0} detected at address {1:x}\n",
                             *ReferencedBF, Rel.getOffset());
       }
       SymbolAddress = Address;
       Addend = 0;
     }
     LLVM_DEBUG({
LLVM_DEBUG(if (opts::MaxDataRelocations &&
       printRelocationInfo(Rel, ReferencedSymbol->getName(), SymbolAddress,
                           Addend, ExtractedValue);
     });
 
     return (!opts::MaxDataRelocations ||
             NumDataRelocations < opts::MaxDataRelocations);
   };
 
-  if ((ReferencedSection && refersToReorderedSection(ReferencedSection)) ||
+  if (opts::Rewrite ||
+      (ReferencedSection && refersToReorderedSection(ReferencedSection)) ||
       (opts::ForceToDataRelocations && checkMaxDataRelocations()) ||
-      // RISC-V has ADD/SUB data-to-data relocations
       BC->isRISCV())
     ForceRelocation = true;
 
   if (IsFromCode) {
     ContainingBF->addRelocation(Rel.getOffset(), ReferencedSymbol, RType,
                                 Addend, ExtractedValue);
   } else if (IsToCode || ForceRelocation) {
     BC->addRelocation(Rel.getOffset(), ReferencedSymbol, RType, Addend,

 }
 
 void RewriteInstance::runOptimizationPasses() {
   NamedRegionTimer T("runOptimizationPasses", "run optimization passes",
                      TimerGroupName, TimerGroupDesc, opts::TimeRewrite);
   BinaryFunctionPassManager::runAllPasses(*BC);
 }
 
-void RewriteInstance::preregisterSections() {
-  // Preregister sections before emission to set their order in the output.
-  const unsigned ROFlags = BinarySection::getFlags(/*IsReadOnly*/ true,
-                                                   /*IsText*/ false,
-                                                   /*IsAllocatable*/ true);
-  if (BinarySection *EHFrameSection = getSection(getEHFrameSectionName())) {
-    // New .eh_frame.
-    BC->registerOrUpdateSection(getNewSecPrefix() + getEHFrameSectionName(),
-                                ELF::SHT_PROGBITS, ROFlags);
-    // Fully register a relocatable copy of the original .eh_frame.
+void RewriteInstance::renameAndPreregisterSections() {
+
+  auto Rename = [this](BinarySection *Section) {
+    if (!Section)
+      return;
+    std::string OldName = Section->getName().str();
+    const std::string NewName = (getOrgSecPrefix() + Section->getName()).str();
+    LLVM_DEBUG(dbgs() << "BOLT-DEBUG: renaming input section "
+                      << Section->getName() << " to " << NewName << "\n";);
+    BC->renameSection(*Section, NewName);
+    BC->registerOrUpdateSection(OldName, ELF::SHT_PROGBITS,
+                                Section->getELFFlags());
+  };
+  if (!opts::Rewrite) {
+    if (BC->HasRelocations)
+      Rename(getSection(BC->getMainCodeSectionName()));
+    Rename(getSection(getEHFrameSectionName()));
+    if (EHFrameSection)
       BC->registerSection(".relocated.eh_frame", *EHFrameSection);
+    Rename(getSection(".eh_frame_hdr"));
+    Rename(getSection(".gcc_except_table"));
   }
-  BC->registerOrUpdateSection(getNewSecPrefix() + ".gcc_except_table",
-                              ELF::SHT_PROGBITS, ROFlags);
-  BC->registerOrUpdateSection(getNewSecPrefix() + ".rodata", ELF::SHT_PROGBITS,
-                              ROFlags);
-  BC->registerOrUpdateSection(getNewSecPrefix() + ".rodata.cold",
-                              ELF::SHT_PROGBITS, ROFlags);
+  if (opts::JumpTables > JTS_BASIC)
+    Rename(getSection(".rodata"));
 }
 
 void RewriteInstance::emitAndLink() {
   NamedRegionTimer T("emitAndLink", "emit and link", TimerGroupName,
                      TimerGroupDesc, opts::TimeRewrite);
 
   SmallString<0> ObjectBuffer;
   raw_svector_ostream OS(ObjectBuffer);
 
   // Implicitly MCObjectStreamer takes ownership of MCAsmBackend (MAB)
   // and MCCodeEmitter (MCE). ~MCObjectStreamer() will delete these
   // two instances.
   std::unique_ptr<MCStreamer> Streamer = BC->createStreamer(OS);
 
   if (EHFrameSection) {
-    if (opts::UseOldText || opts::StrictMode) {
+    if (opts::Rewrite || opts::StrictMode) {
       // The section is going to be regenerated from scratch.
       // Empty the contents, but keep the section reference.
       EHFrameSection->clearContents();
     } else {
       // Make .eh_frame relocatable.
       relocateEHFrameSection();
     }
   }
if (opts::KeepTmp) {
     raw_fd_ostream FOS(OutObjectPath, EC);
     check_error(EC, "cannot create output object file");
     FOS << ObjectBuffer;
     outs() << "BOLT-INFO: intermediary output object file saved for debugging "
               "purposes: "
            << OutObjectPath << "\n";
   }
 
-  ErrorOr<BinarySection &> TextSection =
-      BC->getUniqueSectionByName(BC->getMainCodeSectionName());
-  if (BC->HasRelocations && TextSection)
-    BC->renameSection(*TextSection, getOrgSecPrefix() + ".text");
-
   //////////////////////////////////////////////////////////////////////////////
   // Assign addresses to new sections.
   //////////////////////////////////////////////////////////////////////////////
 
   // Get output object as ObjectFile.
   std::unique_ptr<MemoryBuffer> ObjectMemBuffer =
       MemoryBuffer::getMemBuffer(ObjectBuffer, "in-memory object file", false);
 
   auto EFMM = std::make_unique<ExecutableFileMemoryManager>(*BC);
-  EFMM->setNewSecPrefix(getNewSecPrefix());
-  EFMM->setOrgSecPrefix(getOrgSecPrefix());
 
   Linker = std::make_unique<JITLinkLinker>(*BC, std::move(EFMM));
-  Linker->loadObject(ObjectMemBuffer->getMemBufferRef(),
-                     [this](auto MapSection) { mapFileSections(MapSection); });
+  Linker->loadObject(
+      ObjectMemBuffer->getMemBufferRef(),
+      [this](auto AssignAddress) { mapAllocatableSections(AssignAddress); });
 
   MCAsmLayout FinalLayout(
       static_cast<MCObjectStreamer *>(Streamer.get())->getAssembler());
 
   // Update output addresses based on the new section map and
   // layout. Only do this for the object created by ourselves.
   updateOutputValues(FinalLayout);
 
   if (opts::UpdateDebugSections)
     DebugInfoRewriter->updateLineTableOffsets(FinalLayout);
 
   if (RuntimeLibrary *RtLibrary = BC->getRuntimeLibrary())
-    RtLibrary->link(*BC, ToolPath, *Linker, [this](auto MapSection) {
+    RtLibrary->link(*BC, ToolPath, *Linker, [this](auto AssignAddress) {
       // Map newly registered sections.
-      this->mapAllocatableSections(MapSection);
+      this->mapRuntimeLibrary(AssignAddress);
     });
 
+  if (opts::Rewrite) {
+    // map the first non-allocatable address to the first non-allocatable
+    // offset so that BSS doesn't occupy file space.
+    FirstNonAllocatableOffset =
+        BC->OutputSegments.back().p_offset + BC->OutputSegments.back().p_filesz;
+    BC->OutputAddressToOffsetMap[NextAvailableAddress] =
+        FirstNonAllocatableOffset;
+  }
+  mapNonLoadableSegments();
   // Once the code is emitted, we can rename function sections to actual
   // output sections and de-register sections used for emission.
   for (BinaryFunction *Function : BC->getAllBinaryFunctions()) {
     ErrorOr<BinarySection &> Section = Function->getCodeSection();
     if (Section &&
         (Function->getImageAddress() == 0 || Function->getImageSize() == 0))
       continue;
 
NamedRegionTimer T("updateDebugInfo", "update debug info", TimerGroupName,
                        TimerGroupDesc, opts::TimeRewrite);
     DebugInfoRewriter->updateDebugInfo();
   }
 
   if (opts::WriteBoltInfoSection)
     addBoltInfoSection();
 }
 
-void RewriteInstance::mapFileSections(BOLTLinker::SectionMapper MapSection) {
+void RewriteInstance::mapAllocatableSections(
+    BOLTLinker::SectionMapper AssignAddress) {
+  if (opts::Rewrite) {
+    // Assign new address to every section and
+    // put new sections in the end of old segments,
+    // matching sections with segments by their flags.
+    mapLoadableSegments(AssignAddress);
+  } else {
+    // Reassign old addresses to old sections and segments,
+    // and create new segments for new sections.
+    remapLoadableSegments(AssignAddress);
+  }
+  ProgramHeader LastSegment = BC->OutputSegments.back();
+  const uint64_t EndOfLastSegmentInMem =
+      LastSegment.p_vaddr + LastSegment.p_memsz;
+  const uint64_t EndOfLastSegmentInFile =
+      LastSegment.p_offset + LastSegment.p_filesz;
+  for (BinarySection &Section : BC->allocatableSections()) {
+    if (!Section.getOutputAddress()) {
+      // because of strip, zero-sized sections such as .bss may end up outside
+      // of any segments and stay unmapped. Just put them in end of the last
+      // segment.
+      if (Section.getInputFileOffset() && Section.getSize() == 0) {
+        dbgs() << formatv("BOLT-WARNING: zero-sized allocatable section {0} is "
+                          "outside of any segment.\n",
+                          Section.getName());
+
+        Section.setOutputAddress(EndOfLastSegmentInMem);
+        Section.setOutputFileOffset(EndOfLastSegmentInFile);
+        if (Section.hasValidSectionID())
+          AssignAddress(Section, Section.getOutputAddress());
+        Section.setIsFinalized();
+      }
+    }
+  }
+}
+
+void RewriteInstance::remapLoadableSegments(
+    BOLTLinker::SectionMapper AssignAddress) {
   BC->deregisterUnusedSections();
 
+  auto RestoreName = [this](BinarySection *Section, StringRef Name) {
+    if (!Section)
+      return;
+    LLVM_DEBUG(dbgs() << formatv("BOLT-DEBUG: original section {0} was "
+                                 "not duplicated, restoring name\n",
+                                 Name));
+    assert(!getSection(Name) && "Unexpected section emitted");
+    BC->renameSection(*Section, Name);
+  };
   // If no new .eh_frame was written, remove relocated original .eh_frame.
   BinarySection *RelocatedEHFrameSection =
       getSection(".relocated" + getEHFrameSectionName());
   if (RelocatedEHFrameSection && RelocatedEHFrameSection->hasValidSectionID()) {
-    BinarySection *NewEHFrameSection =
-        getSection(getNewSecPrefix() + getEHFrameSectionName());
+    BinarySection *NewEHFrameSection = getSection(getEHFrameSectionName());
     if (!NewEHFrameSection || !NewEHFrameSection->isFinalized()) {
       // JITLink will still have to process relocations for the section, hence
       // we need to assign it the address that wouldn't result in relocation
       // processing failure.
-      MapSection(*RelocatedEHFrameSection, NextAvailableAddress);
+      AssignAddress(*RelocatedEHFrameSection, NextAvailableAddress);
       BC->deregisterSection(*RelocatedEHFrameSection);
-    }
-  }
-
-  mapCodeSections(MapSection);
 
-  // Map the rest of the sections.
-  mapAllocatableSections(MapSection);
+      // Remove org prefix from sections since they weren't duplicated
+      RestoreName(&*EHFrameSection, getEHFrameSectionName());
+      RestoreName(getSection(getOrgSecPrefix() + getEHFrameHeaderSectionName()),
+                  getEHFrameHeaderSectionName());
+      RestoreName(getSection(getOrgSecPrefix() + ".gcc_except_table"),
+                  ".gcc_except_table");
     }
-
-std::vector<BinarySection *> RewriteInstance::getCodeSections() {
-  std::vector<BinarySection *> CodeSections;
-  for (BinarySection &Section : BC->textSections())
-    if (Section.hasValidSectionID())
-      CodeSections.emplace_back(&Section);
-
-  auto compareSections = [&](const BinarySection *A, const BinarySection *B) {
-    // If both A and B have names starting with ".text.cold", then
-    // - if opts::HotFunctionsAtEnd is true, we want order
-    //   ".text.cold.T", ".text.cold.T-1", ... ".text.cold.1", ".text.cold"
-    // - if opts::HotFunctionsAtEnd is false, we want order
-    //   ".text.cold", ".text.cold.1", ... ".text.cold.T-1", ".text.cold.T"
-    if (A->getName().startswith(BC->getColdCodeSectionName()) &&
-        B->getName().startswith(BC->getColdCodeSectionName())) {
-      if (A->getName().size() != B->getName().size())
-        return (opts::HotFunctionsAtEnd)
-                   ? (A->getName().size() > B->getName().size())
-                   : (A->getName().size() < B->getName().size());
-      return (opts::HotFunctionsAtEnd) ? (A->getName() > B->getName())
-                                       : (A->getName() < B->getName());
-    }
 
-    // Place movers before anything else.
-    if (A->getName() == BC->getHotTextMoverSectionName())
-      return true;
-    if (B->getName() == BC->getHotTextMoverSectionName())
-      return false;
-
-    // Depending on the option, put main text at the beginning or at the end.
-    if (opts::HotFunctionsAtEnd)
-      return B->getName() == BC->getMainCodeSectionName();
-    else
-      return A->getName() == BC->getMainCodeSectionName();
-  };
-
-  // Determine the order of sections.
-  llvm::stable_sort(CodeSections, compareSections);
-
-  return CodeSections;
-}
-
-void RewriteInstance::mapCodeSections(BOLTLinker::SectionMapper MapSection) {
   if (BC->HasRelocations) {
     // Map sections for functions with pre-assigned addresses.
     for (BinaryFunction *InjectedFunction : BC->getInjectedBinaryFunctions()) {
       const uint64_t OutputAddress = InjectedFunction->getOutputAddress();
       if (!OutputAddress)
         continue;
 
       ErrorOr<BinarySection &> FunctionSection =
           InjectedFunction->getCodeSection();
       assert(FunctionSection && "function should have section");
       FunctionSection->setOutputAddress(OutputAddress);
-      MapSection(*FunctionSection, OutputAddress);
+      AssignAddress(*FunctionSection, OutputAddress);
       InjectedFunction->setImageAddress(FunctionSection->getAllocAddress());
       InjectedFunction->setImageSize(FunctionSection->getOutputSize());
     }
-
-    // Populate the list of sections to be allocated.
-    std::vector<BinarySection *> CodeSections = getCodeSections();
-
-    // Remove sections that were pre-allocated (patch sections).
-    llvm::erase_if(CodeSections, [](BinarySection *Section) {
-      return Section->getOutputAddress();
-    });
-    LLVM_DEBUG(dbgs() << "Code sections in the order of output:\n";
-      for (const BinarySection *Section : CodeSections)
-        dbgs() << Section->getName() << '\n';
-    );
-
-    uint64_t PaddingSize = 0; // size of padding required at the end
-
-    // Allocate sections starting at a given Address.
-    auto allocateAt = [&](uint64_t Address) {
-      for (BinarySection *Section : CodeSections) {
-        Address = alignTo(Address, Section->getAlignment());
-        Section->setOutputAddress(Address);
-        Address += Section->getOutputSize();
-
-        // Hugify: Additional huge page from right side due to
-        // weird ASLR mapping addresses (4KB aligned)
-        if (opts::Hugify && !BC->HasFixedLoadAddress &&
-            Section->getName() == BC->getMainCodeSectionName())
-          Address = alignTo(Address, Section->getAlignment());
-      }
 
-      // Make sure we allocate enough space for huge pages.
-      ErrorOr<BinarySection &> TextSection =
-          BC->getUniqueSectionByName(BC->getMainCodeSectionName());
-      if (opts::HotText && TextSection && TextSection->hasValidSectionID()) {
-        uint64_t HotTextEnd =
-            TextSection->getOutputAddress() + TextSection->getOutputSize();
-        HotTextEnd = alignTo(HotTextEnd, BC->PageAlign);
-        if (HotTextEnd > Address) {
-          PaddingSize = HotTextEnd - Address;
-          Address = HotTextEnd;
-        }
-      }
-      return Address;
-    };
+  for (const ProgramHeader &Phdr : BC->loadableSegments()) {
+    copySegment(Phdr, AssignAddress);
 
-    // Check if we can fit code in the original .text
-    bool AllocationDone = false;
-    if (opts::UseOldText) {
-      const uint64_t CodeSize =
-          allocateAt(BC->OldTextSectionAddress) - BC->OldTextSectionAddress;
+  assert(NextAvailableAddress && "Uninitialized NextAvailableAddress!");
+  assert(PHDRTableAddress && PHDRTableOffset &&
+         "Uninitialized PHDRTable location!");
+  BC->OutputSegments.insert(
+      BC->OutputSegments.begin(),
+      ProgramHeader(ELF::PT_PHDR, ELF::PF_R, PHDRTableOffset, PHDRTableAddress,
+                    PHDRTableAddress,
+                    /* file/mem size will be adjusted in writeELFPHDRTable*/ 0,
+                    0, 0x8));
 
-      if (CodeSize <= BC->OldTextSectionSize) {
-        outs() << "BOLT-INFO: using original .text for new code with 0x"
-               << Twine::utohexstr(opts::AlignText) << " alignment\n";
-        AllocationDone = true;
-      } else {
-        errs() << "BOLT-WARNING: original .text too small to fit the new code"
-               << " using 0x" << Twine::utohexstr(opts::AlignText)
-               << " alignment. " << CodeSize << " bytes needed, have "
-               << BC->OldTextSectionSize << " bytes available.\n";
-        opts::UseOldText = false;
-      }
-    }
+  if (!BC->HasRelocations) {
+    mapFunctionsNonRelocMode(AssignAddress);
 
-    if (!AllocationDone)
-      NextAvailableAddress = allocateAt(NextAvailableAddress);
-
-    // Do the mapping for ORC layer based on the allocation.
-    for (BinarySection *Section : CodeSections) {
-      LLVM_DEBUG(
-          dbgs() << "BOLT: mapping " << Section->getName() << " at 0x"
-                 << Twine::utohexstr(Section->getAllocAddress()) << " to 0x"
-                 << Twine::utohexstr(Section->getOutputAddress()) << '\n');
-      MapSection(*Section, Section->getOutputAddress());
-      Section->setOutputFileOffset(
-          getFileOffsetForAddress(Section->getOutputAddress()));
-    }
-
-    // Check if we need to insert a padding section for hot text.
-    if (PaddingSize && !opts::UseOldText)
-      outs() << "BOLT-INFO: padding code to 0x"
-             << Twine::utohexstr(NextAvailableAddress)
-             << " to accommodate hot text\n";
-
-    return;
-  }
+  // if we instrument without rewriting, we want a single segment at
+  // PHDRTableAddress that will be created in mapRuntimeLibrary
+  if (BC->getRuntimeLibrary())
+    mapSectionGroup(BC->getAllNewSections(), AssignAddress);
+  else {
+    createLoadSegment(
+        BC->getNewSectionsByFlags(ELF::SHF_ALLOC | ELF::SHF_EXECINSTR,
+                                  /*ROwithRX*/ true),
+        AssignAddress, ELF::PF_R | ELF::PF_X, BC->PageAlign, PHDRTableAddress);
+    // In case writable sections were emitted, put them in a separate segment.
+    createLoadSegment(
+        BC->getNewSectionsByFlags(ELF::SHF_ALLOC | ELF::SHF_WRITE),
+        AssignAddress, ELF::PF_R | ELF::PF_W, BC->PageAlign);
 
-  // Processing in non-relocation mode.
+void RewriteInstance::mapFunctionsNonRelocMode(
+    BOLTLinker::SectionMapper AssignAddress) {
   uint64_t NewTextSectionStartAddress = NextAvailableAddress;
 
   for (auto &BFI : BC->getBinaryFunctions()) {
     BinaryFunction &Function = BFI.second;
     if (!Function.isEmitted())
       continue;
 
     bool TooLarge = false;
     ErrorOr<BinarySection &> FuncSection = Function.getCodeSection();
     assert(FuncSection && "cannot find section for function");
     FuncSection->setOutputAddress(Function.getAddress());
-    LLVM_DEBUG(dbgs() << "BOLT: mapping 0x"
-                      << Twine::utohexstr(FuncSection->getAllocAddress())
-                      << " to 0x" << Twine::utohexstr(Function.getAddress())
-                      << '\n');
-    MapSection(*FuncSection, Function.getAddress());
+    LLVM_DEBUG(dbgs() << formatv(
+                   "BOLT-DEBUG: mapping function {0} at {1:x} to {2:x}\n",
+                   Function.getOneName(), FuncSection->getAllocAddress(),
+                   Function.getAddress()));
+
+    AssignAddress(*FuncSection, Function.getAddress());
     Function.setImageAddress(FuncSection->getAllocAddress());
     Function.setImageSize(FuncSection->getOutputSize());
     if (Function.getImageSize() > Function.getMaxSize()) {
       TooLarge = true;
       FailedAddresses.emplace_back(Function.getAddress());
     }
 
     // Map jump tables if updating in-place.
     if (opts::JumpTables == JTS_BASIC) {
       for (auto &JTI : Function.JumpTables) {
         JumpTable *JT = JTI.second;
         BinarySection &Section = JT->getOutputSection();
         Section.setOutputAddress(JT->getAddress());
         Section.setOutputFileOffset(getFileOffsetForAddress(JT->getAddress()));
         LLVM_DEBUG(dbgs() << "BOLT-DEBUG: mapping JT " << Section.getName()
                           << " to 0x" << Twine::utohexstr(JT->getAddress())
                           << '\n');
-        MapSection(Section, JT->getAddress());
+        AssignAddress(Section, JT->getAddress());
       }
     }
 
     if (!Function.isSplit())
       continue;
 
     assert(Function.getLayout().isHotColdSplit() &&
            "Cannot allocate more than two fragments per function in "
if (TooLarge) {
       FF.setAddress(0);
       FF.setImageAddress(0);
       FF.setImageSize(0);
       FF.setFileOffset(0);
     } else {
       FF.setAddress(NextAvailableAddress);
       FF.setImageAddress(ColdSection->getAllocAddress());
       FF.setImageSize(ColdSection->getOutputSize());
-      FF.setFileOffset(getFileOffsetForAddress(NextAvailableAddress));
+      FF.setFileOffset(getOutputFileOffsetForAddress(NextAvailableAddress));
       ColdSection->setOutputAddress(FF.getAddress());
     }
 
     LLVM_DEBUG(
         dbgs() << formatv(
             "BOLT: mapping cold fragment {0:x+} to {1:x+} with size {2:x+}\n",
             FF.getImageAddress(), FF.getAddress(), FF.getImageSize()));
-    MapSection(*ColdSection, FF.getAddress());
+    AssignAddress(*ColdSection, FF.getAddress());
 
     if (TooLarge)
       BC->deregisterSection(*ColdSection);
 
     NextAvailableAddress += FF.getImageSize();
   }
 
   // Add the new text section aggregating all existing code sections.
BinarySection &Section =
       BC->registerOrUpdateSection(getBOLTTextSectionName(),
                                   ELF::SHT_PROGBITS,
                                   Flags,
                                   /*Data=*/nullptr,
                                   NewTextSectionSize,
                                   16);
     Section.setOutputAddress(NewTextSectionStartAddress);
     Section.setOutputFileOffset(
-        getFileOffsetForAddress(NewTextSectionStartAddress));
+        getOutputFileOffsetForAddress(NewTextSectionStartAddress));
   }
 }
 
-void RewriteInstance::mapAllocatableSections(
-    BOLTLinker::SectionMapper MapSection) {
-  // Allocate read-only sections first, then writable sections.
-  enum : uint8_t { ST_READONLY, ST_READWRITE };
-  for (uint8_t SType = ST_READONLY; SType <= ST_READWRITE; ++SType) {
-    const uint64_t LastNextAvailableAddress = NextAvailableAddress;
-    if (SType == ST_READWRITE) {
-      // Align R+W segment to regular page size
-      NextAvailableAddress = alignTo(NextAvailableAddress, BC->RegularPageSize);
-      NewWritableSegmentAddress = NextAvailableAddress;
-    }
+void RewriteInstance::createNonLoadSegment(
+    const std::vector<BinarySection *> &Sections, const unsigned p_type,
+    const unsigned p_flags, const unsigned p_align) {
+  assert(p_type != ELF::PT_LOAD &&
+         "Called createNonLoadSegment with PT_LOAD type");
+  if (p_type == ELF::PT_GNU_STACK) {
+    assert(Sections.empty() && "Unexpected sections in GNU_STACK segment");
+    BC->OutputSegments.push_back(
+        ProgramHeader(ELF::PT_GNU_STACK, p_flags, 0, 0, 0, 0, 0, p_align));
+    return;
+  }
+  if (Sections.empty())
+    return;
+
+  bool Mapped = all_of(Sections, std::bind(&BinarySection::getOutputAddress,
+                                           std::placeholders::_1)) &&
+                all_of(Sections, std::bind(&BinarySection::getOutputFileOffset,
+                                           std::placeholders::_1));
+  assert(Mapped && "attempt to create non-load segment with unmapped sections");
+  (void)Mapped;
+  const uint64_t p_vaddr = Sections.front()->getOutputAddress();
+  const uint64_t p_memsz = Sections.back()->getOutputAddress() +
+                           Sections.back()->getOutputSize() - p_vaddr;
+  const uint64_t p_filesz =
+      p_memsz - Sections.back()->isVirtual() * Sections.back()->getOutputSize();
+  const uint64_t p_offset = Sections.front()->getOutputFileOffset();
+  ProgramHeader Result(p_type, p_flags, p_offset, p_vaddr, p_vaddr, p_filesz,
+                       p_memsz, p_align);
+
+  if (p_type == ELF::PT_INTERP) {
+    assert(BC->OutputSegments.size() && "PHDR segment expected");
+    // Put INTERP after PHDR because it must precede loadable segments
+    BC->OutputSegments.insert(BC->OutputSegments.begin() + 1, Result);
+  } else {
+    BC->OutputSegments.push_back(Result);
+  }
 
-    for (BinarySection &Section : BC->allocatableSections()) {
-      if (!Section.hasValidSectionID())
-        continue;
-
-      if (Section.isWritable() == (SType == ST_READONLY))
-        continue;
+void RewriteInstance::mapSection(BinarySection &Section) {
+  assert(!Section.getOutputAddress());
+  if (!Section.isTBSS())
+    NextAvailableAddress =
+        alignTo(NextAvailableAddress, Section.getAlignment());
 
-      if (Section.getOutputAddress()) {
-        LLVM_DEBUG({
-          dbgs() << "BOLT-DEBUG: section " << Section.getName()
-                 << " is already mapped at 0x"
-                 << Twine::utohexstr(Section.getOutputAddress()) << '\n';
-        });
-        continue;
-      }
+  Section.setOutputAddress(NextAvailableAddress);
+  Section.setOutputFileOffset(
+      getOutputFileOffsetForAddress(Section.getOutputAddress()));
 
-      if (Section.hasSectionRef()) {
-        LLVM_DEBUG({
-          dbgs() << "BOLT-DEBUG: mapping original section " << Section.getName()
-                 << " to 0x" << Twine::utohexstr(Section.getAddress()) << '\n';
-        });
-        Section.setOutputAddress(Section.getAddress());
-        Section.setOutputFileOffset(Section.getInputFileOffset());
-        MapSection(Section, Section.getAddress());
-      } else {
-        NextAvailableAddress =
-            alignTo(NextAvailableAddress, Section.getAlignment());
-        LLVM_DEBUG({
-          dbgs() << "BOLT: mapping section " << Section.getName() << " (0x"
-                 << Twine::utohexstr(Section.getAllocAddress()) << ") to 0x"
-                 << Twine::utohexstr(NextAvailableAddress) << ":0x"
-                 << Twine::utohexstr(NextAvailableAddress +
-                                     Section.getOutputSize())
-                 << '\n';
-        });
+  if (!Section.isTBSS())
+    NextAvailableAddress += Section.getOutputSize();
+  Section.setIsFinalized();
+    std::string What = Section.hasSectionRef() ? "original" : "new";
+    dbgs() << formatv(
+        "BOLT-DEBUG: mapping {0} section {1} ({2:x}) to {3:x}:{4:x}\n", What,
+        Section.getName(), Section.getAllocAddress(),
+        Section.getOutputAddress(),
+        Section.getOutputAddress() + Section.getOutputSize());
+  // Hugify: Additional huge page from right side due to
+  // weird ASLR mapping addresses (4KB aligned)
+  if (opts::Hugify && Section.getOutputName() == BC->getMainCodeSectionName())
+}
+
+uint64_t
+RewriteInstance::mapSectionGroup(const std::vector<BinarySection *> &Sections,
+                                 BOLTLinker::SectionMapper AssignAddress) {
+  uint64_t NobitsSize = 0;
+  for (BinarySection *Section : Sections) {
+    if (Section->getOutputAddress()) {
+        dbgs() << formatv(
+            "BOLT-DEBUG: section {0} is already mapped at {1:x}\n",
+            Section->getName(), Section->getOutputAddress());
+      continue;
+    }
+    // .eh_frame_hdr address and size are assigned at mapEhFrames
+    if (Section->getName() == getEHFrameHeaderSectionName())
+      continue;
+    if (Section->getName().endswith(getEHFrameSectionName())) {
+      mapEhFrameAndHeader(AssignAddress);
+      continue;
+    }
 
-        MapSection(Section, NextAvailableAddress);
-        Section.setOutputAddress(NextAvailableAddress);
-        Section.setOutputFileOffset(
-            getFileOffsetForAddress(NextAvailableAddress));
-
-        NextAvailableAddress += Section.getOutputSize();
-      }
-    }
+    mapSection(*Section);
+    if (Section->isVirtual() && !Section->isTLS())
+      NobitsSize += Section->getOutputSize();
+    if (Section->hasValidSectionID())
+      AssignAddress(*Section, Section->getOutputAddress());
+  }
+  return NobitsSize;
+}
+void RewriteInstance::createLoadSegment(
+    const std::vector<BinarySection *> &Sections,
+    BOLTLinker::SectionMapper AssignAddress, const unsigned p_flags,
+    const unsigned p_align, const std::optional<uint64_t> ForceAddress) {
+
+  if (Sections.empty())
+    return;
+  if (!ForceAddress) {
+    NextAvailableAddress = alignTo(NextAvailableAddress, p_align);
+    if (BC->OutputSegments.size() && BC->OutputSegments.back().isLOAD()) {
+      const ProgramHeader &PrevSegment = BC->OutputSegments.back();
+      NextAvailableAddress = alignTo(NextAvailableAddress, PrevSegment.p_align);
+      const uint64_t Align =
+          Sections.size() ? Sections.front()->getAlignment() : 8;
+      const uint64_t SegmentStartOffset =
+          alignTo(PrevSegment.p_offset + PrevSegment.p_memsz, Align);
+      NextAvailableAddress += SegmentStartOffset & (p_align - 1);
+      BC->OutputAddressToOffsetMap[NextAvailableAddress] = SegmentStartOffset;
+    }
+  }
+  uint64_t p_vaddr = NextAvailableAddress;
+  uint64_t p_offset = getOutputFileOffsetForAddress(NextAvailableAddress);
+  LLVM_DEBUG({ dbgs() << "BOLT-DEBUG: creating LOAD segment\n"; });
+  const uint64_t NobitsSize = mapSectionGroup(Sections, AssignAddress);
+  uint64_t p_memsz = NextAvailableAddress - p_vaddr;
+  if (!p_memsz)
+    return;
+  if (ForceAddress) {
+    p_memsz += p_vaddr - *ForceAddress;
+    p_offset = getOutputFileOffsetForAddress(*ForceAddress);
+    p_vaddr = *ForceAddress;
+  }
+  uint64_t p_filesz = p_memsz - NobitsSize;
+  ProgramHeader Result = ProgramHeader(ELF::PT_LOAD, p_flags, p_offset, p_vaddr,
+                                       p_vaddr, p_filesz, p_memsz, p_align);
+  BC->OutputSegments.push_back(Result);
+}
+
+std::vector<BinarySection *>
+RewriteInstance::getSectionsForSegment(const ProgramHeader &Phdr,
+                                       bool IncludeNew) {
+  std::vector<BinarySection *> Result;
+  std::vector<BinarySection *> Nobits;
+  for (BinarySection &Section : BC->allocatableSections()) {
+    if (Phdr.isTLS() > Section.isTLS())
+      continue;
+    if (Phdr.contains(Section) && !shouldStrip(Section)) {
+      if (Section.isVirtual() && !Section.isTLS())
+        Nobits.push_back(&Section);
+      else
+        Result.push_back(&Section);
 
-    if (SType == ST_READONLY) {
-      if (PHDRTableAddress) {
-        // Segment size includes the size of the PHDR area.
-        NewTextSegmentSize = NextAvailableAddress - PHDRTableAddress;
-      } else {
-        // Existing PHDR table would be updated.
-        NewTextSegmentSize = NextAvailableAddress - NewTextSegmentAddress;
-      }
-    } else if (SType == ST_READWRITE) {
-      NewWritableSegmentSize = NextAvailableAddress - NewWritableSegmentAddress;
-      // Restore NextAvailableAddress if no new writable sections
-      if (!NewWritableSegmentSize)
-        NextAvailableAddress = LastNextAvailableAddress;
+  auto GetSectionIt = [&Result](StringRef Name) {
+    return std::find_if(
+        Result.begin(), Result.end(),
+        [Name](BinarySection *Sec) { return Sec->getOutputName() == Name; });
+  };
+
+  if (IncludeNew && Phdr.isLOAD()) {
+    std::vector<BinarySection *> Extra = BC->getNewSectionsByFlags(
+        Phdr.getSectionFlags(), /*ROwithRX*/ !HasReadOnlySegment);
+    // We need to put .text.cold after .text
+    auto PosForNewSections = Result.end();
+    if (Phdr.isExec()) {
+      PosForNewSections = GetSectionIt(".text");
+      if (PosForNewSections != Result.end())
+        ++PosForNewSections;
+    }
+    Result.insert(PosForNewSections, Extra.begin(), Extra.end());
+  }
+  if (opts::Rewrite && Phdr.isExec()) {
+    // Put .plt before .text because:
+    // - it makes clear where PLT will be relative to .text, which simplifies
+    // stub insertion for AArch64. Without it we can't decide where to insert
+    // stubs because we don't know the final binary layout before linking.
+    // - unless --hot-functions-at-end is used, PLT comes just before hot text
+    // section which increases locality.
+    auto PltIt = GetSectionIt(".plt");
+    if (PltIt != Result.end()) {
+      BinarySection *Plt = *PltIt;
+      Result.erase(PltIt);
+      auto TextIt = GetSectionIt(".text");
+      assert(TextIt != Result.end() && "No .text section!");
+      Result.insert(TextIt, Plt);
+    }
+  }
+  Result.insert(Result.end(), Nobits.begin(), Nobits.end());
+  return Result;
+}
+void RewriteInstance::mapNonLoadableSegments() {
+  for (const ProgramHeader &Phdr : BC->nonLoadableSegments()) {
+    // PHDR is created earlier
+    if (Phdr.p_type == ELF::PT_PHDR)
+      continue;
+    if (!opts::Rewrite && Phdr.p_type == ELF::PT_GNU_EH_FRAME) {
+      BinarySection *EHFrameHeader = getSection(getEHFrameHeaderSectionName());
+      assert(EHFrameHeader && "Cannot find .eh_frame_hdr for PT_GNU_EH_FRAME!");
+      createNonLoadSegment({EHFrameHeader}, Phdr.p_type, Phdr.p_flags,
+                           Phdr.p_align);
+      createNonLoadSegment(getSectionsForSegment(Phdr), Phdr.p_type,
+                           Phdr.p_flags, Phdr.p_align);
     }
   }
 }
 
-void RewriteInstance::updateOutputValues(const MCAsmLayout &Layout) {
-  for (BinaryFunction *Function : BC->getAllBinaryFunctions())
-    Function->updateOutputValues(Layout);
-}
+void RewriteInstance::mapLoadableSegments(
+    BOLTLinker::SectionMapper AssignAddress) {
+  BC->deregisterUnusedSections();
 
-void RewriteInstance::patchELFPHDRTable() {
-  auto ELF64LEFile = cast<ELF64LEObjectFile>(InputFile);
-  const ELFFile<ELF64LE> &Obj = ELF64LEFile->getELFFile();
-  raw_fd_ostream &OS = Out->os();
+  PHDRTableOffset = 0x40;
+  NextAvailableAddress = BaseAddress + PHDRTableOffset;
+  PHDRTableAddress = NextAvailableAddress;
+  assert(BC->OutputAddressToOffsetMap.empty() && "Unexpected mapping!");
 
-  // Write/re-write program headers.
-  Phnum = Obj.getHeader().e_phnum;
-  if (PHDRTableOffset) {
-    // Writing new pheader table and adding one new entry for R+X segment.
-    Phnum += 1;
-    if (NewWritableSegmentSize) {
-      // Adding one more entry for R+W segment.
-      Phnum += 1;
-    }
+  BC->OutputAddressToOffsetMap[BaseAddress] = 0;
+  // add PHDR and reserve space for RE/RW segments for runtime library
+  uint64_t Phnum = BC->InputSegments.size() + !HasProgramHeaderSegment +
+                   (!!BC->getRuntimeLibrary()) * 2;
+  uint64_t PHDRTableSize = Phnum * sizeof(ELF64LE::Phdr);
+  BC->MaxPHDRSize = PHDRTableSize;
+  BC->OutputSegments.push_back(
+      ProgramHeader(ELF::PT_PHDR, ELF::PF_R, PHDRTableOffset, PHDRTableAddress,
+                    PHDRTableAddress, PHDRTableSize, PHDRTableSize, 0x8));
+  NextAvailableAddress += PHDRTableSize;
+
+  for (const ProgramHeader &Phdr : BC->loadableSegments()) {
+
+    const uint64_t Align = Phdr.isExec() ? BC->PageAlign : Phdr.p_align;
+    bool IsFirstLoad = (Phdr.p_offset == 0);
+    createLoadSegment(getSectionsForSegment(Phdr), AssignAddress, Phdr.p_flags,
+                      Align,
+                      /*ForceAddress=*/
+                      IsFirstLoad ? std::optional(BaseAddress) : std::nullopt);
+  }
+}
+void RewriteInstance::copySegment(const ProgramHeader &Segment,
+                                  BOLTLinker::SectionMapper AssignAddress) {
+  BC->OutputSegments.push_back(Segment);
+  BC->OutputAddressToOffsetMap[Segment.p_vaddr] = Segment.p_offset;
+  for (BinarySection *Section : getSectionsForSegment(Segment, false)) {
+
+    Section->setOutputAddress(Section->getAddress());
+    Section->setOutputFileOffset(Section->getInputFileOffset());
+    if (Section->hasValidSectionID())
+      AssignAddress(*Section, Section->getOutputAddress());
+    Section->setIsFinalized();
+}
+
+void RewriteInstance::mapRuntimeLibrary(
+    BOLTLinker::SectionMapper AssignAddress) {
+  if (opts::Rewrite) {
+    // if we are rewriting, we can afford two segments with proper flags.
+    createLoadSegment(
+        BC->getNewSectionsByFlags(ELF::SHF_ALLOC | ELF::SHF_EXECINSTR,
+                                  /*ROwithRX*/ true),
+        AssignAddress, ELF::PF_R | ELF::PF_X, BC->RegularPageSize);
+    createLoadSegment(
+        BC->getNewSectionsByFlags(ELF::SHF_ALLOC | ELF::SHF_WRITE),
+        AssignAddress, ELF::PF_R | ELF::PF_W, BC->RegularPageSize);
   } else {
-    assert(!PHDRTableAddress && "unexpected address for program header table");
-    PHDRTableOffset = Obj.getHeader().e_phoff;
-    if (NewWritableSegmentSize) {
-      errs() << "Unable to add writable segment with UseGnuStack option\n";
-      exit(1);
-    }
-  }
+    auto NewSegmentContents = BC->getAllNewSections();
+    unsigned Flags = ELF::PF_R | ELF::PF_X | ELF::PF_W;
+    createLoadSegment(NewSegmentContents, AssignAddress, Flags, BC->PageAlign,
+                      PHDRTableAddress);
 
-  // NOTE Currently .eh_frame_hdr appends to the last segment, recalculate
-  // last segments size based on the NextAvailableAddress variable.
-  if (!NewWritableSegmentSize) {
-    if (PHDRTableAddress)
-      NewTextSegmentSize = NextAvailableAddress - PHDRTableAddress;
-    else
-      NewTextSegmentSize = NextAvailableAddress - NewTextSegmentAddress;
-  } else {
-    NewWritableSegmentSize = NextAvailableAddress - NewWritableSegmentAddress;
-  }
+void RewriteInstance::updateOutputValues(const MCAsmLayout &Layout) {
+  for (BinaryFunction *Function : BC->getAllBinaryFunctions())
+    Function->updateOutputValues(Layout);
 
+void RewriteInstance::writeELFPHDRTable() {
+  raw_fd_ostream &OS = Out->os();
+  assert(PHDRTableOffset && "No PHDR table offset!");
+  assert(BC->OutputSegments.size() && "Empty PHDR!");
+  assert(BC->OutputSegments[0].p_type == ELF::PT_PHDR && "No PHDR segment!");
   OS.seek(PHDRTableOffset);
-
-  bool ModdedGnuStack = false;
-  (void)ModdedGnuStack;
-  bool AddedSegment = false;
-  (void)AddedSegment;
-
-  auto createNewTextPhdr = [&]() {
-    ELF64LEPhdrTy NewPhdr;
-    NewPhdr.p_type = ELF::PT_LOAD;
-    if (PHDRTableAddress) {
-      NewPhdr.p_offset = PHDRTableOffset;
-      NewPhdr.p_vaddr = PHDRTableAddress;
-      NewPhdr.p_paddr = PHDRTableAddress;
-    } else {
-      NewPhdr.p_offset = NewTextSegmentOffset;
-      NewPhdr.p_vaddr = NewTextSegmentAddress;
-      NewPhdr.p_paddr = NewTextSegmentAddress;
-    }
-    NewPhdr.p_filesz = NewTextSegmentSize;
-    NewPhdr.p_memsz = NewTextSegmentSize;
-    NewPhdr.p_flags = ELF::PF_X | ELF::PF_R;
-    // FIXME: Currently instrumentation is experimental and the runtime data
-    // is emitted with code, thus everything needs to be writable
-    if (opts::Instrument)
-      NewPhdr.p_flags |= ELF::PF_W;
-    NewPhdr.p_align = BC->PageAlign;
-
-    return NewPhdr;
-  };
-
-  auto createNewWritableSectionsPhdr = [&]() {
-    ELF64LEPhdrTy NewPhdr;
-    NewPhdr.p_type = ELF::PT_LOAD;
-    NewPhdr.p_offset = getFileOffsetForAddress(NewWritableSegmentAddress);
-    NewPhdr.p_vaddr = NewWritableSegmentAddress;
-    NewPhdr.p_paddr = NewWritableSegmentAddress;
-    NewPhdr.p_filesz = NewWritableSegmentSize;
-    NewPhdr.p_memsz = NewWritableSegmentSize;
-    NewPhdr.p_align = BC->RegularPageSize;
-    NewPhdr.p_flags = ELF::PF_R | ELF::PF_W;
-    return NewPhdr;
-  };
-
-  // Copy existing program headers with modifications.
-  for (const ELF64LE::Phdr &Phdr : cantFail(Obj.program_headers())) {
-    ELF64LE::Phdr NewPhdr = Phdr;
-    if (PHDRTableAddress && Phdr.p_type == ELF::PT_PHDR) {
-      NewPhdr.p_offset = PHDRTableOffset;
-      NewPhdr.p_vaddr = PHDRTableAddress;
-      NewPhdr.p_paddr = PHDRTableAddress;
-      NewPhdr.p_filesz = sizeof(NewPhdr) * Phnum;
-      NewPhdr.p_memsz = sizeof(NewPhdr) * Phnum;
-    } else if (Phdr.p_type == ELF::PT_GNU_EH_FRAME) {
-      ErrorOr<BinarySection &> EHFrameHdrSec =
-          BC->getUniqueSectionByName(getNewSecPrefix() + ".eh_frame_hdr");
-      if (EHFrameHdrSec && EHFrameHdrSec->isAllocatable() &&
-          EHFrameHdrSec->isFinalized()) {
-        NewPhdr.p_offset = EHFrameHdrSec->getOutputFileOffset();
-        NewPhdr.p_vaddr = EHFrameHdrSec->getOutputAddress();
-        NewPhdr.p_paddr = EHFrameHdrSec->getOutputAddress();
-        NewPhdr.p_filesz = EHFrameHdrSec->getOutputSize();
-        NewPhdr.p_memsz = EHFrameHdrSec->getOutputSize();
-      }
-    } else if (opts::UseGnuStack && Phdr.p_type == ELF::PT_GNU_STACK) {
-      NewPhdr = createNewTextPhdr();
-      ModdedGnuStack = true;
-    } else if (!opts::UseGnuStack && Phdr.p_type == ELF::PT_DYNAMIC) {
-      // Insert the new header before DYNAMIC.
-      ELF64LE::Phdr NewTextPhdr = createNewTextPhdr();
-      OS.write(reinterpret_cast<const char *>(&NewTextPhdr),
-               sizeof(NewTextPhdr));
-      if (NewWritableSegmentSize) {
-        ELF64LEPhdrTy NewWritablePhdr = createNewWritableSectionsPhdr();
-        OS.write(reinterpret_cast<const char *>(&NewWritablePhdr),
-                 sizeof(NewWritablePhdr));
-      }
-      AddedSegment = true;
-    }
-    OS.write(reinterpret_cast<const char *>(&NewPhdr), sizeof(NewPhdr));
-  }
-
-  if (!opts::UseGnuStack && !AddedSegment) {
-    // Append the new header to the end of the table.
-    ELF64LE::Phdr NewTextPhdr = createNewTextPhdr();
-    OS.write(reinterpret_cast<const char *>(&NewTextPhdr), sizeof(NewTextPhdr));
-    if (NewWritableSegmentSize) {
-      ELF64LEPhdrTy NewWritablePhdr = createNewWritableSectionsPhdr();
-      OS.write(reinterpret_cast<const char *>(&NewWritablePhdr),
-               sizeof(NewWritablePhdr));
-    }
-  }
-
-  assert((!opts::UseGnuStack || ModdedGnuStack) &&
-         "could not find GNU_STACK program header to modify");
+  uint64_t PHDRTableSize = BC->OutputSegments.size() * sizeof(ELF64LE::Phdr);
+  assert(PHDRTableSize <= BC->MaxPHDRSize && "Exceeded MaxPHDRSize!");
+  BC->OutputSegments[0].p_filesz = PHDRTableSize;
+  BC->OutputSegments[0].p_memsz = PHDRTableSize;
+  for (const auto &Phdr : BC->OutputSegments) {
+    ELF64LE::Phdr PhdrToWrite(Phdr);
+    OS.write(reinterpret_cast<const char *>(&PhdrToWrite), sizeof(PhdrToWrite));
+  return;
 }
 
 namespace {
 
 /// Write padding to \p OS such that its current \p Offset becomes aligned
 /// at \p Alignment. Return new (aligned) offset.
 uint64_t appendPadding(raw_pwrite_stream &OS, uint64_t Offset,
                        uint64_t Alignment) {

 
 }
 
 void RewriteInstance::rewriteNoteSections() {
   auto ELF64LEFile = cast<ELF64LEObjectFile>(InputFile);
   const ELFFile<ELF64LE> &Obj = ELF64LEFile->getELFFile();
   raw_fd_ostream &OS = Out->os();
 
-  uint64_t NextAvailableOffset = getFileOffsetForAddress(NextAvailableAddress);
+  uint64_t NextAvailableOffset =
+      getOutputFileOffsetForAddress(NextAvailableAddress);
   assert(NextAvailableOffset >= FirstNonAllocatableOffset &&
          "next available offset calculation failure");
   OS.seek(NextAvailableOffset);
 
   // Copy over non-allocatable section contents and update file offsets.
   for (const ELF64LE::Shdr &Section : cantFail(Obj.sections())) {
     if (Section.sh_type == ELF::SHT_NULL)
       continue;
if (!willOverwriteSection(SectionName)) {
         Size = appendPadding(OS, Size, Section.sh_addralign);
       }
     }
 
     // Perform section post-processing.
     assert(BSec->getAlignment() <= Section.sh_addralign &&
            "alignment exceeds value in file");
 
-    if (BSec->getAllocAddress()) {
+    if (BSec->getAllocAddress() && !DataWritten) {
       assert(!DataWritten && "Writing section twice.");
       (void)DataWritten;
       SectionData = BSec->getOutputData();
 
       LLVM_DEBUG(dbgs() << "BOLT-DEBUG: " << (Size ? "appending" : "writing")
                         << " contents to section " << SectionName << '\n');
       OS.write(reinterpret_cast<char *>(SectionData), BSec->getOutputSize());
       Size += BSec->getOutputSize();
for (const ELF64LE::Shdr &Section : cantFail(Obj.sections())) {
     NewSection.setOutputAddress(0);
     NewSection.setOutputFileOffset(NextAvailableOffset);
 
     NextAvailableOffset += Size;
   }
 
   // Write new note sections.
   for (BinarySection &Section : BC->nonAllocatableSections()) {
-    if (Section.getOutputFileOffset() || !Section.getAllocAddress())
+    if (Section.getOutputFileOffset() || !Section.getAllocAddress() ||
+        shouldStrip(Section))
       continue;
 
     assert(!Section.hasPendingRelocations() && "cannot have pending relocs");
 
     NextAvailableOffset =
         appendPadding(OS, NextAvailableOffset, Section.getAlignment());
     Section.setOutputFileOffset(NextAvailableOffset);
 
     LLVM_DEBUG(
         dbgs() << "BOLT-DEBUG: writing out new section " << Section.getName()
                << " of size " << Section.getOutputSize() << " at offset 0x"
                << Twine::utohexstr(Section.getOutputFileOffset()) << '\n');
 
     OS.write(Section.getOutputContents().data(), Section.getOutputSize());
     NextAvailableOffset += Section.getOutputSize();
   }
 }
 
 template <typename ELFT>
 void RewriteInstance::finalizeSectionStringTable(ELFObjectFile<ELFT> *File) {
   // Pre-populate section header string table.
   for (const BinarySection &Section : BC->sections())
-    if (!Section.isAnonymous())
+    if (!Section.isAnonymous()) {
       SHStrTab.add(Section.getOutputName());
+      LLVM_DEBUG(dbgs() << "BOLT-DEBUG: adding " << Section.getOutputName()
+                        << " to shstrtab\n";);
+    }
+
   SHStrTab.finalize();
 
   const size_t SHStrTabSize = SHStrTab.getSize();
   uint8_t *DataCopy = new uint8_t[SHStrTabSize];
   memset(DataCopy, 0, SHStrTabSize);
   SHStrTab.write(DataCopy);
   BC->registerOrUpdateNoteSection(".shstrtab",
                                   DataCopy,
if (isDebugSection(SectionName) && !opts::UpdateDebugSections)
     return true;
 
   // Strip symtab section if needed
   if (opts::RemoveSymtab && Section.sh_type == ELF::SHT_SYMTAB)
     return true;
 
   return false;
 }
+bool RewriteInstance::shouldStrip(const BinarySection &Section) {
+  // Strip non-allocatable relocation sections.
+  if (!(Section.getELFFlags() & ELF::SHF_ALLOC) &&
+      Section.getELFType() == ELF::SHT_RELA)
+    return true;
+
+  // Strip debug sections if not updating them.
+  if (isDebugSection(Section.getName()) && !opts::UpdateDebugSections)
+    return true;
+
+  // Strip symtab section if needed
+  if (opts::RemoveSymtab && Section.getELFType() == ELF::SHT_SYMTAB)
+    return true;
+
+  return false;
+}
 
 template <typename ELFT>
 std::vector<typename object::ELFObjectFile<ELFT>::Elf_Shdr>
 RewriteInstance::getOutputSections(ELFObjectFile<ELFT> *File,
                                    std::vector<uint32_t> &NewSectionIndex) {
   using ELFShdrTy = typename ELFObjectFile<ELFT>::Elf_Shdr;
   const ELFFile<ELFT> &Obj = File->getELFFile();
-  typename ELFT::ShdrRange Sections = cantFail(Obj.sections());
+  typename ELFT::ShdrRange InputSections = cantFail(Obj.sections());
 
-  // Keep track of section header entries attached to the corresponding section.
-  std::vector<std::pair<BinarySection *, ELFShdrTy>> OutputSections;
-  auto addSection = [&](const ELFShdrTy &Section, BinarySection *BinSec) {
+  // Keep track of section header entries together with their name.
+  std::vector<std::pair<std::string, ELFShdrTy>> OutputSections;
+  auto addSection = [&](const std::string &Name, const ELFShdrTy &Section) {
     ELFShdrTy NewSection = Section;
-    NewSection.sh_name = SHStrTab.getOffset(BinSec->getOutputName());
-    OutputSections.emplace_back(BinSec, std::move(NewSection));
+    NewSection.sh_name = SHStrTab.getOffset(Name);
+    OutputSections.emplace_back(Name, std::move(NewSection));
   };
 
-  // Copy over entries for original allocatable sections using modified name.
-  for (const ELFShdrTy &Section : Sections) {
-    // Always ignore this section.
-    if (Section.sh_type == ELF::SHT_NULL) {
-      OutputSections.emplace_back(nullptr, Section);
-      continue;
-    }
-
-    if (!(Section.sh_flags & ELF::SHF_ALLOC))
-      continue;
-
-    SectionRef SecRef = File->toSectionRef(&Section);
-    BinarySection *BinSec = BC->getSectionForSectionRef(SecRef);
-    assert(BinSec && "Matching BinarySection should exist.");
+  // NULL Section
+  OutputSections.emplace_back("", ELFShdrTy{});
 
-    addSection(Section, BinSec);
-  }
-
-  for (BinarySection &Section : BC->allocatableSections()) {
-    if (!Section.isFinalized())
-      continue;
+  // TODO: Reduce number of for loops
+  for (const BinarySection &Section : BC->allocatableSections()) {
 
-    if (Section.hasSectionRef() || Section.isAnonymous()) {
+    if (Section.isAnonymous() || !Section.isFinalized()) {
       if (opts::Verbosity)
         outs() << "BOLT-INFO: not writing section header for section "
                << Section.getOutputName() << '\n';
       continue;
     }
 
     if (opts::Verbosity >= 1)
-      outs() << "BOLT-INFO: writing section header for "
-             << Section.getOutputName() << '\n';
+      outs() << "BOLT-INFO: writing section header for " << Section.getName()
+             << '\n';
     ELFShdrTy NewSection;
-    NewSection.sh_type = ELF::SHT_PROGBITS;
+    NewSection.sh_type = Section.getELFType();
     NewSection.sh_addr = Section.getOutputAddress();
     NewSection.sh_offset = Section.getOutputFileOffset();
     NewSection.sh_size = Section.getOutputSize();
     NewSection.sh_entsize = 0;
     NewSection.sh_flags = Section.getELFFlags();
     NewSection.sh_link = 0;
     NewSection.sh_info = 0;
     NewSection.sh_addralign = Section.getAlignment();
-    addSection(NewSection, &Section);
+    addSection(std::string(Section.getOutputName()), NewSection);
   }
 
   // Sort all allocatable sections by their offset.
-  llvm::stable_sort(OutputSections, [](const auto &A, const auto &B) {
+  llvm::stable_sort(OutputSections,
+                    [](const std::pair<std::string, ELFShdrTy> &A,
+                       const std::pair<std::string, ELFShdrTy> &B) {
                       return A.second.sh_offset < B.second.sh_offset;
                     });
 
   // Fix section sizes to prevent overlapping.
   ELFShdrTy *PrevSection = nullptr;
-  BinarySection *PrevBinSec = nullptr;
+  StringRef PrevSectionName;
   for (auto &SectionKV : OutputSections) {
     ELFShdrTy &Section = SectionKV.second;
 
     // TBSS section does not take file or memory space. Ignore it for layout
     // purposes.
     if (Section.sh_type == ELF::SHT_NOBITS && (Section.sh_flags & ELF::SHF_TLS))
       continue;
 
     if (PrevSection &&
         PrevSection->sh_addr + PrevSection->sh_size > Section.sh_addr) {
       if (opts::Verbosity > 1)
-        outs() << "BOLT-INFO: adjusting size for section "
-               << PrevBinSec->getOutputName() << '\n';
+        outs() << "BOLT-INFO: adjusting size for section " << PrevSectionName
+               << '\n';
       PrevSection->sh_size = Section.sh_addr > PrevSection->sh_addr
                                  ? Section.sh_addr - PrevSection->sh_addr
                                  : 0;
     }
 
     PrevSection = &Section;
-    PrevBinSec = SectionKV.first;
+    PrevSectionName = SectionKV.first;
   }
 
   uint64_t LastFileOffset = 0;
 
   // Copy over entries for non-allocatable sections performing necessary
   // adjustments.
-  for (const ELFShdrTy &Section : Sections) {
+  for (const ELFShdrTy &Section : InputSections) {
     if (Section.sh_type == ELF::SHT_NULL)
       continue;
     if (Section.sh_flags & ELF::SHF_ALLOC)
       continue;
 
     StringRef SectionName =
         cantFail(Obj.getSectionName(Section), "cannot get section name");
 
     if (shouldStrip(Section, SectionName))
       continue;
 
-    SectionRef SecRef = File->toSectionRef(&Section);
-    BinarySection *BinSec = BC->getSectionForSectionRef(SecRef);
-    assert(BinSec && "Matching BinarySection should exist.");
+    ErrorOr<BinarySection &> BSec = BC->getUniqueSectionByName(SectionName);
+    assert(BSec && "missing section info for non-allocatable section");
 
     ELFShdrTy NewSection = Section;
-    NewSection.sh_offset = BinSec->getOutputFileOffset();
-    NewSection.sh_size = BinSec->getOutputSize();
+    NewSection.sh_offset = BSec->getOutputFileOffset();
+    NewSection.sh_size = BSec->getOutputSize();
 
     if (NewSection.sh_type == ELF::SHT_SYMTAB)
       NewSection.sh_info = NumLocalSymbols;
 
-    addSection(NewSection, BinSec);
+    addSection(std::string(SectionName), NewSection);
 
-    LastFileOffset = BinSec->getOutputFileOffset();
+    LastFileOffset = BSec->getOutputFileOffset();
   }
 
   // Create entries for new non-allocatable sections.
   for (BinarySection &Section : BC->nonAllocatableSections()) {
     if (Section.getOutputFileOffset() <= LastFileOffset)
       continue;
 
+    if (shouldStrip(Section))
+      continue;
+
     if (opts::Verbosity >= 1)
-      outs() << "BOLT-INFO: writing section header for "
-             << Section.getOutputName() << '\n';
+      outs() << "BOLT-INFO: writing section header for " << Section.getName()
+             << '\n';
 
     ELFShdrTy NewSection;
     NewSection.sh_type = Section.getELFType();
     NewSection.sh_addr = 0;
     NewSection.sh_offset = Section.getOutputFileOffset();
     NewSection.sh_size = Section.getOutputSize();
     NewSection.sh_entsize = 0;
     NewSection.sh_flags = Section.getELFFlags();
     NewSection.sh_link = 0;
     NewSection.sh_info = 0;
     NewSection.sh_addralign = Section.getAlignment();
 
-    addSection(NewSection, &Section);
+    addSection(std::string(Section.getName()), NewSection);
   }
 
   // Assign indices to sections.
   std::unordered_map<std::string, uint64_t> NameToIndex;
-  for (uint32_t Index = 1; Index < OutputSections.size(); ++Index)
-    OutputSections[Index].first->setIndex(Index);
+  for (uint32_t Index = 1; Index < OutputSections.size(); ++Index) {
+    const std::string &SectionName = OutputSections[Index].first;
+    NameToIndex[SectionName] = Index;
+    if (ErrorOr<BinarySection &> Section =
+            BC->getUniqueSectionByName(SectionName))
+      Section->setIndex(Index);
+  }
 
   // Update section index mapping
   NewSectionIndex.clear();
-  NewSectionIndex.resize(Sections.size(), 0);
-  for (const ELFShdrTy &Section : Sections) {
+  NewSectionIndex.resize(InputSections.size(), 0);
+  for (const ELFShdrTy &Section : InputSections) {
     if (Section.sh_type == ELF::SHT_NULL)
       continue;
 
-    size_t OrgIndex = std::distance(Sections.begin(), &Section);
-
-    SectionRef SecRef = File->toSectionRef(&Section);
-    BinarySection *BinSec = BC->getSectionForSectionRef(SecRef);
-    assert(BinSec && "BinarySection should exist for an input section.");
+    size_t OldIndex = std::distance(InputSections.begin(), &Section);
+    std::string SectionName =
+        std::string(cantFail(Obj.getSectionName(Section)));
 
     // Some sections are stripped
-    if (!BinSec->hasValidIndex())
+    if (!NameToIndex.count(SectionName))
       continue;
-
-    NewSectionIndex[OrgIndex] = BinSec->getIndex();
+    if (SectionName == ".rodata" || SectionName == ".text") {
+      std::string OrgSec = (getOrgSecPrefix() + SectionName).str();
+      // if we emitted new .rodata or .text, point the indices to the old ones
+      if (NameToIndex.find(OrgSec) != NameToIndex.end()) {
+        NewSectionIndex[OldIndex] = NameToIndex[OrgSec];
+        continue;
+      }
     }
+    NewSectionIndex[OldIndex] = NameToIndex[SectionName];
+  }
+  for (const ELFShdrTy &Section : InputSections) {
+    if (Section.sh_type == ELF::SHT_NULL)
+      continue;
 
+    std::string SectionName =
+        std::string(cantFail(Obj.getSectionName(Section)));
+
+    if (shouldStrip(Section, SectionName))
+      continue;
+    const uint64_t NewIndex = NameToIndex[SectionName];
+    if (Section.sh_link) {
+      auto &LinkSection = InputSections[Section.sh_link];
+      std::string LinkSectionName =
+          std::string(cantFail(Obj.getSectionName(LinkSection)));
+      OutputSections[NewIndex].second.sh_link = NameToIndex[LinkSectionName];
+    }
+    if (Section.sh_info) {
+      if (Section.sh_type == ELF::SHT_REL || Section.sh_type == ELF::SHT_RELA) {
+        auto &InfoSection = InputSections[Section.sh_info];
+        std::string InfoSectionName =
+            std::string(cantFail(Obj.getSectionName(InfoSection)));
+        OutputSections[NewIndex].second.sh_info = NameToIndex[InfoSectionName];
+      } else if (SectionName == ".symtab")
+        OutputSections[NewIndex].second.sh_info = NumLocalSymbols;
+      else
+        OutputSections[NewIndex].second.sh_info = Section.sh_info;
+    }
+    OutputSections[NewIndex].second.sh_entsize = Section.sh_entsize;
+  }
   std::vector<ELFShdrTy> SectionsOnly(OutputSections.size());
   llvm::copy(llvm::make_second_range(OutputSections), SectionsOnly.begin());
 
   return SectionsOnly;
 }
 
 // Rewrite section header table inserting new entries as needed. The sections
 // header table size itself may affect the offsets of other sections,
void RewriteInstance::patchELFSectionHeaderTable(ELFObjectFile<ELFT> *File) {
 
   // Align starting address for section header table. There's no architecutal
   // need to align this, it is just for pleasant human readability.
   uint64_t SHTOffset = OS.tell();
   SHTOffset = appendPadding(OS, SHTOffset, 16);
 
   // Write all section header entries while patching section references.
   for (ELFShdrTy &Section : OutputSections) {
-    Section.sh_link = NewSectionIndex[Section.sh_link];
-    if (Section.sh_type == ELF::SHT_REL || Section.sh_type == ELF::SHT_RELA) {
-      if (Section.sh_info)
-        Section.sh_info = NewSectionIndex[Section.sh_info];
-    }
     OS.write(reinterpret_cast<const char *>(&Section), sizeof(Section));
   }
 
   // Fix ELF header.
   ELFEhdrTy NewEhdr = Obj.getHeader();
 
   if (BC->HasRelocations) {
     if (RuntimeLibrary *RtLibrary = BC->getRuntimeLibrary())
       NewEhdr.e_entry = RtLibrary->getRuntimeStartAddress();
     else
       NewEhdr.e_entry = getNewFunctionAddress(NewEhdr.e_entry);
     assert((NewEhdr.e_entry || !Obj.getHeader().e_entry) &&
            "cannot find new address for entry point");
   }
   NewEhdr.e_phoff = PHDRTableOffset;
-  NewEhdr.e_phnum = Phnum;
+  NewEhdr.e_phnum = BC->OutputSegments.size();
   NewEhdr.e_shoff = SHTOffset;
   NewEhdr.e_shnum = OutputSections.size();
   NewEhdr.e_shstrndx = NewSectionIndex[NewEhdr.e_shstrndx];
   OS.pwrite(reinterpret_cast<const char *>(&NewEhdr), sizeof(NewEhdr), 0);
 }
 
 template <typename ELFT, typename WriteFuncTy, typename StrTabFuncTy>
 void RewriteInstance::updateELFSymbolTable(
if (Function && Symbol.getType() == ELF::STT_SECTION)
       Function = nullptr;
 
     // For non-dynamic symtab, make sure the symbol section matches that of
     // the function. It can mismatch e.g. if the symbol is a section marker
     // in which case we treat the symbol separately from the function.
     // For dynamic symbol table, the section index could be wrong on the input,
     // and its value is ignored by the runtime if it's different from
     // SHN_UNDEF and SHN_ABS.
-    if (!IsDynSym && Function &&
+    if (!IsDynSym && Function && Symbol.st_shndx &&
         Symbol.st_shndx !=
             Function->getOriginSection()->getSectionRef().getIndex())
       Function = nullptr;
 
     // Create a new symbol based on the existing symbol.
     ELFSymTy NewSymbol = Symbol;
 
     if (Function) {
       // If the symbol matched a function that was not emitted, update the
       // corresponding section index but otherwise leave it unchanged.
-      if (Function->isEmitted()) {
+      if (Function->isPLTFunction()) {
+        NewSymbol.st_value = Function->getOutputAddress();
+      } else if (Function->isEmitted()) {
         NewSymbol.st_value = Function->getOutputAddress();
         NewSymbol.st_size = Function->getOutputSize();
         NewSymbol.st_shndx = Function->getCodeSection()->getIndex();
       } else if (Symbol.st_shndx < ELF::SHN_LORESERVE) {
         NewSymbol.st_shndx = getNewSectionIndex(Symbol.st_shndx);
       }
 
       // Add new symbols to the symbol table if necessary.
if (Function) {
               "Cannot locate fragment containg secondary entrypoint");
           FF = Function->getLayout().fragment_begin();
         }
 
         NewSymbol.st_shndx =
             Function->getCodeSection(FF->getFragmentNum())->getIndex();
       } else {
         // Check if the symbol belongs to moved data object and update it.
-        BinaryData *BD = opts::ReorderData.empty()
-                             ? nullptr
-                             : BC->getBinaryDataAtAddress(Symbol.st_value);
+        BinaryData *BD = nullptr;
+        if (!opts::ReorderData.empty() || opts::Rewrite)
+          BD = BC->getBinaryDataAtAddress(Symbol.st_value);
+
         if (BD && BD->isMoved() && !BD->isJumpTable()) {
-          assert((!BD->getSize() || !Symbol.st_size ||
-                  Symbol.st_size == BD->getSize()) &&
-                 "sizes must match");
 
           BinarySection &OutputSection = BD->getOutputSection();
           assert(OutputSection.getIndex());
           LLVM_DEBUG(dbgs()
                      << "BOLT-DEBUG: moving " << BD->getName() << " from "
                      << *BC->getSectionNameForAddress(Symbol.st_value) << " ("
                      << Symbol.st_shndx << ") to " << OutputSection.getName()
                      << " (" << OutputSection.getIndex() << ")\n");
for (const ELFSymTy &Symbol : cantFail(Obj.symbols(&SymTabSection))) {
     auto updateSymbolValue = [&](const StringRef Name,
                                  std::optional<uint64_t> Value = std::nullopt) {
       NewSymbol.st_value = Value ? *Value : getNewValueForSymbol(Name);
       NewSymbol.st_shndx = ELF::SHN_ABS;
       outs() << "BOLT-INFO: setting " << Name << " to 0x"
              << Twine::utohexstr(NewSymbol.st_value) << '\n';
     };
 
+    auto SetToEnd = [&](BinarySection *Section) {
+      if (Section->getOutputName() == ".bolt.org.text") {
+        // move .text end symbol with text itself.
+        Section = &BC->getUniqueSectionByName(".text").get();
+      }
+      NewSymbol.st_value = Section->getOutputEndAddress();
+      NewSymbol.st_shndx = Section->getIndex();
+    };
+
     if (opts::HotText &&
         (*SymbolName == "__hot_start" || *SymbolName == "__hot_end")) {
       updateSymbolValue(*SymbolName);
       ++NumHotTextSymsUpdated;
     }
 
     if (opts::HotData && (*SymbolName == "__hot_data_start" ||
                           *SymbolName == "__hot_data_end")) {
       updateSymbolValue(*SymbolName);
       ++NumHotDataSymsUpdated;
     }
 
+    if (auto It = BC->EndSymbols.find(*SymbolName); It != BC->EndSymbols.end())
+      SetToEnd(It->second);
+
     if (*SymbolName == "_end")
       updateSymbolValue(*SymbolName, NextAvailableAddress);
 
     if (IsDynSym)
       Write((&Symbol - cantFail(Obj.symbols(&SymTabSection)).begin()) *
                 sizeof(ELFSymTy),
             NewSymbol);
     else
void RewriteInstance::patchELFSymTabs(ELFObjectFile<ELFT> *File) {
 
   // Compute a preview of how section indices will change after rewriting, so
   // we can properly update the symbol table based on new section indices.
   std::vector<uint32_t> NewSectionIndex;
   getOutputSections(File, NewSectionIndex);
 
   // Set pointer at the end of the output file, so we can pwrite old symbol
   // tables if we need to.
-  uint64_t NextAvailableOffset = getFileOffsetForAddress(NextAvailableAddress);
+  uint64_t NextAvailableOffset =
+      getOutputFileOffsetForAddress(NextAvailableAddress);
   assert(NextAvailableOffset >= FirstNonAllocatableOffset &&
          "next available offset calculation failure");
   Out->os().seek(NextAvailableOffset);
 
   // Update dynamic symbol table.
   const ELFShdrTy *DynSymSection = nullptr;
   for (const ELFShdrTy &Section : cantFail(Obj.sections())) {
     if (Section.sh_type == ELF::SHT_DYNSYM) {
       DynSymSection = &Section;
       break;
     }
   }
   assert((DynSymSection || BC->IsStaticExecutable) &&
          "dynamic symbol table expected");
+
   if (DynSymSection) {
+    auto Dynsym = BC->getUniqueSectionByName(".dynsym");
+    assert(Dynsym);
+    const uint64_t NewOffset = Dynsym->getOutputFileOffset();
+    assert(NewOffset);
     updateELFSymbolTable(
         File,
-        /*IsDynSym=*/true,
-        *DynSymSection,
-        NewSectionIndex,
-        [&](size_t Offset, const ELFSymTy &Sym) {
+        /*IsDynSym=*/true, *DynSymSection, NewSectionIndex,
+        [&, NewOffset](size_t Offset, const ELFSymTy &Sym) {
           Out->os().pwrite(reinterpret_cast<const char *>(&Sym),
-                           sizeof(ELFSymTy),
-                           DynSymSection->sh_offset + Offset);
+                           sizeof(ELFSymTy), NewOffset + Offset);
         },
         [](StringRef) -> size_t { return 0; });
   }
 
   if (opts::RemoveSymtab)
     return;
 
   // (re)create regular symbol table.
void RewriteInstance::patchELFAllocatableRelrSection(
   if (!DynamicRelrAddress)
     return;
 
   raw_fd_ostream &OS = Out->os();
   const uint8_t PSize = BC->AsmInfo->getCodePointerSize();
   const uint64_t MaxDelta = ((CHAR_BIT * DynamicRelrEntrySize) - 1) * PSize;
 
   auto FixAddend = [&](const BinarySection &Section, const Relocation &Rel) {
-    // Fix relocation symbol value in place if no static relocation found
-    // on the same address
-    if (Section.getRelocationAt(Rel.Offset))
-      return;
+    uint64_t Addend = 0;
 
+    if (const uint64_t EndSymValue = Section.getNewEndSymbolValue(Rel.Offset))
+      Addend = EndSymValue;
+
+    if (!Addend)
+      Addend = getNewFunctionOrDataAddress(Rel.Addend);
     // No fixup needed if symbol address was not changed
-    const uint64_t Addend = getNewFunctionOrDataAddress(Rel.Addend);
+
     if (!Addend)
       return;
 
     uint64_t FileOffset = Section.getOutputFileOffset();
     if (!FileOffset)
       FileOffset = Section.getInputFileOffset();
 
     FileOffset += Rel.Offset;
for (const Relocation &Rel : Section.dynamicRelocations()) {
       FixAddend(Section, Rel);
     }
   }
 
   ErrorOr<BinarySection &> Section =
       BC->getSectionForAddress(*DynamicRelrAddress);
   assert(Section && "cannot get .relr.dyn section");
   assert(Section->isRelr() && "Expected section to be SHT_RELR type");
-  uint64_t RelrDynOffset = Section->getInputFileOffset();
+  uint64_t RelrDynOffset = Section->getOutputFileOffset();
+  assert(RelrDynOffset && "No output offset for .relr.dyn");
+
   const uint64_t RelrDynEndOffset = RelrDynOffset + Section->getSize();
 
   auto WriteRelr = [&](uint64_t Value) {
     if (RelrDynOffset + DynamicRelrEntrySize > RelrDynEndOffset) {
       errs() << "BOLT-ERROR: Offset overflow for relr.dyn section\n";
       exit(1);
     }
 
RewriteInstance::patchELFAllocatableRelaSections(ELFObjectFile<ELFT> *File) {
 
   uint64_t RelDynOffset = 0, RelDynEndOffset = 0;
   uint64_t RelPltOffset = 0, RelPltEndOffset = 0;
 
   auto setSectionFileOffsets = [&](uint64_t Address, uint64_t &Start,
                                    uint64_t &End) {
     ErrorOr<BinarySection &> Section = BC->getSectionForAddress(Address);
     assert(Section && "cannot get relocation section");
-    Start = Section->getInputFileOffset();
-    End = Start + Section->getSize();
+    Start = Section->getOutputFileOffset();
+    End = Start + Section->getOutputSize();
   };
 
   if (!DynamicRelocationsAddress && !PLTRelocationsAddress)
     return;
 
   if (DynamicRelocationsAddress)
     setSectionFileOffsets(*DynamicRelocationsAddress, RelDynOffset,
                           RelDynEndOffset);
for (BinarySection &Section : BC->allocatableSections()) {
         uint64_t RelOffset =
             getNewFunctionOrDataAddress(SectionInputAddress + Rel.Offset);
 
         RelOffset = RelOffset == 0 ? SectionAddress + Rel.Offset : RelOffset;
         if (Rel.Symbol) {
           SymbolIdx = getOutputDynamicSymbolIndex(Symbol);
         } else {
           // Usually this case is used for R_*_(I)RELATIVE relocations
-          const uint64_t Address = getNewFunctionOrDataAddress(Addend);
+
+          // Check if it's end-of-section relocation first because they're
+          // tricky
+          uint64_t Address = Section.getNewEndSymbolValue(Rel.Offset);
+
+          if (!Address)
+            Address = getNewFunctionOrDataAddress(Rel.Addend);
+
           if (Address)
             Addend = Address;
         }
 
         NewRelA.setSymbolAndType(SymbolIdx, Rel.Type, EF.isMips64EL());
         NewRelA.r_offset = RelOffset;
         NewRelA.r_addend = Addend;
 
RewriteInstance::patchELFAllocatableRelaSections(ELFObjectFile<ELFT> *File) {
   };
 
   // Fill the rest of the sections with R_*_NONE relocations
   fillNone(RelDynOffset, RelDynEndOffset);
   fillNone(RelPltOffset, RelPltEndOffset);
 }
 
 template <typename ELFT>
-void RewriteInstance::patchELFGOT(ELFObjectFile<ELFT> *File) {
-  raw_fd_ostream &OS = Out->os();
-
-  SectionRef GOTSection;
-  for (const SectionRef &Section : File->sections()) {
-    StringRef SectionName = cantFail(Section.getName());
-    if (SectionName == ".got") {
-      GOTSection = Section;
-      break;
-    }
-  }
-  if (!GOTSection.getObject()) {
-    if (!BC->IsStaticExecutable)
-      errs() << "BOLT-INFO: no .got section found\n";
-    return;
-  }
-
-  StringRef GOTContents = cantFail(GOTSection.getContents());
-  for (const uint64_t *GOTEntry =
-           reinterpret_cast<const uint64_t *>(GOTContents.data());
-       GOTEntry < reinterpret_cast<const uint64_t *>(GOTContents.data() +
-                                                     GOTContents.size());
-       ++GOTEntry) {
-    if (uint64_t NewAddress = getNewFunctionAddress(*GOTEntry)) {
-      LLVM_DEBUG(dbgs() << "BOLT-DEBUG: patching GOT entry 0x"
-                        << Twine::utohexstr(*GOTEntry) << " with 0x"
-                        << Twine::utohexstr(NewAddress) << '\n');
-      OS.pwrite(reinterpret_cast<const char *>(&NewAddress), sizeof(NewAddress),
-                reinterpret_cast<const char *>(GOTEntry) -
-                    File->getData().data());
-    }
-  }
-}
-
-template <typename ELFT>
 void RewriteInstance::patchELFDynamic(ELFObjectFile<ELFT> *File) {
   if (BC->IsStaticExecutable)
     return;
 
   const ELFFile<ELFT> &Obj = File->getELFFile();
   raw_fd_ostream &OS = Out->os();
 
-  using Elf_Phdr = typename ELFFile<ELFT>::Elf_Phdr;
   using Elf_Dyn = typename ELFFile<ELFT>::Elf_Dyn;
 
   // Locate DYNAMIC by looking through program headers.
-  uint64_t DynamicOffset = 0;
-  const Elf_Phdr *DynamicPhdr = nullptr;
-  for (const Elf_Phdr &Phdr : cantFail(Obj.program_headers())) {
+  const ProgramHeader *DynamicPhdr = nullptr;
+  for (const ProgramHeader &Phdr : BC->InputSegments) {
     if (Phdr.p_type == ELF::PT_DYNAMIC) {
-      DynamicOffset = Phdr.p_offset;
       DynamicPhdr = &Phdr;
       assert(Phdr.p_memsz == Phdr.p_filesz && "dynamic sizes should match");
       break;
     }
   }
   assert(DynamicPhdr && "missing dynamic in ELF binary");
 
   bool ZNowSet = false;
 
+  auto DynamicSection = BC->getUniqueSectionByName(".dynamic");
+  assert(DynamicSection);
+  uint64_t NewDynamicOffset = DynamicSection->getOutputFileOffset();
+
   // Go through all dynamic entries and patch functions addresses with
   // new ones.
   typename ELFT::DynRange DynamicEntries =
       cantFail(Obj.dynamicEntries(), "error accessing dynamic table");
   auto DTB = DynamicEntries.begin();
   for (const Elf_Dyn &Dyn : DynamicEntries) {
     Elf_Dyn NewDE = Dyn;
     bool ShouldPatch = true;
case ELF::DT_FLAGS:
       }
       break;
     case ELF::DT_FLAGS_1:
       if (BC->RequiresZNow) {
         NewDE.d_un.d_val |= ELF::DF_1_NOW;
         ZNowSet = true;
       }
       break;
+    case ELF::DT_INIT_ARRAY:
+    case ELF::DT_FINI_ARRAY:
+    case ELF::DT_GNU_HASH:
+    case ELF::DT_SYMTAB:
+    case ELF::DT_STRTAB:
+    case ELF::DT_PLTGOT:
+    case ELF::DT_RELA:
+    case ELF::DT_RELR:
+    case ELF::DT_JMPREL:
+    case ELF::DT_VERNEED:
+    case ELF::DT_VERSYM: {
+      auto Section = BC->getSectionForAddress(Dyn.d_un.d_ptr);
+      assert(Section && "Cant'find section for dynamic entry");
+      assert(Section->getAddress() == NewDE.d_un.d_ptr &&
+             "Invalid address for dynamic entry");
+      assert(Section->getOutputAddress() &&
+             "No output address for section referred in .dynamic");
+      NewDE.d_un.d_ptr = Section->getOutputAddress();
+      break;
+    }
     }
     if (ShouldPatch)
       OS.pwrite(reinterpret_cast<const char *>(&NewDE), sizeof(NewDE),
-                DynamicOffset + (&Dyn - DTB) * sizeof(Dyn));
+                NewDynamicOffset + (&Dyn - DTB) * sizeof(Dyn));
   }
 
   if (BC->RequiresZNow && !ZNowSet) {
     errs() << "BOLT-ERROR: output binary requires immediate relocation "
               "processing which depends on DT_FLAGS or DT_FLAGS_1 presence in "
               ".dynamic. Please re-link the binary with -znow.\n";
     exit(1);
   }
 }
 
 template <typename ELFT>
 Error RewriteInstance::readELFDynamic(ELFObjectFile<ELFT> *File) {
   const ELFFile<ELFT> &Obj = File->getELFFile();
 
-  using Elf_Phdr = typename ELFFile<ELFT>::Elf_Phdr;
   using Elf_Dyn = typename ELFFile<ELFT>::Elf_Dyn;
 
   // Locate DYNAMIC by looking through program headers.
-  const Elf_Phdr *DynamicPhdr = nullptr;
-  for (const Elf_Phdr &Phdr : cantFail(Obj.program_headers())) {
+  const ProgramHeader *DynamicPhdr = 0;
+  for (const ProgramHeader &Phdr : BC->InputSegments) {
     if (Phdr.p_type == ELF::PT_DYNAMIC) {
       DynamicPhdr = &Phdr;
       break;
     }
   }
 
   if (!DynamicPhdr) {
     outs() << "BOLT-INFO: static input executable detected\n";

 uint64_t RewriteInstance::getNewFunctionOrDataAddress(uint64_t OldAddress) {
   if (uint64_t Function = getNewFunctionAddress(OldAddress))
     return Function;
 
   const BinaryData *BD = BC->getBinaryDataAtAddress(OldAddress);
   if (BD && BD->isMoved())
     return BD->getOutputAddress();
 
+  if (auto Section = BC->getSectionForAddress(OldAddress)) {
+    assert(Section->getOutputAddress());
+    return Section->getOutputAddress() + OldAddress - Section->getAddress();
+  }
   return 0;
 }
 
 void RewriteInstance::rewriteFile() {
   std::error_code EC;
   Out = std::make_unique<ToolOutputFile>(opts::OutputFilename, EC,
                                          sys::fs::OF_None);
   check_error(EC, "cannot create output executable file");
 
   raw_fd_ostream &OS = Out->os();
 
+  if (!opts::Rewrite) {
     // Copy allocatable part of the input.
     OS << InputFile->getData().substr(0, FirstNonAllocatableOffset);
-
+  }
+  // We obtain an asm-specific writer so that we can emit nops in an
+  // architecture-specific way at the end of the function.
+  std::unique_ptr<MCAsmBackend> MAB(
+      BC->TheTarget->createMCAsmBackend(*BC->STI, *BC->MRI, MCTargetOptions()));
   auto Streamer = BC->createStreamer(OS);
   // Make sure output stream has enough reserved space, otherwise
   // pwrite() will fail.
-  uint64_t Offset = OS.seek(getFileOffsetForAddress(NextAvailableAddress));
+  uint64_t Offset =
+      OS.seek(getOutputFileOffsetForAddress(NextAvailableAddress));
   (void)Offset;
-  assert(Offset == getFileOffsetForAddress(NextAvailableAddress) &&
+  assert(Offset == getOutputFileOffsetForAddress(NextAvailableAddress) &&
          "error resizing output file");
 
   // Overwrite functions with fixed output address. This is mostly used by
   // non-relocation mode, with one exception: injected functions are covered
   // here in both modes.
   uint64_t CountOverwrittenFunctions = 0;
   uint64_t OverwrittenScore = 0;
   for (BinaryFunction *Function : BC->getAllBinaryFunctions()) {
if (!BC->HasRelocations) {
     if (BC->TotalScore != 0) {
       double Coverage = OverwrittenScore / (double)BC->TotalScore * 100.0;
       outs() << format("BOLT-INFO: rewritten functions cover %.2lf", Coverage)
              << "% of the execution count of simple functions of "
                 "this binary\n";
     }
   }
 
-  if (BC->HasRelocations && opts::TrapOldCode) {
+  if (BC->HasRelocations && opts::TrapOldCode && !opts::Rewrite) {
     uint64_t SavedPos = OS.tell();
     // Overwrite function body to make sure we never execute these instructions.
     for (auto &BFI : BC->getBinaryFunctions()) {
       BinaryFunction &BF = BFI.second;
       if (!BF.getFileOffset() || !BF.isEmitted())
         continue;
       OS.seek(BF.getFileOffset());
       for (unsigned I = 0; I < BF.getMaxSize(); ++I)
         OS.write((unsigned char)BC->MIB->getTrapFillValue());
     }
     OS.seek(SavedPos);
   }
 
+  auto ShouldWrite = [](BinarySection &Section) {
+    return Section.isFinalized() && Section.getOutputData() &&
+           !Section.isVirtual() &&
+           (Section.getData() != Section.getOutputData() ||
+            Section.getAddress() != Section.getOutputAddress() ||
+            opts::Rewrite);
+  };
   // Write all allocatable sections - reloc-mode text is written here as well
   for (BinarySection &Section : BC->allocatableSections()) {
-    if (!Section.isFinalized() || !Section.getOutputData())
+    if (!ShouldWrite(Section))
       continue;
 
     if (opts::Verbosity >= 1)
       outs() << "BOLT: writing new section " << Section.getName()
              << "\n data at 0x" << Twine::utohexstr(Section.getAllocAddress())
-             << "\n of size " << Section.getOutputSize() << "\n at offset "
-             << Section.getOutputFileOffset() << '\n';
+             << "\n of size 0x" << Twine::utohexstr(Section.getOutputSize())
+             << "\n at offset 0x"
+             << Twine::utohexstr(Section.getOutputFileOffset()) << '\n';
     OS.pwrite(reinterpret_cast<const char *>(Section.getOutputData()),
               Section.getOutputSize(), Section.getOutputFileOffset());
   }
 
   for (BinarySection &Section : BC->allocatableSections())
     Section.flushPendingRelocations(OS, [this](const MCSymbol *S) {
       return getNewValueForSymbol(S->getName());
     });
 
   // If .eh_frame is present create .eh_frame_hdr.
   if (EHFrameSection)
     writeEHFrameHeader();
 
   // Add BOLT Addresses Translation maps to allow profile collection to
   // happen in the output binary
   if (opts::EnableBAT)
     addBATSection();
 
-  // Patch program header table.
-  patchELFPHDRTable();
+  // Write program header table.
+  writeELFPHDRTable();
 
   // Finalize memory image of section string table.
   finalizeSectionStringTable();
 
   // Update symbol tables.
   patchELFSymTabs();
 
   patchBuildID();
 
   if (opts::EnableBAT)
     encodeBATSection();
 
   // Copy non-allocatable sections once allocatable part is finished.
   rewriteNoteSections();
 
   if (BC->HasRelocations) {
     patchELFAllocatableRelaSections();
     patchELFAllocatableRelrSection();
-    patchELFGOT();
   }
 
   // Patch dynamic section/segment.
   patchELFDynamic();
 
   // Update ELF book-keeping info.
   patchELFSectionHeaderTable();
 
   if (opts::PrintSections) {
     outs() << "BOLT-INFO: Sections after processing:\n";
     BC->printSections(outs());
   }
 
   Out->keep();
   EC = sys::fs::setPermissions(opts::OutputFilename, sys::fs::perms::all_all);
   check_error(EC, "cannot set permissions of output file");
 }
 
+// this function is needed to estimate .eh_frame_hdr size when assigning
+// addresses to leave enough space for entries, but the actual content of
+// .eh_frame_hdr can only we written later after linking
+void RewriteInstance::mapEhFrameAndHeader(
+    BOLTLinker::SectionMapper AssignAddress) {
+
+  auto getEHFrameHeaderEntriesCount = [this](BinarySection *EHFrameSection) {
+    DWARFDebugFrame NewEHFrame(BC->TheTriple->getArch(), true,
+                               EHFrameSection->getOutputAddress());
+    Error E = NewEHFrame.parse(DWARFDataExtractor(
+        EHFrameSection->getOutputContents(), BC->AsmInfo->isLittleEndian(),
+        BC->AsmInfo->getCodePointerSize()));
+    check_error(std::move(E), "failed to parse EH frame");
+    const uint64_t NumEntries =
+        NewEHFrame.entries().end() - NewEHFrame.entries().begin();
+    return NumEntries;
+  };
+
+  BinarySection *NewEHFrameSection = getSection(getEHFrameSectionName());
+  assert(NewEHFrameSection && NewEHFrameSection->hasValidSectionID());
+
+  mapSection(*NewEHFrameSection);
+  AssignAddress(*NewEHFrameSection, NewEHFrameSection->getOutputAddress());
+  uint64_t NumEntries = getEHFrameHeaderEntriesCount(NewEHFrameSection);
+
+  if (BinarySection *RelocatedEHFrameSection =
+          getSection(".relocated" + getEHFrameSectionName())) {
+    NumEntries += getEHFrameHeaderEntriesCount(RelocatedEHFrameSection);
+    mapSection(*RelocatedEHFrameSection);
+    AssignAddress(*RelocatedEHFrameSection,
+                  RelocatedEHFrameSection->getOutputAddress());
+  }
+
+  const uint64_t Size = NumEntries * 8 + 12;
+
+  const unsigned Flags = BinarySection::getFlags(/*IsReadOnly=*/true,
+                                                 /*IsText=*/false,
+                                                 /*IsAllocatable=*/true);
+  BinarySection &EHFrameHdr = BC->registerOrUpdateSection(
+      getEHFrameHeaderSectionName(), ELF::SHT_PROGBITS, Flags, nullptr, Size,
+      /*Alignment=*/1);
+
+  mapSection(EHFrameHdr);
+}
+
 void RewriteInstance::writeEHFrameHeader() {
-  BinarySection *NewEHFrameSection =
-      getSection(getNewSecPrefix() + getEHFrameSectionName());
+  BinarySection *NewEHFrameSection = getSection(getEHFrameSectionName());
 
   // No need to update the header if no new .eh_frame was created.
-  if (!NewEHFrameSection)
+  if (!NewEHFrameSection || !NewEHFrameSection->hasValidSectionID()) {
     return;
+  }
 
   DWARFDebugFrame NewEHFrame(BC->TheTriple->getArch(), true,
                              NewEHFrameSection->getOutputAddress());
+
   Error E = NewEHFrame.parse(DWARFDataExtractor(
       NewEHFrameSection->getOutputContents(), BC->AsmInfo->isLittleEndian(),
       BC->AsmInfo->getCodePointerSize()));
   check_error(std::move(E), "failed to parse EH frame");
+  LLVM_DEBUG(dbgs() << "BOLT: writing a new .eh_frame_hdr\n");
 
   uint64_t RelocatedEHFrameAddress = 0;
   StringRef RelocatedEHFrameContents;
   BinarySection *RelocatedEHFrameSection =
       getSection(".relocated" + getEHFrameSectionName());
   if (RelocatedEHFrameSection) {
     RelocatedEHFrameAddress = RelocatedEHFrameSection->getOutputAddress();
     RelocatedEHFrameContents = RelocatedEHFrameSection->getOutputContents();
   }
   DWARFDebugFrame RelocatedEHFrame(BC->TheTriple->getArch(), true,
                                    RelocatedEHFrameAddress);
   Error Er = RelocatedEHFrame.parse(DWARFDataExtractor(
       RelocatedEHFrameContents, BC->AsmInfo->isLittleEndian(),
       BC->AsmInfo->getCodePointerSize()));
   check_error(std::move(Er), "failed to parse EH frame");
 
-  LLVM_DEBUG(dbgs() << "BOLT: writing a new .eh_frame_hdr\n");
-
-  NextAvailableAddress =
-      appendPadding(Out->os(), NextAvailableAddress, EHFrameHdrAlign);
-
-  const uint64_t EHFrameHdrOutputAddress = NextAvailableAddress;
-  const uint64_t EHFrameHdrFileOffset =
-      getFileOffsetForAddress(NextAvailableAddress);
-
+  auto EHFrameHdr = BC->getUniqueSectionByName(getEHFrameHeaderSectionName());
+  assert(EHFrameHdr);
   std::vector<char> NewEHFrameHdr = CFIRdWrt->generateEHFrameHeader(
-      RelocatedEHFrame, NewEHFrame, EHFrameHdrOutputAddress, FailedAddresses);
+      RelocatedEHFrame, NewEHFrame, EHFrameHdr->getOutputAddress(),
+      FailedAddresses);
 
-  assert(Out->os().tell() == EHFrameHdrFileOffset && "offset mismatch");
-  Out->os().write(NewEHFrameHdr.data(), NewEHFrameHdr.size());
-
-  const unsigned Flags = BinarySection::getFlags(/*IsReadOnly=*/true,
-                                                 /*IsText=*/false,
-                                                 /*IsAllocatable=*/true);
-  BinarySection *OldEHFrameHdrSection = getSection(".eh_frame_hdr");
-  if (OldEHFrameHdrSection)
-    OldEHFrameHdrSection->setOutputName(getOrgSecPrefix() + ".eh_frame_hdr");
-
-  BinarySection &EHFrameHdrSec = BC->registerOrUpdateSection(
-      getNewSecPrefix() + ".eh_frame_hdr", ELF::SHT_PROGBITS, Flags, nullptr,
-      NewEHFrameHdr.size(), /*Alignment=*/1);
-  EHFrameHdrSec.setOutputFileOffset(EHFrameHdrFileOffset);
-  EHFrameHdrSec.setOutputAddress(EHFrameHdrOutputAddress);
-  EHFrameHdrSec.setOutputName(".eh_frame_hdr");
-
-  NextAvailableAddress += EHFrameHdrSec.getOutputSize();
+  assert(NewEHFrameHdr.size() <= EHFrameHdr->getOutputSize());
+  Out->os().pwrite(NewEHFrameHdr.data(), NewEHFrameHdr.size(),
+                   EHFrameHdr->getOutputFileOffset());
 
   // Merge new .eh_frame with the relocated original so that gdb can locate all
   // FDEs.
   if (RelocatedEHFrameSection) {
     const uint64_t NewEHFrameSectionSize =
         RelocatedEHFrameSection->getOutputAddress() +
         RelocatedEHFrameSection->getOutputSize() -
         NewEHFrameSection->getOutputAddress();
-    NewEHFrameSection->updateContents(NewEHFrameSection->getOutputData(),
-                                      NewEHFrameSectionSize);
+    NewEHFrameSection->updateContents(nullptr, NewEHFrameSectionSize);
     BC->deregisterSection(*RelocatedEHFrameSection);
   }
 
-  LLVM_DEBUG(dbgs() << "BOLT-DEBUG: size of .eh_frame after merge is "
-                    << NewEHFrameSection->getOutputSize() << '\n');
+  LLVM_DEBUG(dbgs() << "BOLT-DEBUG: size of new .eh_frame is "
+                    << EHFrameSection->getOutputSize() << '\n');
 }
 
 uint64_t RewriteInstance::getNewValueForSymbol(const StringRef Name) {
   auto Value = Linker->lookupSymbol(Name);
   if (Value)
     return *Value;
 
   // Return the original value if we haven't emitted the symbol.
   BinaryData *BD = BC->getBinaryDataByName(Name);
   if (!BD)
     return 0;
 
   return BD->getAddress();
 }
 
-uint64_t RewriteInstance::getFileOffsetForAddress(uint64_t Address) const {
-  // Check if it's possibly part of the new segment.
-  if (Address >= NewTextSegmentAddress)
-    return Address - NewTextSegmentAddress + NewTextSegmentOffset;
-
+uint64_t
+RewriteInstance::getFileOffsetForAddress(const uint64_t Address) const {
   // Find an existing segment that matches the address.
   const auto SegmentInfoI = BC->SegmentMapInfo.upper_bound(Address);
   if (SegmentInfoI == BC->SegmentMapInfo.begin())
     return 0;
 
-  const SegmentInfo &SegmentInfo = std::prev(SegmentInfoI)->second;
-  if (Address < SegmentInfo.Address ||
-      Address >= SegmentInfo.Address + SegmentInfo.FileSize)
+  const ProgramHeader &SegmentInfo = std::prev(SegmentInfoI)->second;
+  if (Address < SegmentInfo.p_vaddr ||
+      Address >= SegmentInfo.p_vaddr + SegmentInfo.p_filesz)
     return 0;
 
-  return SegmentInfo.FileOffset + Address - SegmentInfo.Address;
+  return SegmentInfo.p_offset + Address - SegmentInfo.p_vaddr;
+}
+
+uint64_t
+RewriteInstance::getOutputFileOffsetForAddress(const uint64_t Address) const {
+  auto LB = BC->OutputAddressToOffsetMap.lower_bound(Address);
+  if (LB == BC->OutputAddressToOffsetMap.end() || LB->first > Address) {
+    assert(LB != BC->OutputAddressToOffsetMap.begin());
+    --LB;
+  }
+  const uint64_t SegmentStartAddress = LB->first;
+  const uint64_t SegmentStartOffset = LB->second;
+  const uint64_t OffsetInSegment = Address - SegmentStartAddress;
+  return SegmentStartOffset + OffsetInSegment;
 }
 
 bool RewriteInstance::willOverwriteSection(StringRef SectionName) {
   if (llvm::is_contained(SectionsToOverwrite, SectionName))
     return true;
   if (llvm::is_contained(DebugSectionsToOverwrite, SectionName))
     return true;
 
bool RewriteInstance::isDebugSection(StringRef SectionName) {
   return false;
 }
 
 bool RewriteInstance::isKSymtabSection(StringRef SectionName) {
   if (SectionName.startswith("__ksymtab"))
     return true;
 
   return false;
 }

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

 #include "MCTargetDesc/AArch64MCTargetDesc.h"
 #include "Utils/AArch64BaseInfo.h"
 #include "bolt/Core/MCPlusBuilder.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
+#include <cstdint>
 
 #define DEBUG_TYPE "mcplus"
 
 using namespace llvm;
 using namespace bolt;
 
 namespace {
 
bool isMOVW(const MCInst &Inst) const {
     return (Inst.getOpcode() == AArch64::MOVKWi ||
             Inst.getOpcode() == AArch64::MOVKXi ||
             Inst.getOpcode() == AArch64::MOVNWi ||
             Inst.getOpcode() == AArch64::MOVNXi ||
             Inst.getOpcode() == AArch64::MOVZXi ||
             Inst.getOpcode() == AArch64::MOVZWi);
   }
 
-  bool isADD(const MCInst &Inst) const {
+  bool isADD(const MCInst &Inst) const override {
     return (Inst.getOpcode() == AArch64::ADDSWri ||
             Inst.getOpcode() == AArch64::ADDSWrr ||
             Inst.getOpcode() == AArch64::ADDSWrs ||
             Inst.getOpcode() == AArch64::ADDSWrx ||
             Inst.getOpcode() == AArch64::ADDSXri ||
             Inst.getOpcode() == AArch64::ADDSXrr ||
             Inst.getOpcode() == AArch64::ADDSXrs ||
             Inst.getOpcode() == AArch64::ADDSXrx ||
public:
   ///  Matches PLT entry pattern and returns the associated GOT entry address.
   ///  Typical PLT entry looks like the following:
   ///
   ///    adrp    x16, 230000
   ///    ldr     x17, [x16, #3040]
   ///    add     x16, x16, #0xbe0
   ///    br      x17
   ///
-  uint64_t analyzePLTEntry(MCInst &Instruction, InstructionIterator Begin,
-                           InstructionIterator End,
+  uint64_t analyzePLTEntry(InstructionIterator Begin, InstructionIterator End,
                            uint64_t BeginPC) const override {
     // Check branch instruction
-    MCInst *Branch = &Instruction;
+    MCInst *Branch = &*(std::prev(End));
     assert(Branch->getOpcode() == AArch64::BR && "Unexpected opcode");
 
     DenseMap<const MCInst *, SmallVector<llvm::MCInst *, 4>> UDChain =
         computeLocalUDChain(Branch, Begin, End);
 
     // Match ldr instruction
     SmallVector<MCInst *, 4> &BranchUses = UDChain[Branch];
     if (BranchUses.size() < 1 || BranchUses[0] == nullptr)
if (I->getOpcode() != AArch64::ADRP ||
       return 0;
     TargetHiBits = &*I;
     Addr |= (Address + ((int64_t)I->getOperand(1).getImm() << 12)) &
             0xFFFFFFFFFFFFF000ULL;
     Target = Addr;
     return 3;
   }
 
-  bool matchAdrpAddPair(const MCInst &Adrp, const MCInst &Add) const override {
-    if (!isADRP(Adrp) || !isAddXri(Add))
+  bool matchAdrpPair(const MCInst &Adrp,
+                     const MCInst &AddOrLdr) const override {
+    if (!isADRP(Adrp))
+      return false;
+    if (!isAddXri(AddOrLdr) && !isLDRX(AddOrLdr))
       return false;
-
     assert(Adrp.getOperand(0).isReg() &&
            "Unexpected operand in ADRP instruction");
     MCPhysReg AdrpReg = Adrp.getOperand(0).getReg();
-    assert(Add.getOperand(1).isReg() &&
-           "Unexpected operand in ADDXri instruction");
-    MCPhysReg AddReg = Add.getOperand(1).getReg();
-    return AdrpReg == AddReg;
+    assert(AddOrLdr.getOperand(1).isReg() &&
+           "Unexpected operand in ADDXri/LDRX instruction");
+    MCPhysReg AddReg = AddOrLdr.getOperand(1).getReg();
+    if (AdrpReg != AddReg)
+      return false;
+    return true;
   }
 
   bool replaceImmWithSymbolRef(MCInst &Inst, const MCSymbol *Symbol,
                                int64_t Addend, MCContext *Ctx, int64_t &Value,
                                uint64_t RelType) const override {
     unsigned ImmOpNo = -1U;
     for (unsigned Index = 0; Index < MCPlus::getNumPrimeOperands(Inst);
          ++Index) {
       if (Inst.getOperand(Index).isImm()) {
         ImmOpNo = Index;
         break;
       }
     }
     if (ImmOpNo == -1U)
       return false;
 
     Value = Inst.getOperand(ImmOpNo).getImm();
 
     setOperandToSymbolRef(Inst, ImmOpNo, Symbol, Addend, Ctx, RelType);
 
     return true;
   }
+  bool patchPLTInstructions(InstructionIterator Begin, InstructionIterator End,
+                            const MCSymbol *Target, MCContext *Ctx,
+                            const MCSymbol *BFSymbol) const override {
+    int64_t Val;
+    int Count = 0;
+    for (auto I = Begin; I != End; ++I) {
+      if (isADRP(*I))
+        Count += replaceImmWithSymbolRef(*I, Target, 0, Ctx, Val,
+                                         ELF::R_AARCH64_ADR_PREL_PG_HI21);
+      else if (isADD(*I) || isLoad(*I))
+        Count += replaceImmWithSymbolRef(*I, Target, 0, Ctx, Val,
+                                         ELF::R_AARCH64_LDST64_ABS_LO12_NC);
+    }
+    return Count == 3;
+  }
+
+  bool relaxLdrToAdd(MCInst &Inst) const override {
+    assert(Inst.getNumOperands() == 3);
+    assert(Inst.getOpcode() == AArch64::LDRXui);
+    Inst.setOpcode(AArch64::ADDXri);
+    Inst.addOperand(MCOperand::createImm(0)); // zero shift
+    return true;
+  }
 
   bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
                           MCContext *Ctx) const override {
     Inst.setOpcode(AArch64::B);
     Inst.clear();
     Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
         Inst, MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx),
         *Ctx, 0)));

bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp

public:
   bool isCNop(const MCInst &Inst) const {
     return Inst.getOpcode() == RISCV::C_NOP;
   }
 
   bool isNoop(const MCInst &Inst) const override {
     return isNop(Inst) || isCNop(Inst);
   }
 
+  bool isAuipc(const MCInst &Inst) const {
+    return Inst.getOpcode() == RISCV::AUIPC;
+  }
+
+  bool isLD(const MCInst &Inst) const { return Inst.getOpcode() == RISCV::LD; }
+
   bool hasPCRelOperand(const MCInst &Inst) const override {
     switch (Inst.getOpcode()) {
     default:
       return false;
     case RISCV::JAL:
     case RISCV::AUIPC:
       return true;
     }
public:
 
   bool lowerTailCall(MCInst &Inst) override {
     removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall);
     if (getConditionalTailCall(Inst))
       unsetConditionalTailCall(Inst);
     return true;
   }
 
-  uint64_t analyzePLTEntry(MCInst &Instruction, InstructionIterator Begin,
-                           InstructionIterator End,
+  uint64_t analyzePLTEntry(InstructionIterator Begin, InstructionIterator End,
                            uint64_t BeginPC) const override {
-    auto I = Begin;
 
-    assert(I != End);
+    assert(Begin != End && std::next(Begin) != End);
+
+    if (std::next(Begin)->getOpcode() == RISCV::SUB)
+      return analyzePLTHeader(Begin, End, BeginPC);
+
+    auto I = Begin;
     auto &AUIPC = *I++;
     assert(AUIPC.getOpcode() == RISCV::AUIPC);
     assert(AUIPC.getOperand(0).getReg() == RISCV::X28);
 
     assert(I != End);
     auto &LD = *I++;
     assert(LD.getOpcode() == RISCV::LD);
     assert(LD.getOperand(0).getReg() == RISCV::X28);
uint64_t analyzePLTEntry(InstructionIterator Begin, InstructionIterator End,
 
     assert(I == End);
 
     auto AUIPCOffset = AUIPC.getOperand(1).getImm() << 12;
     auto LDOffset = LD.getOperand(2).getImm();
     return BeginPC + AUIPCOffset + LDOffset;
   }
 
+  uint64_t analyzePLTHeader(InstructionIterator Begin, InstructionIterator End,
+                            uint64_t BeginPC) const {
+    auto I = Begin;
+
+    assert(I != End);
+    auto &AUIPC = *I++;
+    assert(AUIPC.getOpcode() == RISCV::AUIPC);
+    assert(AUIPC.getOperand(0).getReg() == RISCV::X7);
+
+    assert(I != End);
+    auto &SUB = *I++;
+    assert(SUB.getOpcode() == RISCV::SUB);
+    assert(SUB.getOperand(0).getReg() == RISCV::X6);
+    assert(SUB.getOperand(1).getReg() == RISCV::X6);
+    assert(SUB.getOperand(2).getReg() == RISCV::X28);
+
+    assert(I != End);
+    auto &LD = *I++;
+    assert(LD.getOpcode() == RISCV::LD);
+    assert(LD.getOperand(0).getReg() == RISCV::X28);
+    assert(LD.getOperand(1).getReg() == RISCV::X7);
+
+    assert(I != End);
+    auto &ADDI1 = *I++;
+    assert(ADDI1.getOpcode() == RISCV::ADDI);
+    assert(ADDI1.getOperand(0).getReg() == RISCV::X6);
+    assert(ADDI1.getOperand(1).getReg() == RISCV::X6);
+
+    assert(I != End);
+    auto &ADDI2 = *I++;
+    assert(ADDI2.getOpcode() == RISCV::ADDI);
+    assert(ADDI2.getOperand(0).getReg() == RISCV::X5);
+    assert(ADDI2.getOperand(1).getReg() == RISCV::X7);
+
+    assert(I != End);
+    auto &SRLI = *I++;
+    assert(SRLI.getOpcode() == RISCV::SRLI);
+    assert(SRLI.getOperand(0).getReg() == RISCV::X6);
+    assert(SRLI.getOperand(1).getReg() == RISCV::X6);
+
+    assert(I != End);
+    auto &LD2 = *I++;
+    assert(LD2.getOpcode() == RISCV::LD);
+    assert(LD2.getOperand(0).getReg() == RISCV::X5);
+    assert(LD2.getOperand(1).getReg() == RISCV::X5);
+    assert(LD2.getOperand(2).getImm() == 8);
+
+    assert(I != End);
+    auto &JR = *I++;
+    (void)JR;
+    assert(JR.getOpcode() == RISCV::JALR);
+    assert(JR.getOperand(0).getReg() == RISCV::X0);
+    assert(JR.getOperand(1).getReg() == RISCV::X28);
+    assert(I == End);
+
+    auto AUIPCOffset = AUIPC.getOperand(1).getImm() << 12;
+    auto LDOffset = LD.getOperand(2).getImm();
+    return BeginPC + AUIPCOffset + LDOffset;
+  }
+
   bool replaceImmWithSymbolRef(MCInst &Inst, const MCSymbol *Symbol,
                                int64_t Addend, MCContext *Ctx, int64_t &Value,
                                uint64_t RelType) const override {
     unsigned ImmOpNo = -1U;
 
     for (unsigned Index = 0; Index < MCPlus::getNumPrimeOperands(Inst);
          ++Index) {
       if (Inst.getOperand(Index).isImm()) {
bool isCallAuipc(const MCInst &Inst) const {
     default:
       return false;
     case RISCVMCExpr::VK_RISCV_CALL:
     case RISCVMCExpr::VK_RISCV_CALL_PLT:
       return true;
     }
   }
 
+  bool patchPLTInstructions(InstructionIterator Begin, InstructionIterator End,
+                            const MCSymbol *Target, MCContext *Ctx,
+                            const MCSymbol *BFSymbol) const override {
+    int64_t Val;
+    int Count = 0;
+
+    for (auto I = Begin; I != End; ++I) {
+      if (isAuipc(*I))
+        Count += replaceImmWithSymbolRef(*I, Target, 0, Ctx, Val,
+                                         ELF::R_RISCV_PCREL_HI20);
+      else if (isLD(*I) && (I->getOperand(1).getReg() == RISCV::X7 ||
+                            I->getOperand(1).getReg() == RISCV::X28))
+        Count += replaceImmWithSymbolRef(*I, BFSymbol, 0, Ctx, Val,
+                                         ELF::R_RISCV_PCREL_LO12_I);
+    }
+    return Count == 2;
+  }
+
   bool isRISCVCall(const MCInst &First, const MCInst &Second) const override {
     if (!isCallAuipc(First))
       return false;
 
     assert(Second.getOpcode() == RISCV::JALR);
     return true;
   }
 };

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

public:
   bool isLEA64r(const MCInst &Inst) const override {
     return Inst.getOpcode() == X86::LEA64r;
   }
 
   bool isLeave(const MCInst &Inst) const override {
     return Inst.getOpcode() == X86::LEAVE || Inst.getOpcode() == X86::LEAVE64;
   }
 
+  virtual bool isCall64m(const MCInst &Inst) const override {
+    return Inst.getOpcode() == X86::CALL64m;
+  }
+
   bool isMoveMem2Reg(const MCInst &Inst) const override {
     switch (Inst.getOpcode()) {
     case X86::MOV16rm:
     case X86::MOV32rm:
     case X86::MOV64rm:
       return true;
     }
     return false;

bolt/lib/Utils/CommandLineOpts.cpp

 cl::OptionCategory BoltRelocCategory("BOLT options in relocation mode");
 cl::OptionCategory BoltOutputCategory("Output options");
 cl::OptionCategory AggregatorCategory("Data aggregation options");
 cl::OptionCategory BoltInstrCategory("BOLT instrumentation options");
 cl::OptionCategory HeatmapCategory("Heatmap options");
 
 cl::opt<unsigned> AlignText("align-text",
                             cl::desc("alignment of .text section"), cl::Hidden,
-                            cl::cat(BoltCategory));
+                            cl::init(64), cl::cat(BoltCategory));
 
 cl::opt<unsigned> AlignFunctions(
     "align-functions",
     cl::desc("align functions at a given value (relocation mode)"),
     cl::init(64), cl::cat(BoltOptCategory));
 
 cl::opt<bool>
 AggregateOnly("aggregate-only",
StrictMode("strict",
                cl::desc("trust the input to be from a well-formed source"),
 
                cl::cat(BoltCategory));
 
 cl::opt<bool> TimeOpts("time-opts",
                        cl::desc("print time spent in each optimization"),
                        cl::cat(BoltOptCategory));
 
-cl::opt<bool> UseOldText(
-    "use-old-text",
-    cl::desc("re-use space in old .text if possible (relocation mode)"),
+cl::opt<bool> UseOldText("use-old-text",
+                         cl::desc("re-use space in old .text. Deprecated - use "
+                                  "-rewrite instead"),
+                         cl::cat(BoltCategory));
+
+cl::opt<bool>
+    Rewrite("rewrite",
+            cl::desc("Rewrite entire binary - relocate all sections and "
+                     "create new program header table. Requires relocations"),
             cl::cat(BoltCategory));
 
 cl::opt<bool> UpdateDebugSections(
     "update-debug-sections",
     cl::desc("update DWARF debug sections of the executable"),
     cl::cat(BoltCategory));
 
 cl::opt<unsigned>
     Verbosity("v", cl::desc("set verbosity level for diagnostic output"),
               cl::init(0), cl::ZeroOrMore, cl::cat(BoltCategory),
               cl::sub(cl::SubCommand::getAll()));
 
 bool processAllFunctions() {
   if (opts::AggregateOnly)
     return false;
 
-  if (UseOldText || StrictMode)
+  if (Rewrite || StrictMode)
     return true;
 
   return false;
 }
 
 } // namespace opts

bolt/test/AArch64/Inputs/array_end.c

+
+__attribute__((destructor)) void destr() {}
+
+__attribute__((noinline)) void callFini() {
+  extern void (*__fini_array_start[])();
+  extern void (*__fini_array_end[])();
+  unsigned long Count = __fini_array_end - __fini_array_start;
+  for (unsigned long I = 0; I < Count; ++I)
+    (*__fini_array_start[I])();
+}
+
+void _start() {
+  callFini();
+  __asm__("mov     x0, #0\n"
+          "mov     w8, #93\n"
+          "svc     #0\n");
+}

bolt/test/AArch64/Inputs/array_end.lld_script

+
+PHDRS
+{
+  text PT_LOAD FILEHDR PHDRS;
+}
+
 SECTIONS {
+  . = SIZEOF_HEADERS;
   .fini_array    :
   {
     PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array) SORT_BY_INIT_PRIORITY(.dtors.*)))
     PROVIDE_HIDDEN (__fini_array_end = .);
   }
 
   . = . + 128;
 
   .text : { *(.text) }
+  .text : { *(.text) } :text
+  /DISCARD/ : {
+    *(.eh_frame);
+    *(.comment);
+    *(.got);
+    *(.got.plt);
+    *(.data);
+    *(.bss)
+  }
 }

bolt/test/AArch64/Inputs/dw_cfa_gnu_window_save.yaml

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+    AddressAlign:    0x8
+    Info:            .got.plt
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+        Type:            R_AARCH64_JUMP_SLOT
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+        Symbol:          pltSym2
+        Type:            R_AARCH64_JUMP_SLOT
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+        Symbol:          pltSym3
+        Type:            R_AARCH64_JUMP_SLOT
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+        Symbol:          pltSym4
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     Type:            SHT_NOBITS
     Flags:           [ SHF_WRITE, SHF_ALLOC, SHF_TLS ]
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     Type:            SHT_DYNAMIC
     Flags:           [ SHF_WRITE, SHF_ALLOC ]
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         Value:           0x0
   - Name:            .got
     Type:            SHT_PROGBITS
     Flags:           [ SHF_WRITE, SHF_ALLOC ]
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-    Type:            SHT_RELA
-    Flags:           [ SHF_ALLOC, SHF_INFO_LINK ]
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       - Name:            .plt
       - Name:            .text
       - Name:            .rela.text
       - Name:            .eh_frame_hdr
       - Name:            .eh_frame
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       - Name:            .dynamic
       - Name:            .got
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       - Name:            .symtab
       - Name:            .strtab
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     Type:            STT_SECTION
     Section:         .text
     Value:           0x590
   - Name:            t1
     Type:            STT_TLS
     Section:         .tbss
     Binding:         STB_GLOBAL
     Size:            0x4
 DynamicSymbols:
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+    Type:            STT_FUNC
+    Binding:         STB_GLOBAL
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+    Type:            STT_FUNC
+    Binding:         STB_GLOBAL
+  - Name:            pltSym3
+    Type:            STT_FUNC
+    Binding:         STB_GLOBAL
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+    Type:            STT_FUNC
+    Binding:         STB_GLOBAL
   - Name:            t1
     Type:            STT_TLS
     Section:         .tbss
     Binding:         STB_GLOBAL
     Size:            0x4
 ...

bolt/test/AArch64/Inputs/tls-trad.yaml

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   - Name:            .eh_frame
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+  - Name:            .rela.plt
+    Type:            SHT_RELA
+    Flags:           [ SHF_ALLOC, SHF_INFO_LINK ]
+    Link:            .dynsym
+    AddressAlign:    0x8
+    Info:            .got.plt
+    Relocations:
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+        Symbol:          pltSym1
+        Type:            R_AARCH64_JUMP_SLOT
+      - Offset:          0x11000
+        Symbol:          pltSym2
+        Type:            R_AARCH64_JUMP_SLOT
+      - Offset:          0x11008
+        Symbol:          pltSym3
+        Type:            R_AARCH64_JUMP_SLOT
+      - Offset:          0x11010
+        Symbol:          pltSym4
+        Type:            R_AARCH64_JUMP_SLOT
+      - Offset:          0x10fb0
+        Symbol:          t1
+        Type:            R_AARCH64_TLSDESC
   - Name:            .tbss
     Type:            SHT_NOBITS
     Flags:           [ SHF_WRITE, SHF_ALLOC, SHF_TLS ]
     Address:         0x10DE0
     AddressAlign:    0x4
     Offset:          0xDE0
     Size:            0x4
   - Name:            .dynamic
     Type:            SHT_DYNAMIC
     Flags:           [ SHF_WRITE, SHF_ALLOC ]
     Address:         0x10DF0
+    Offset:          0xDF0
     Link:            .dynstr
     AddressAlign:    0x8
     Entries:
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         Value:           0x0
   - Name:            .got
     Type:            SHT_PROGBITS
     Flags:           [ SHF_WRITE, SHF_ALLOC ]
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     AddressAlign:    0x8
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     Content:         F00D010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+  - Name:            .got.plt
+    Type:            SHT_PROGBITS
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+    Offset:          0xFE8
+    AddressAlign:    0x8
+    Size:            0x30
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     Type:            SHT_RELA
     Flags:           [ SHF_INFO_LINK ]
     Link:            .symtab
     AddressAlign:    0x8
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         Symbol:          t1
         Type:            R_AARCH64_TLSGD_ADD_LO12_NC
   - Type:            SectionHeaderTable
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       - Name:            .plt
       - Name:            .text
       - Name:            .rela.text
       - Name:            .eh_frame_hdr
       - Name:            .eh_frame
+      - Name:            .rela.plt
       - Name:            .tbss
       - Name:            .dynamic
       - Name:            .got
+      - Name:            .got.plt
       - Name:            .symtab
       - Name:            .strtab
       - Name:            .shstrtab
 Symbols:
   - Name:            .text
     Type:            STT_SECTION
     Section:         .text
     Value:           0x590
+#   Add functions because otherwise BOLT will complain
+  - Name:            one
+    Type:            STT_FUNC
+    Section:         .text
+    Value:           0x540
+  - Name:            two
+    Type:            STT_FUNC
+    Section:         .text
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   - Name:            t1
     Type:            STT_TLS
     Section:         .tbss
     Binding:         STB_GLOBAL
     Size:            0x4
+  - Name:            pltSym1
+    Type:            STT_FUNC
+    Binding:         STB_GLOBAL
+  - Name:            pltSym2
+    Type:            STT_FUNC
+    Binding:         STB_GLOBAL
+  - Name:            pltSym3
+    Type:            STT_FUNC
+    Binding:         STB_GLOBAL
+  - Name:            pltSym4
+    Type:            STT_FUNC
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 ...

bolt/test/AArch64/array_end.c

-// Test checks that bolt properly finds end section label.
-// Linker script contains gap after destructor array, so
-// __init_array_end address would not be owned by any section.
-
-// REQUIRES: system-linux
-// RUN: %clang %cflags -no-pie %s -o %t.exe -Wl,-q \
-// RUN:   -Wl,-T %S/Inputs/array_end.lld_script
-// RUN: llvm-bolt %t.exe -o %t.bolt --print-disasm \
-// RUN:  --print-only="callFini" | FileCheck %s
-
-// CHECK: adr [[REG:x[0-28]+]], "__fini_array_end/1"
-
-__attribute__((destructor)) void destr() {}
-
-__attribute__((noinline)) void callFini() {
-  extern void (*__fini_array_start[])();
-  extern void (*__fini_array_end[])();
-  unsigned long Count = __fini_array_end - __fini_array_start;
-  for (unsigned long I = 0; I < Count; ++I)
-    (*__fini_array_start[I])();
-}
-
-void _start() { callFini(); }

bolt/test/AArch64/array_end.test

+// Test checks that bolt properly finds end section label.
+// Linker script contains gap after destructor array, so
+// __init_array_end address would not be owned by any section.
+
+// REQUIRES: system-linux
+// RUN: %clang %cflags -no-pie %S/Inputs/array_end.c -o %t.exe -Wl,-q \
+// RUN:   -Wl,-T %S/Inputs/array_end.lld_script
+// RUN: llvm-bolt %t.exe -o %t.bolt --print-disasm \
+// RUN:  --print-only="callFini" --debug-only=bolt 2>&1 | FileCheck %s
+
+// CHECK: BOLT-INFO: __fini_array_end is in the end of .fini_array
+// CHECK: adr [[REG:x[0-28]+]], __fini_array_end
+
+// RUN: llvm-bolt %t.exe -o %t.bolt.rewritten --rewrite --print-disasm \
+// RUN:  --print-only="callFini" --debug-only=bolt 2>&1 | FileCheck %s
+
+// Check assembly and symtab
+// RUN: llvm-objdump --disassemble-symbols=callFini %t.bolt > %t.log
+// RUN: llvm-readelf -WS %t.bolt | grep .fini_array >> %t.log
+// RUN: llvm-readelf -Ws %t.bolt | grep __fini_array_end >> %t.log
+// RUN: llvm-readelf -Ws %t.bolt | grep __fini_array_end >> %t.log
+
+// RUN: cat %t.log | FileCheck %s --check-prefix=CHECK-FIRST
+
+// CHECK-FIRST: adrp    [[REG:x[0-28]+]], 0x[[#%x,PAGE:]]
+// CHECK-FIRST: add     [[REG]], [[REG]], #0x[[#%x,OFFSET:]]
+// CHECK-FIRST: .fini_array PROGBITS {{[0]+}}[[#%x,SECADDR:]] {{[0]+}}[[#%x,SECOFFSET:]] {{[0]+}}[[#%x,SECSIZE:]]
+// CHECK-FIRST: {{[0]+}}[[#%x,PAGE+OFFSET]]     0 NOTYPE  LOCAL  HIDDEN     {{[0-9]+}} __fini_array_end
+// CHECK-FIRST: {{[0]+}}[[#%x,SECADDR+SECSIZE]]     0 NOTYPE  LOCAL  HIDDEN     {{[0-9]+}} __fini_array_end
+
+// Check assembly and symtab after rewrite
+// RUN: llvm-objdump --disassemble-symbols=callFini %t.bolt.rewritten > %t.log
+// RUN: llvm-readelf -WS %t.bolt.rewritten | grep .fini_array >> %t.log
+// RUN: llvm-readelf -Ws %t.bolt.rewritten | grep __fini_array_end >> %t.log
+// RUN: llvm-readelf -Ws %t.bolt.rewritten | grep __fini_array_end >> %t.log
+
+// RUN: cat %t.log | FileCheck %s --check-prefix=CHECK-SECOND
+
+// CHECK-SECOND: adrp    [[REG:x[0-28]+]], 0x[[#%x,PAGE:]]
+// CHECK-SECOND: add     [[REG]], [[REG]], #0x[[#%x,OFFSET:]]
+// CHECK-SECOND: .fini_array PROGBITS {{[0]+}}[[#%x,SECADDR:]] {{[0]+}}[[#%x,SECOFFSET:]] {{[0]+}}[[#%x,SECSIZE:]]
+// CHECK-SECOND: {{[0]+}}[[#%x,PAGE+OFFSET]]     0 NOTYPE  LOCAL  HIDDEN     {{[0-9]+}} __fini_array_end
+// CHECK-SECOND: {{[0]+}}[[#%x,SECADDR+SECSIZE]]     0 NOTYPE  LOCAL  HIDDEN     {{[0-9]+}} __fini_array_end

bolt/test/AArch64/got-ld64-relaxation.test

 // This test checks that ADR+LDR instruction sequence relaxed by the linker
 // to the ADR+ADD sequence is properly reconized and handled by bolt
 
 // RUN: yaml2obj %p/Inputs/got-ld64-relaxation.yaml &> %t.exe
-// RUN: llvm-bolt %t.exe -o /dev/null --print-fix-relaxations \
-// RUN:   --print-only=main | FileCheck %s
+// RUN: llvm-bolt %t.exe -o %t.exe.bolt -print-only=_start -print-disasm | FileCheck %s
 
-// CHECK: adrp x0, foo
-// CHECK-NEXT: add x0, x0, :lo12:foo
+// CHECK: adrp x1, foo
+// CHECK-NEXT: add x1, x1, :lo12:foo

bolt/test/X86/Inputs/blarge.yaml

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   - Name:            .rodata
     Type:            SHT_PROGBITS
     Flags:           [ SHF_ALLOC ]
     Address:         0x0000000000401240
     AddressAlign:    0x0000000000000010
     Content:         01000200000000002A2A2A2A2A2A2A2A2A2043554249432046554E4354494F4E53202A2A2A2A2A2A2A2A2A2A2A0000002A2A2A2A2A2A2A2A2A20494E54454745522053515220524F4F5453202A2A2A2A2A2A2A2A2A2A2A002A2A2A2A2A2A2A2A2A20414E474C4520434F4E56455253494F4E202A2A2A2A2A2A2A2A2A2A2A000025332E30662064656772656573203D20252E3132662072616469616E730A0000252E3132662072616469616E73203D2025332E306620646567726565730A0000536F6C7574696F6E733A0020256600737172742825336429203D202532640A007371727428256C5829203D2025580A00000000000000F0BF00000000000014400000000000002440000000000000F03F0000000000003EC0000000000000404000000000000025C0000000000000314000000000000012C00000000000003FC000000000000036400000000000000CC000000000008041C06666666666662BC00000000000002840AE47E17A14AE284000000000000008409A999999999937C00000000000001840295C8FC2F5F850C000000000000020C000000000000041400000000000001E40D7A3703D0A572140000000000080464000000000000030403333333333331540333333333333FBBF00000000000028C077BE9F1A2FDDDC3F85EB51B81E85E33F000000000000D03F182D4454FB2109400000000000806640FCA9F1D24D62503F0000000000807640399D52A246DF413F9B0B6097FB21194000000000000000C0182D4454FB211940182D4454FB212940555555555555D53F00004040000010410000D84100005842FFFFFFFFFFFFFF7F0000000000000000
   - Name:            .dynamic
     Type:            SHT_DYNAMIC
     Flags:           [ SHF_WRITE, SHF_ALLOC ]
     Address:         0x00000000006016B0
+    Offset:          0x16B0
     Link:            .dynstr
     AddressAlign:    0x0000000000000008
     Content:         01000000000000000100000000000000010000000000000072000000000000000C00000000000000C0054000000000000D000000000000003412400000000000190000000000000098166000000000001B0000000000000008000000000000001A00000000000000A0166000000000001C000000000000000800000000000000040000000000000048024000000000000500000000000000C803400000000000060000000000000090024000000000000A00000000000000AE000000000000000B000000000000001800000000000000150000000000000000000000000000000300000000000000981860000000000002000000000000000000000000000000140000000000000007000000000000001700000000000000E8044000000000000700000000000000D0044000000000000800000000000000000000000000000009000000000000001800000000000000FEFFFF6F000000009004400000000000FFFFFF6F000000000200000000000000F0FFFF6F000000007604400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
   - Name:            .data
     Type:            SHT_PROGBITS
     Flags:           [ SHF_WRITE, SHF_ALLOC ]
     Address:         0x00000000006018F8
     AddressAlign:    0x0000000000000008
- Name:            main
       Binding:         STB_GLOBAL
 DynamicSymbols:
     - Name:            sqrt
       Type:            STT_FUNC
       Binding:         STB_GLOBAL
 ProgramHeaders:
   - Type: PT_PHDR
     Flags: [ PF_X, PF_R ]
-    VAddr: 0x00000000004005E0
-    PAddr: 0x00000000004005E0
-    FirstSec: .noplt
-    LastSec: .noplt
+    VAddr: 0x0000000000400040
+    PAddr: 0x0000000000400040
+    FileSize: 0xe0
+    MemSize: 0xe0
   - Type: PT_LOAD
     Flags: [ PF_X, PF_R ]
     VAddr: 0x00000000004005E0
     PAddr: 0x00000000004005E0
+    Offset: 0x5e0
     FirstSec: .noplt
     LastSec: .rodata
   - Type: PT_LOAD
     Flags: [ PF_R, PF_W ]
     VAddr: 0x00000000006018F8
     PAddr: 0x00000000006018F8
     FirstSec: .data
-    LastSec: .bss
-  - Type: PT_DYNAMIC
-    Flags: [ PF_R, PF_W ]
-    VAddr: 0x00000000006016B0
-    PAddr: 0x00000000006016B0
-    FirstSec: .dynamic
-    LastSec: .dynamic
+    LastSec: .dynstr
+#  - Type: PT_DYNAMIC
+#    Flags: [ PF_R, PF_W ]
+#    VAddr: 0x00000000006016B0
+#    PAddr: 0x00000000006016B0
+#    FirstSec: .dynamic
+#    LastSec: .dynstr
 ...

bolt/test/X86/Inputs/broken_dynsym.yaml

 !ELF
 FileHeader:
   Class: ELFCLASS64
   Data: ELFDATA2LSB
   Type: ET_EXEC
   Machine: EM_X86_64
 ProgramHeaders:
   - Type: PT_LOAD
     FirstSec: .a
-    LastSec: .a
+    LastSec: .dynstr
     Align:           0x1000
 Sections:
   - Name: .a
     Type: SHT_PROGBITS
     Content: 00
     AddressAlign:    0x1
   - Name: .b
     Type: 0

bolt/test/X86/Inputs/issue20.yaml

 --- !ELF
 FileHeader:
   Class:           ELFCLASS64
   Data:            ELFDATA2LSB
   Type:            ET_EXEC
   Machine:         EM_X86_64
   Entry:           0x00000000004004CD
 Sections:
   - Name:            .text
     Type:            SHT_PROGBITS
     Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
     Address:         0x00000000004003E0
+    Offset:          0x3E0
     AddressAlign:    0x0000000000000010
     Content:         31ED4989D15E4889E24883E4F0505449C7C07005400048C7C10005400048C7C7CD044000E8B7FFFFFFF4660F1F440000B82F10600055482D281060004883F80E4889E577025DC3B8000000004885C074F45DBF28106000FFE00F1F8000000000B82810600055482D2810600048C1F8034889E54889C248C1EA3F4801D048D1F875025DC3BA000000004885D274F45D4889C6BF28106000FFE20F1F8000000000803D9D0B2000007511554889E5E87EFFFFFF5DC6058A0B200001F3C30F1F400048833D7809200000741EB8000000004885C0741455BF200E60004889E5FFD05DE97BFFFFFF0F1F00E973FFFFFF4831C0C34883E703FF24FD90054000B801000000EB13B802000000EB0CB803000000EB05B804000000C3660F1F84000000000041574189FF41564989F641554989D541544C8D25F808200055488D2DF8082000534C29E531DB48C1FD034883EC08E85DFEFFFF4885ED741E0F1F8400000000004C89EA4C89F64489FF41FF14DC4883C3014839EB75EA4883C4085B5D415C415D415E415FC390662E0F1F840000000000F3C3
   - Name:            .rodata
     Type:            SHT_PROGBITS
     Flags:           [ SHF_ALLOC ]
     Address:         0x0000000000400580
     AddressAlign:    0x0000000000000008
+    Offset:          0x580
     Content:         01000200000000000000000000000000DC04400000000000E304400000000000EA04400000000000F104400000000000
   - Name:            .dynamic
     Type:            SHT_DYNAMIC
     Flags:           [ SHF_WRITE, SHF_ALLOC ]
     Address:         0x0000000000600E28
+    Offset:          0xE28
     Link:            .dynstr
     AddressAlign:    0x0000000000000008
     Content:         010000000000000001000000000000000C0000000000000090034000000000000D0000000000000074054000000000001900000000000000100E6000000000001B0000000000000008000000000000001A00000000000000180E6000000000001C000000000000000800000000000000F5FEFF6F000000009802400000000000050000000000000000034000000000000600000000000000B8024000000000000A0000000000000038000000000000000B0000000000000018000000000000001500000000000000000000000000000003000000000000000010600000000000020000000000000000000000000000001400000000000000070000000000000017000000000000007803400000000000070000000000000060034000000000000800000000000000000000000000000009000000000000001800000000000000FEFFFF6F000000004003400000000000FFFFFF6F000000000100000000000000F0FFFF6F000000003803400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 Symbols:
     - Name:            main
       Type:            STT_FUNC
       Section:         .text
       Value:           0x00000000004004CD
       Size:            0x000000000000002A
       Binding:         STB_GLOBAL
     - Name:            jumptbl
       Section:         .rodata
       Value:           0x0000000000400590
       Binding:         STB_GLOBAL
 DynamicSymbols:
     - Name:            mydata
       Section:         .rodata
       Value:           0x0000000000400100
       Binding:         STB_GLOBAL
 ProgramHeaders:
   - Type: PT_LOAD
     Flags: [ PF_X, PF_R ]
-    VAddr: 0x004003E0
-    PAddr: 0x004003E0
+    VAddr: 0x00400000
+    PAddr: 0x00400000
+    Offset: 0x0
     FirstSec: .text
-    LastSec: .text
-  - Type: PT_DYNAMIC
-    Flags: [ PF_X, PF_R ]
+    LastSec: .rodata
+  - Type: PT_LOAD
+    Flags: [ PF_W, PF_R ]
     VAddr: 0x00600E28
     PAddr: 0x00600E28
+    Offset: 0xE28
     FirstSec: .dynamic
-    LastSec: .dynamic
+    LastSec: .dynstr
+#   - Type: PT_DYNAMIC
+#    Flags: [ PF_X, PF_R ]
+#    VAddr: 0x00600E28
+#    PAddr: 0x00600E28
+#    FirstSec: .dynamic
+#    LastSec: .dynamic
 ...

bolt/test/X86/Inputs/issue26.yaml

 --- !ELF
 FileHeader:
   Class:           ELFCLASS64
   Data:            ELFDATA2LSB
   Type:            ET_EXEC
   Machine:         EM_X86_64
   Entry:           0x00000000004004FA
 Sections:
   - Name:            .text
     Type:            SHT_PROGBITS
     Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
     Address:         0x00000000004003E0
+    Offset:          0x3E0
     AddressAlign:    0x0000000000000010
     Content:         31ED4989D15E4889E24883E4F0505449C7C07005400048C7C10005400048C7C7FA044000E8B7FFFFFFF4660F1F440000B82F10600055482D281060004883F80E4889E577025DC3B8000000004885C074F45DBF28106000FFE00F1F8000000000B82810600055482D2810600048C1F8034889E54889C248C1EA3F4801D048D1F875025DC3BA000000004885D274F45D4889C6BF28106000FFE20F1F8000000000803D9D0B2000007511554889E5E87EFFFFFF5DC6058A0B200001F3C30F1F400048833D7809200000741EB8000000004885C0741455BF200E60004889E5FFD05DE97BFFFFFF0F1F00E973FFFFFF648B0425B0FCFFFF39C70F850C0000004839160F850400000048890EC3B8FFFFFFFFC34839FE0F84F0FFFFFFC34831C0C3669041574189FF41564989F641554989D541544C8D25F808200055488D2DF8082000534C29E531DB48C1FD034883EC08E85DFEFFFF4885ED741E0F1F8400000000004C89EA4C89F64489FF41FF14DC4883C3014839EB75EA4883C4085B5D415C415D415E415FC390662E0F1F840000000000F3C3
-  - Name:            .rela.text
-    Type:            SHT_RELA
-    Flags:           [ SHF_INFO_LINK ]
-    Link:            .symtab
-    AddressAlign:    0x0000000000000008
-    Info:            .text
-    Relocations:
   - Name:            .rodata
     Type:            SHT_PROGBITS
     Flags:           [ SHF_ALLOC ]
     Address:         0x0000000000400580
+    Offset:          0x580
     AddressAlign:    0x0000000000000008
     Content:         '01000200000000000000000000000000'
   - Name:            .dynamic
     Type:            SHT_DYNAMIC
     Flags:           [ SHF_WRITE, SHF_ALLOC ]
     Address:         0x0000000000600E28
+    Offset:          0xE28
     Link:            .dynstr
     AddressAlign:    0x0000000000000008
     Content:         010000000000000001000000000000000C0000000000000090034000000000000D0000000000000074054000000000001900000000000000100E6000000000001B0000000000000008000000000000001A00000000000000180E6000000000001C000000000000000800000000000000F5FEFF6F000000009802400000000000050000000000000000034000000000000600000000000000B8024000000000000A0000000000000038000000000000000B0000000000000018000000000000001500000000000000000000000000000003000000000000000010600000000000020000000000000000000000000000001400000000000000070000000000000017000000000000007803400000000000070000000000000060034000000000000800000000000000000000000000000009000000000000001800000000000000FEFFFF6F000000004003400000000000FFFFFF6F000000000100000000000000F0FFFF6F000000003803400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+  - Name:            .rela.text
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000008
+    Info:            .text
+    Relocations:
 Symbols:
     - Name:            FUNC
       Type:            STT_FUNC
       Section:         .text
       Value:           0x00000000004004F0
       Size:            0x000000000000000A
       Binding:         STB_GLOBAL
     - Name:            main
- Name:            XYZ
       Size:            0x0000000000000023
       Binding:         STB_GLOBAL
 DynamicSymbols:
     - Name:            mydata
       Section:         .rodata
       Value:           0x0000000000400100
       Binding:         STB_GLOBAL
 ProgramHeaders:
-  - Type: PT_PHDR
-    Flags: [ PF_X, PF_R ]
-    VAddr: 0x004003E0
-    PAddr: 0x004003E0
-    FirstSec: .text
-    LastSec: .text
   - Type: PT_LOAD
     Flags: [ PF_X, PF_R ]
-    VAddr: 0x004003E0
-    PAddr: 0x004003E0
+    VAddr: 0x00400000
+    PAddr: 0x00400000
+    Offset: 0x0
     FirstSec: .text
-    LastSec: .text
-  - Type: PT_DYNAMIC
-    Flags: [ PF_X, PF_R ]
-    VAddr: 0x00600E28
-    PAddr: 0x00600E28
+    LastSec: .rodata
+  - Type: PT_LOAD
+    Flags: [ PF_R, PF_W ]
+    VAddr: 0x600e28
     FirstSec: .dynamic
-    LastSec: .dynamic
+    LastSec: .dynstr
 ...

bolt/test/X86/Inputs/plt-got-sec.yaml

 --- !ELF
 FileHeader:
   Class:           ELFCLASS64
   Data:            ELFDATA2LSB
   Type:            ET_EXEC
   Machine:         EM_X86_64
   Entry:           0x401050
 ProgramHeaders:
   - Type:            PT_PHDR
     Flags:           [ PF_R ]
     VAddr:           0x400040
     Align:           0x8
+    FileSize:        0x2d8
+    MemSize:         0x2d8
   - Type:            PT_INTERP
     Flags:           [ PF_R ]
     FirstSec:        .interp
     LastSec:         .interp
     VAddr:           0x400318
   - Type:            PT_LOAD
     Flags:           [ PF_R ]
     FirstSec:        .interp
     LastSec:         .rela.plt
     VAddr:           0x400000
+    Offset:          0x0
     Align:           0x1000
   - Type:            PT_LOAD
     Flags:           [ PF_X, PF_R ]
     FirstSec:        .init
     LastSec:         .fini
     VAddr:           0x401000
     Align:           0x1000
   - Type:            PT_LOAD

bolt/test/X86/Inputs/plt-mold.yaml

 --- !ELF
 FileHeader:
   Class:           ELFCLASS64
   Data:            ELFDATA2LSB
   Type:            ET_DYN
   Machine:         EM_X86_64
   Entry:           0x13D0
 ProgramHeaders:
   - Type:            PT_PHDR
     Flags:           [ PF_R ]
     VAddr:           0x40
+    FileSize:        0x230
+    MemSize:         0x230
     Align:           0x8
   - Type:            PT_INTERP
     Flags:           [ PF_R ]
     FirstSec:        .interp
     LastSec:         .interp
     VAddr:           0x270
   - Type:            PT_LOAD
     Flags:           [ PF_R ]
     FirstSec:        .interp
     LastSec:         .rodata.str
+    VAddr:           0x0
+    Offset:          0x0
     Align:           0x1000
   - Type:            PT_LOAD
     Flags:           [ PF_X, PF_R ]
     FirstSec:        .plt
     LastSec:         .text
     VAddr:           0x13A0
     Align:           0x1000
   - Type:            PT_LOAD

bolt/test/X86/Inputs/plt-sec-8-byte.yaml

 --- !ELF
 FileHeader:
   Class:           ELFCLASS64
   Data:            ELFDATA2LSB
   Type:            ET_EXEC
   Machine:         EM_X86_64
   Entry:           0x400510
 ProgramHeaders:
   - Type:            PT_PHDR
     Flags:           [ PF_R ]
     VAddr:           0x400040
+    Offset:          0x40
     Align:           0x8
+    FileSize:        0x1F8
+    MemSize:         0x1F8
   - Type:            PT_INTERP
     Flags:           [ PF_R ]
     FirstSec:        .interp
     LastSec:         .interp
     VAddr:           0x400238
   - Type:            PT_LOAD
     Flags:           [ PF_X, PF_R ]
     FirstSec:        .interp
     LastSec:         .eh_frame
+    Offset:          0x0
     VAddr:           0x400000
     Align:           0x200000
   - Type:            PT_LOAD
     Flags:           [ PF_W, PF_R ]
     FirstSec:        .init_array
     LastSec:         .bss
     VAddr:           0x600DA8
     Align:           0x200000

bolt/test/X86/Inputs/plt-sec.yaml

 --- !ELF
 FileHeader:
   Class:           ELFCLASS64
   Data:            ELFDATA2LSB
   Type:            ET_EXEC
   Machine:         EM_X86_64
   Entry:           0x401050
 ProgramHeaders:
   - Type:            PT_PHDR
     Flags:           [ PF_R ]
     VAddr:           0x400040
+    Offset:          0x40
+    FileSize:        0x2d8
+    MemSize:         0x2d8
     Align:           0x8
   - Type:            PT_INTERP
     Flags:           [ PF_R ]
     FirstSec:        .interp
     LastSec:         .interp
     VAddr:           0x400318
   - Type:            PT_LOAD
     Flags:           [ PF_R ]
     FirstSec:        .interp
     LastSec:         .rela.plt
     VAddr:           0x400000
+    Offset:          0x0
     Align:           0x1000
   - Type:            PT_LOAD
     Flags:           [ PF_X, PF_R ]
     FirstSec:        .init
     LastSec:         .fini
     VAddr:           0x401000
+    Offset:          0x1000
     Align:           0x1000
   - Type:            PT_LOAD
     Flags:           [ PF_R ]
     FirstSec:        .rodata
     LastSec:         .eh_frame
     VAddr:           0x402000
+    Offset:          0x2000
     Align:           0x1000
   - Type:            PT_LOAD
     Flags:           [ PF_W, PF_R ]
     FirstSec:        .init_array
     LastSec:         .bss
     VAddr:           0x403E10
     Align:           0x1000
   - Type:            PT_DYNAMIC

bolt/test/X86/Inputs/srol-bug-input.yaml

 --- !ELF
 FileHeader:
   Class:           ELFCLASS64
   Data:            ELFDATA2LSB
   Type:            ET_EXEC
   Machine:         EM_X86_64
   Entry:           0x0000000000400000
 Sections:
   - Name:            .text
     Type:            SHT_PROGBITS
     Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
-    Address:         0x0000000000400000
+    Address:         0x0000000000400200
     AddressAlign:    0x0000000000000010
+    Offset:          0x200
     Content:         0315fa0000002B15f40000002315ee0000000B15e80000003315e2000000500fB715da0000008A15d4000000668B15cd0000008B15c7000000488B15c00000003A15ba000000663B15b30000003B15ad000000483B15a60000008415a0000000668515990000008515930000004885158c000000C3
   - Name:            .rodata
     Type:            SHT_PROGBITS
     Flags:           [ SHF_ALLOC ]
-    Address:         0x0000000000400100
+    Address:         0x0000000000400300
     AddressAlign:    0x0000000000000100
+    Offset:          0x300
     Content:         010002000000000000000000
   - Name:            .dynamic
     Type:            SHT_DYNAMIC
     Flags:           [ SHF_WRITE, SHF_ALLOC ]
     Address:         0x000000000061ADA8
+    Offset:          0xADA8
     Link:            .dynstr
     AddressAlign:    0x0000000000000008
     Content:         01000000000000000100000000000000010000000000000096000000000000000100000000000000C400000000000000010000000000000001010000000000000C0000000000000028224000000000000D000000000000005C29410000000000190000000000000028A36100000000001B0000000000000008000000000000001A0000000000000030A36100000000001C000000000000000800000000000000F5FEFF6F0000000098024000000000000500000000000000300F4000000000000600000000000000D0024000000000000A00000000000000BC050000000000000B00000000000000180000000000000015000000000000000000000000000000030000000000000000B0610000000000020000000000000000000000000000001400000000000000070000000000000017000000000000006017400000000000070000000000000088164000000000000800000000000000000000000000000009000000000000001800000000000000FEFFFF6F00000000F815400000000000FFFFFF6F000000000200000000000000F0FFFF6F00000000EC14400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 Symbols:
     - Name:            mydata
       Section:         .rodata
-      Value:           0x0000000000400100
+      Value:           0x0000000000400300
       Binding:         STB_GLOBAL
     - Name:            myfunc
       Type:            STT_FUNC
       Section:         .text
-      Value:           0x0000000000400000
+      Value:           0x0000000000400200
       Binding:         STB_GLOBAL
 DynamicSymbols:
     - Name:            mydata
       Section:         .rodata
       Value:           0x0000000000400100
       Binding:         STB_GLOBAL
 ProgramHeaders:
-  - Type: PT_PHDR
-    Flags: [ PF_X, PF_R ]
-    VAddr: 0x00400000
-    PAddr: 0x00400000
-    FirstSec: .text
-    LastSec: .text
   - Type: PT_LOAD
     Flags: [ PF_X, PF_R ]
     VAddr: 0x00400000
     PAddr: 0x00400000
+    Offset: 0x0
     FirstSec: .text
-    LastSec: .text
-  - Type: PT_DYNAMIC
-    Flags: [ PF_X, PF_R ]
+    LastSec: .rodata
+  - Type: PT_LOAD
+    Flags: [ PF_W, PF_R ]
     VAddr: 0x0061ADA8
-    PAddr: 0x0064ADA8
+    PAddr: 0x0061ADA8
     FirstSec: .dynamic
-    LastSec: .dynamic
+    LastSec: .dynstr
 ...

bolt/test/X86/branch-data.test

 # Checks that llvm-bolt is able to read data generated by perf2bolt and update
 # the CFG edges accordingly with absolute number of branches and mispredictions.
 # Also checks that llvm-bolt disassembler and CFG builder is working properly.
 
 RUN: yaml2obj %p/Inputs/blarge.yaml &> %t.exe
 RUN: llvm-bolt %t.exe -o /dev/null --data %p/Inputs/blarge.fdata --print-cfg | FileCheck %s
 
 CHECK:    Binary Function "usqrt"
 CHECK:      State       : CFG constructed
 CHECK:      Address     : 0x401170
 CHECK:      Size        : 0x43
 CHECK:      MaxSize     : 0x43
-CHECK:      Offset      : 0xcb0
+CHECK:      Offset      : 0x1170
 CHECK:      Section     : .text
 CHECK:      IsSimple    : 1
 CHECK:      BB Count    : 5
 CHECK:      Exec Count  : 199
 CHECK:      Branch Count: 7689
 CHECK:    }
 CHECK:    .LBB{{.*}}
 CHECK:      Exec Count : 199

bolt/test/X86/cfi-expr-rewrite.s

.LBB07:
   retq
 
   .cfi_endproc
 .size blake2b_compress_avx2, .-blake2b_compress_avx2
 .section .rodata
 "blake2b_IV/1":
 "DATAat0x4013a0":
 "DATAat0x401380":
+.long 0x0

bolt/test/X86/double-rel.s

 ## Check that BOLT can correctly use relocations to symbolize instruction
 ## operands when an instruction can have up to two relocations associated
 ## with it.
 
 # REQUIRES: system-linux
 
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-linux %s -o %t.o
 # RUN: ld.lld %t.o -o %t.exe -q --Tdata=0x80000
 # RUN: llvm-bolt %t.exe --relocs -o /dev/null --print-only=_start --print-disasm \
 # RUN:   | FileCheck %s --check-prefix=CHECK-BOLT
 # RUN: llvm-objdump -d --print-imm-hex %t.exe \
 # RUN:   | FileCheck %s --check-prefix=CHECK-OBJDUMP
 
   .data
   .globl VAR
 VAR:
-  .quad
+  .quad 0
 
   .text
   .globl _start
   .type _start,@function
 _start:
   .cfi_startproc
 
 ## VAR value is 0x80000. Using relocations, llvm-bolt should correctly

bolt/test/X86/dummy-eh-frame-bug.s

 # REQUIRES: system-linux
 
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-linux %s -o %t.o
 # RUN: ld.lld %t.o -o %t.exe -q
 # RUN: llvm-bolt %t.exe -o %t.bolt.exe --funcs=nocfi_function
 # RUN: llvm-readelf --section-headers %t.bolt.exe | FileCheck %s
 
 ## Check that llvm-bolt does not allocate unmarked space for original .eh_frame
 ## after .text when no update is needed to .eh_frame.
 
 # CHECK: {{ .text}} PROGBITS [[#%x,ADDR:]] [[#%x,OFFSET:]] [[#%x,SIZE:]]
-# CHECK-NEXT: 0000000000000000 [[#%x, OFFSET + SIZE]]
+# CHECK-NEXT: 0000000000000000 [[#%.6x, OFFSET + SIZE]]
 
   .text
   .globl nocfi_function
   .type nocfi_function,@function
 nocfi_function:
   ret
   .size nocfi_function, .-nocfi_function
 
   .globl _start
   .type _start,@function
 _start:
   .cfi_startproc
   call nocfi_function
   .size _start, .-_start
   .cfi_endproc

bolt/test/X86/section-end-sym.s

 ## Check that BOLT doesn't consider end-of-section symbols (e.g., _etext) as
 ## functions.
 
 # REQUIRES: x86_64-linux, asserts
 
 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-linux %s -o %t.o
 # RUN: ld.lld %t.o -o %t.exe -q
 # RUN: llvm-bolt %t.exe -o /dev/null --print-cfg --debug-only=bolt 2>&1 \
 # RUN:   | FileCheck %s
 
 # CHECK: considering symbol etext for function
-# CHECK-NEXT: rejecting as symbol points to end of its section
+# CHECK-NEXT: BOLT-INFO: etext is in the end of .text
 # CHECK-NOT: Binary Function "etext{{.*}}" after building cfg
 
-
   .text
   .globl _start
   .type _start,@function
 _start:
   retq
   .size _start, .-_start
 
   .align 0x1000
   .globl etext
 etext:
 
   .data
 .Lfoo:
   .word 0

bolt/test/reorder-data-writable-ptload.c

 // This test checks that reorder-data pass puts new hot .data section
 // to the writable segment.
 
 // RUN: %clang %cflags -O3 -nostdlib -Wl,-q %s -o %t.exe
 // RUN: llvm-bolt %t.exe -o %t.bolt --reorder-data=".data" \
 // RUN:   -data %S/Inputs/reorder-data-writable-ptload.fdata
 // RUN: llvm-readelf -SlW %t.bolt | FileCheck %s
 
-// CHECK: .bolt.org.data
-// CHECK: {{.*}} .data PROGBITS [[#%x,ADDR:]] [[#%x,OFF:]]
+// CHECK: .data
+// CHECK: {{.*}} .data.hot PROGBITS [[#%x,ADDR:]] [[#%x,OFF:]]
 // CHECK: LOAD 0x{{.*}}[[#OFF]] 0x{{.*}}[[#ADDR]] {{.*}} RW
 
 volatile int cold1 = 42;
 volatile int hot1 = 42;
 volatile int cold2 = 42;
 volatile int cold3 = 42;
 
 void _start() {
   hot1++;
   _start();
 }

bolt/test/runtime/AArch64/adrrelaxationpass.s

main:
   adr x3, br
 br:
   br x1
   .size main, .-main
 .CI:
   .word 0xff
 
 # CHECK: <main>:
-# CHECK-NEXT: adr x0, 0x{{[1-8a-f][0-9a-f]*}}
-# CHECK-NEXT: adrp x1, 0x{{[1-8a-f][0-9a-f]*}}
-# CHECK-NEXT: add x1, x1, #{{[1-8a-f][0-9a-f]*}}
-# CHECK-NEXT: adrp x2, 0x{{[1-8a-f][0-9a-f]*}}
-# CHECK-NEXT: add x2, x2, #{{[1-8a-f][0-9a-f]*}}
-# CHECK-NEXT: adr x3, 0x{{[1-8a-f][0-9a-f]*}}
+# CHECK-NEXT: adr x0, 0x{{[1-9a-f][0-9a-f]*}}
+# CHECK-NEXT: adrp x1, 0x{{[1-9a-f][0-9a-f]*}}
+# CHECK-NEXT: add x1, x1, #{{[1-9a-f][0-9a-f]*}}
+# CHECK-NEXT: adrp x2, 0x{{[1-9a-f][0-9a-f]*}}
+# CHECK-NEXT: add x2, x2, #{{[1-9a-f][0-9a-f]*}}
+# CHECK-NEXT: adr x3, 0x{{[1-9a-f][0-9a-f]*}}
 # CHECK-ERROR: BOLT-ERROR: Cannot relax adr in non-simple function main

bolt/unittests/Core/BinaryContext.cpp

 INSTANTIATE_TEST_SUITE_P(AArch64, BinaryContextTester,
                          ::testing::Values(Triple::aarch64));
 
 #endif
 
 TEST_P(BinaryContextTester, BaseAddress) {
   // Check that  base address calculation is correct for a binary with the
   // following segment layout:
-  BC->SegmentMapInfo[0] = SegmentInfo{0, 0x10e8c2b4, 0, 0x10e8c2b4, 0x1000};
+  BC->SegmentMapInfo[0] = ProgramHeader(ELF::PT_LOAD, ELF::PF_R, 0, 0, 0,
+                                        0x10e8c2b4, 0x10e8c2b4, 0x1000);
   BC->SegmentMapInfo[0x10e8d2b4] =
-      SegmentInfo{0x10e8d2b4, 0x3952faec, 0x10e8c2b4, 0x3952faec, 0x1000};
+      ProgramHeader(ELF::PT_LOAD, ELF::PF_R, 0x10e8c2b4, 0x10e8d2b4, 0x10e8d2b4,
+                    0x3952faec, 0x3952faec, 0x1000);
   BC->SegmentMapInfo[0x4a3bddc0] =
-      SegmentInfo{0x4a3bddc0, 0x148e828, 0x4a3bbdc0, 0x148e828, 0x1000};
+      ProgramHeader(ELF::PT_LOAD, ELF::PF_R, 0x4a3bbdc0, 0x4a3bddc0, 0x4a3bddc0,
+                    0x148e828, 0x148e828, 0x1000);
   BC->SegmentMapInfo[0x4b84d5e8] =
-      SegmentInfo{0x4b84d5e8, 0x294f830, 0x4b84a5e8, 0x3d3820, 0x1000};
-
+      ProgramHeader(ELF::PT_LOAD, ELF::PF_R, 0x4b84a5e8, 0x4b84d5e8, 0x4b84d5e8,
+                    0x3d3820, 0x294f830, 0x1000);
   std::optional<uint64_t> BaseAddress =
       BC->getBaseAddressForMapping(0x7f13f5556000, 0x10e8c000);
   ASSERT_TRUE(BaseAddress.has_value());
   ASSERT_EQ(*BaseAddress, 0x7f13e46c9000ULL);
 
   BaseAddress = BC->getBaseAddressForMapping(0x7f13f5556000, 0x137a000);
   ASSERT_FALSE(BaseAddress.has_value());
 }