[DAGCombine] Fold setcc equal to infinity into is.fpclass

[arsenm]

I think this is a backwards canonicalization decision and fabs + fcmp will be more broadly understood

llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll

1160 ↗

(On Diff #499361)

This improvement will be picked up whenever my patch to combine class+fcmp lands

[qiucf]

In D144534#4144155, @arsenm wrote:

I think this is a backwards canonicalization decision and fabs + fcmp will be more broadly understood

Do you think this peephole should exist in backend? For targets with hardware instruction supporting is.fpclass, the intrinsic is more efficient than fabs+fcmp. Or, after __builtin_isinf_sign producing is.fpclass from frontend, this will not be needed?

[arsenm]

In D144534#4146290, @qiucf wrote:

In D144534#4144155, @arsenm wrote:

I think this is a backwards canonicalization decision and fabs + fcmp will be more broadly understood

Do you think this peephole should exist in backend? For targets with hardware instruction supporting is.fpclass, the intrinsic is more efficient than fabs+fcmp. Or, after __builtin_isinf_sign producing is.fpclass from frontend, this will not be needed?

Yes, the backend should handle optimally lowering fcmp and is.fpclass depending on instruction availability

[arsenm]

I think this is better done in the backend. D143198 is the opposite direction but we could use both paths in the backend

[qiucf]

Implement in backend.

[arsenm]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4969

Is the advantage that you avoid materializing the inf constant? Can you check if the constantfp is legal?

4972

Could also handle the unordered case

4976

getTargetConstant

llvm/test/CodeGen/AMDGPU/fp-classify.ll

616

The result is the same but I’d somewhat prefer to keep the original isa. The infinity constant is more likely reusable with other uses in the program

[qiucf]

llvm/test/CodeGen/AMDGPU/fp-classify.ll

616

Fpclass checks are be better if the constant is used one or more times only in such comparison, I think?

[arsenm]

llvm/test/CodeGen/AMDGPU/fp-classify.ll

616

These have identical code size and cycles. I think an infinity constant is more likely to appear from unrelated function uses. Plus fcmp is a better canonical form. You should avoid this if you base on only doing the transform if the constant is illegal

[arsenm]

Should check if the constant is legal. Also handling the unordered case isn't much more work

[qiucf]

Migrated to https://github.com/llvm/llvm-project/pull/67829

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

         case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break;
         default: break;
         }
         if (NewCond != ISD::SETCC_INVALID &&
             isCondCodeLegal(NewCond, N0.getSimpleValueType()))
           return DAG.getSetCC(dl, VT, N0, N1, NewCond);
       }
     }
+
+    if (isOperationLegalOrCustom(ISD::IS_FPCLASS, N0.getValueType())) {
+      bool IsFabs = N0.getOpcode() == ISD::FABS;
+      SDValue Op = IsFabs ? N0.getOperand(0) : N0;
+      if (Cond == ISD::SETOEQ && CFP->isInfinity()) {
+        FPClassTest Flag = CFP->isNegative() ? (IsFabs ? fcNone : fcNegInf)
+                                             : (IsFabs ? fcInf : fcPosInf);
+        return DAG.getNode(ISD::IS_FPCLASS, dl, VT, Op,
+                           DAG.getConstant(Flag, dl, MVT::i32, true));
+      }
+    }
   }
 
   if (N0 == N1) {
     // The sext(setcc()) => setcc() optimization relies on the appropriate
     // constant being emitted.
     assert(!N0.getValueType().isInteger() &&
            "Integer types should be handled by FoldSetCC");
 

llvm/test/CodeGen/AMDGPU/fp-classify.ll

 
 define amdgpu_kernel void @test_isinf_pattern_f16(ptr addrspace(1) nocapture %out, half %x) #0 {
 ; SI-LABEL: test_isinf_pattern_f16:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; SI-NEXT:    s_load_dword s0, s[0:1], 0xb
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
-; SI-NEXT:    s_mov_b32 s1, 0x7f800000
+; SI-NEXT:    v_mov_b32_e32 v0, 0x200
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_cvt_f32_f16_e64 v0, |s0|
-; SI-NEXT:    v_cmp_eq_f32_e32 vcc, s1, v0
+; SI-NEXT:    v_cvt_f32_f16_e64 v1, |s0|
+; SI-NEXT:    v_cmp_class_f32_e32 vcc, v1, v0
 ; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
 ; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_isinf_pattern_f16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

llvm/test/CodeGen/AMDGPU/fract-match.ll

 ; GFX6-NEXT:    v_floor_f32_e32 v4, v0
 ; GFX6-NEXT:    v_sub_f32_e32 v6, v1, v5
 ; GFX6-NEXT:    v_sub_f32_e32 v7, v0, v4
 ; GFX6-NEXT:    v_min_f32_e32 v6, 0x3f7fffff, v6
 ; GFX6-NEXT:    v_cmp_u_f32_e32 vcc, v1, v1
 ; GFX6-NEXT:    v_min_f32_e32 v7, 0x3f7fffff, v7
 ; GFX6-NEXT:    v_cndmask_b32_e32 v6, v6, v1, vcc
 ; GFX6-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
-; GFX6-NEXT:    s_movk_i32 s10, 0x204
+; GFX6-NEXT:    v_mov_b32_e32 v8, 0x200
 ; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v0, vcc
-; GFX6-NEXT:    v_cmp_class_f32_e64 s[8:9], v0, s10
+; GFX6-NEXT:    v_cmp_class_f32_e64 s[8:9], |v0|, v8
 ; GFX6-NEXT:    s_mov_b32 s6, 0
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v7, 0, s[8:9]
-; GFX6-NEXT:    v_cmp_class_f32_e64 s[8:9], v1, s10
+; GFX6-NEXT:    v_cmp_class_f32_e64 s[8:9], |v1|, v8
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s4, s6
 ; GFX6-NEXT:    s_mov_b32 s5, s6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v6, 0, s[8:9]
 ; GFX6-NEXT:    buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;

 ; GFX7-NEXT:    buffer_store_dword v7, v[2:3], s[4:7], 0 addr64
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: safe_math_fract_v2f16:
 ; GFX8:       ; %bb.0: ; %entry
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX8-NEXT:    s_movk_i32 s6, 0x204
+; GFX8-NEXT:    v_mov_b32_e32 v7, 0x200
 ; GFX8-NEXT:    v_floor_f16_e32 v4, v3
 ; GFX8-NEXT:    v_floor_f16_e32 v5, v0
 ; GFX8-NEXT:    v_fract_f16_e32 v6, v3
-; GFX8-NEXT:    v_cmp_class_f16_e64 s[4:5], v3, s6
+; GFX8-NEXT:    v_cmp_class_f16_e64 s[4:5], |v3|, v7
 ; GFX8-NEXT:    v_pack_b32_f16 v4, v5, v4
 ; GFX8-NEXT:    v_fract_f16_e32 v5, v0
 ; GFX8-NEXT:    v_cndmask_b32_e64 v3, v6, 0, s[4:5]
-; GFX8-NEXT:    v_cmp_class_f16_e64 s[4:5], v0, s6
+; GFX8-NEXT:    v_cmp_class_f16_e64 s[4:5], |v0|, v7
 ; GFX8-NEXT:    v_cndmask_b32_e64 v0, v5, 0, s[4:5]
 ; GFX8-NEXT:    v_pack_b32_f16 v0, v0, v3
 ; GFX8-NEXT:    global_store_dword v[1:2], v4, off
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: safe_math_fract_v2f16:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; GFX11-NEXT:    v_fract_f16_e32 v6, v0
 ; GFX11-NEXT:    v_floor_f16_e32 v5, v0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
 ; GFX11-NEXT:    v_fract_f16_e32 v4, v3
-; GFX11-NEXT:    v_cmp_class_f16_e64 s0, v3, 0x204
+; GFX11-NEXT:    v_cmp_class_f16_e64 s0, |v3|, 0x200
 ; GFX11-NEXT:    v_floor_f16_e32 v7, v3
 ; GFX11-NEXT:    v_cndmask_b32_e64 v3, v4, 0, s0
-; GFX11-NEXT:    v_cmp_class_f16_e64 s0, v0, 0x204
+; GFX11-NEXT:    v_cmp_class_f16_e64 s0, |v0|, 0x200
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
 ; GFX11-NEXT:    v_pack_b32_f16 v4, v5, v7
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, v6, 0, s0
 ; GFX11-NEXT:    global_store_b32 v[1:2], v4, off
 ; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v3
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:

 ; GFX6-NEXT:    s_mov_b32 s9, 0x3fefffff
 ; GFX6-NEXT:    v_add_f64 v[12:13], v[0:1], -v[6:7]
 ; GFX6-NEXT:    v_min_f64 v[10:11], v[10:11], s[8:9]
 ; GFX6-NEXT:    v_cmp_u_f64_e32 vcc, v[2:3], v[2:3]
 ; GFX6-NEXT:    v_min_f64 v[12:13], v[12:13], s[8:9]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v11, v11, v3, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e32 v10, v10, v2, vcc
 ; GFX6-NEXT:    v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
-; GFX6-NEXT:    s_movk_i32 s10, 0x204
-; GFX6-NEXT:    v_cmp_class_f64_e64 s[8:9], v[0:1], s10
+; GFX6-NEXT:    v_mov_b32_e32 v14, 0x200
+; GFX6-NEXT:    v_cmp_class_f64_e64 s[8:9], |v[0:1]|, v14
 ; GFX6-NEXT:    v_cndmask_b32_e32 v13, v13, v1, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e32 v12, v12, v0, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v12, 0, s[8:9]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v13, 0, s[8:9]
-; GFX6-NEXT:    v_cmp_class_f64_e64 s[8:9], v[2:3], s10
+; GFX6-NEXT:    v_cmp_class_f64_e64 s[8:9], |v[2:3]|, v14
 ; GFX6-NEXT:    s_mov_b32 s6, 0
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s4, s6
 ; GFX6-NEXT:    s_mov_b32 s5, s6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v10, 0, s[8:9]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, v11, 0, s[8:9]
 ; GFX6-NEXT:    buffer_store_dwordx4 v[6:9], v[4:5], s[4:7], 0 addr64
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX7-LABEL: safe_math_fract_v2f64:
 ; GFX7:       ; %bb.0: ; %entry
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    s_movk_i32 s4, 0x204
+; GFX7-NEXT:    v_mov_b32_e32 v6, 0x200
 ; GFX7-NEXT:    v_fract_f64_e32 v[10:11], v[0:1]
-; GFX7-NEXT:    v_cmp_class_f64_e64 s[8:9], v[0:1], s4
+; GFX7-NEXT:    v_cmp_class_f64_e64 s[8:9], |v[0:1]|, v6
 ; GFX7-NEXT:    v_fract_f64_e32 v[12:13], v[2:3]
-; GFX7-NEXT:    v_cmp_class_f64_e64 s[10:11], v[2:3], s4
+; GFX7-NEXT:    v_cmp_class_f64_e64 s[10:11], |v[2:3]|, v6
 ; GFX7-NEXT:    v_floor_f64_e32 v[8:9], v[2:3]
 ; GFX7-NEXT:    v_floor_f64_e32 v[6:7], v[0:1]
 ; GFX7-NEXT:    s_mov_b32 s6, 0
 ; GFX7-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX7-NEXT:    s_mov_b32 s4, s6
 ; GFX7-NEXT:    s_mov_b32 s5, s6
 ; GFX7-NEXT:    v_cndmask_b32_e64 v0, v10, 0, s[8:9]
 ; GFX7-NEXT:    v_cndmask_b32_e64 v1, v11, 0, s[8:9]
 ; GFX7-NEXT:    v_cndmask_b32_e64 v2, v12, 0, s[10:11]
 ; GFX7-NEXT:    v_cndmask_b32_e64 v3, v13, 0, s[10:11]
 ; GFX7-NEXT:    buffer_store_dwordx4 v[6:9], v[4:5], s[4:7], 0 addr64
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: safe_math_fract_v2f64:
 ; GFX8:       ; %bb.0: ; %entry
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    s_movk_i32 s6, 0x204
+; GFX8-NEXT:    v_mov_b32_e32 v6, 0x200
 ; GFX8-NEXT:    v_fract_f64_e32 v[10:11], v[0:1]
-; GFX8-NEXT:    v_cmp_class_f64_e64 s[4:5], v[0:1], s6
+; GFX8-NEXT:    v_cmp_class_f64_e64 s[4:5], |v[0:1]|, v6
 ; GFX8-NEXT:    v_fract_f64_e32 v[12:13], v[2:3]
-; GFX8-NEXT:    v_cmp_class_f64_e64 s[6:7], v[2:3], s6
+; GFX8-NEXT:    v_cmp_class_f64_e64 s[6:7], |v[2:3]|, v6
 ; GFX8-NEXT:    v_floor_f64_e32 v[8:9], v[2:3]
 ; GFX8-NEXT:    v_floor_f64_e32 v[6:7], v[0:1]
 ; GFX8-NEXT:    v_cndmask_b32_e64 v0, v10, 0, s[4:5]
 ; GFX8-NEXT:    v_cndmask_b32_e64 v1, v11, 0, s[4:5]
 ; GFX8-NEXT:    v_cndmask_b32_e64 v2, v12, 0, s[6:7]
 ; GFX8-NEXT:    v_cndmask_b32_e64 v3, v13, 0, s[6:7]
 ; GFX8-NEXT:    global_store_dwordx4 v[4:5], v[6:9], off
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: safe_math_fract_v2f64:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX11-NEXT:    v_fract_f64_e32 v[10:11], v[0:1]
-; GFX11-NEXT:    v_cmp_class_f64_e64 s0, v[0:1], 0x204
+; GFX11-NEXT:    v_cmp_class_f64_e64 s0, |v[0:1]|, 0x200
 ; GFX11-NEXT:    v_fract_f64_e32 v[12:13], v[2:3]
-; GFX11-NEXT:    v_cmp_class_f64_e64 s1, v[2:3], 0x204
+; GFX11-NEXT:    v_cmp_class_f64_e64 s1, |v[2:3]|, 0x200
 ; GFX11-NEXT:    v_floor_f64_e32 v[8:9], v[2:3]
 ; GFX11-NEXT:    v_floor_f64_e32 v[6:7], v[0:1]
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, v10, 0, s0
 ; GFX11-NEXT:    v_cndmask_b32_e64 v1, v11, 0, s0
 ; GFX11-NEXT:    v_cndmask_b32_e64 v2, v12, 0, s1
 ; GFX11-NEXT:    v_cndmask_b32_e64 v3, v13, 0, s1
 ; GFX11-NEXT:    global_store_b128 v[4:5], v[6:9], off
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0

llvm/test/CodeGen/PowerPC/fp-classify.ll

 ; P8-NEXT:    lfs 1, .LCPI0_0@toc@l(3)
 ; P8-NEXT:    li 3, 0
 ; P8-NEXT:    fcmpu 0, 0, 1
 ; P8-NEXT:    iseleq 3, 4, 3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinff:
 ; P9:       # %bb.0: # %entry
-; P9-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; P9-NEXT:    xsabsdp 0, 1
-; P9-NEXT:    li 4, 1
-; P9-NEXT:    lfs 1, .LCPI0_0@toc@l(3)
+; P9-NEXT:    xststdcsp 0, 1, 48
 ; P9-NEXT:    li 3, 0
-; P9-NEXT:    fcmpu 0, 0, 1
+; P9-NEXT:    li 4, 1
 ; P9-NEXT:    iseleq 3, 4, 3
 ; P9-NEXT:    blr
 entry:
   %0 = tail call float @llvm.fabs.f32(float %x)
   %cmpinf = fcmp oeq float %0, 0x7FF0000000000000
   ret i1 %cmpinf
 }
 
 define zeroext i1 @abs_isinf(double %x) {
 ; P8-LABEL: abs_isinf:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    xsabsdp 0, 1
 ; P8-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; P8-NEXT:    li 4, 1
 ; P8-NEXT:    lfs 1, .LCPI1_0@toc@l(3)
 ; P8-NEXT:    li 3, 0
 ; P8-NEXT:    fcmpu 0, 0, 1
 ; P8-NEXT:    iseleq 3, 4, 3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinf:
 ; P9:       # %bb.0: # %entry
-; P9-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
-; P9-NEXT:    xsabsdp 0, 1
-; P9-NEXT:    li 4, 1
-; P9-NEXT:    lfs 1, .LCPI1_0@toc@l(3)
+; P9-NEXT:    xststdcdp 0, 1, 48
 ; P9-NEXT:    li 3, 0
-; P9-NEXT:    fcmpu 0, 0, 1
+; P9-NEXT:    li 4, 1
 ; P9-NEXT:    iseleq 3, 4, 3
 ; P9-NEXT:    blr
 entry:
   %0 = tail call double @llvm.fabs.f64(double %x)
   %cmpinf = fcmp oeq double %0, 0x7FF0000000000000
   ret i1 %cmpinf
 }
 

 ; P8-NEXT:    srwi 3, 3, 5
 ; P8-NEXT:    addi 1, 1, 48
 ; P8-NEXT:    ld 0, 16(1)
 ; P8-NEXT:    mtlr 0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinfq:
 ; P9:       # %bb.0: # %entry
-; P9-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; P9-NEXT:    xsabsqp 2, 2
-; P9-NEXT:    li 4, 1
-; P9-NEXT:    addi 3, 3, .LCPI2_0@toc@l
-; P9-NEXT:    lxv 35, 0(3)
+; P9-NEXT:    xststdcqp 0, 2, 48
 ; P9-NEXT:    li 3, 0
-; P9-NEXT:    xscmpuqp 0, 2, 3
+; P9-NEXT:    li 4, 1
 ; P9-NEXT:    iseleq 3, 4, 3
 ; P9-NEXT:    blr
 entry:
   %0 = tail call fp128 @llvm.fabs.f128(fp128 %x)
   %cmpinf = fcmp oeq fp128 %0, 0xL00000000000000007FFF000000000000
   ret i1 %cmpinf
 }