[DAGCombine] Fold setcc equal to infinity into is.fpclass

[arsenm]

I think this is a backwards canonicalization decision and fabs + fcmp will be more broadly understood

llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll

1160 ↗

(On Diff #499361)

This improvement will be picked up whenever my patch to combine class+fcmp lands

[qiucf]

In D144534#4144155, @arsenm wrote:

I think this is a backwards canonicalization decision and fabs + fcmp will be more broadly understood

Do you think this peephole should exist in backend? For targets with hardware instruction supporting is.fpclass, the intrinsic is more efficient than fabs+fcmp. Or, after __builtin_isinf_sign producing is.fpclass from frontend, this will not be needed?

[arsenm]

In D144534#4146290, @qiucf wrote:

In D144534#4144155, @arsenm wrote:

I think this is a backwards canonicalization decision and fabs + fcmp will be more broadly understood

Do you think this peephole should exist in backend? For targets with hardware instruction supporting is.fpclass, the intrinsic is more efficient than fabs+fcmp. Or, after __builtin_isinf_sign producing is.fpclass from frontend, this will not be needed?

Yes, the backend should handle optimally lowering fcmp and is.fpclass depending on instruction availability

[arsenm]

I think this is better done in the backend. D143198 is the opposite direction but we could use both paths in the backend

[qiucf]

Implement in backend.

[arsenm]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4969

Is the advantage that you avoid materializing the inf constant? Can you check if the constantfp is legal?

4972

Could also handle the unordered case

4976

getTargetConstant

llvm/test/CodeGen/AMDGPU/fp-classify.ll

616 ↗

(On Diff #534885)

The result is the same but I’d somewhat prefer to keep the original isa. The infinity constant is more likely reusable with other uses in the program

[qiucf]

llvm/test/CodeGen/AMDGPU/fp-classify.ll

616 ↗

(On Diff #534885)

Fpclass checks are be better if the constant is used one or more times only in such comparison, I think?

[arsenm]

llvm/test/CodeGen/AMDGPU/fp-classify.ll

616 ↗

(On Diff #534885)

These have identical code size and cycles. I think an infinity constant is more likely to appear from unrelated function uses. Plus fcmp is a better canonical form. You should avoid this if you base on only doing the transform if the constant is illegal

[arsenm]

Should check if the constant is legal. Also handling the unordered case isn't much more work

[qiucf]

Migrated to https://github.com/llvm/llvm-project/pull/67829

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

         (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
         (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) &&
         N0.getOpcode() == ISD::AND) {
       if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
         EVT ShiftTy =
             getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize());
         if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
           // Perform the xform if the AND RHS is a single bit.
           unsigned ShCt = AndRHS->getAPIntValue().logBase2();
           if (AndRHS->getAPIntValue().isPowerOf2() &&
               !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) {
             return DAG.getNode(ISD::TRUNCATE, dl, VT,
                                DAG.getNode(ISD::SRL, dl, ShValTy, N0,
                                            DAG.getConstant(ShCt, dl, ShiftTy)));
           }
         } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
           // (X & 8) == 8  -->  (X & 8) >> 3

       ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond);
       if (DCI.isBeforeLegalizeOps() ||
           isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
         SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
         return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
       }
     }
 
+    if (isOperationLegalOrCustom(ISD::IS_FPCLASS, N0.getValueType()) &&
+        !isFPImmLegal(CFP->getValueAPF(), CFP->getValueType(0))) {
+      bool IsFabs = N0.getOpcode() == ISD::FABS;
+      SDValue Op = IsFabs ? N0.getOperand(0) : N0;
+      if ((Cond == ISD::SETOEQ || Cond == ISD::SETUEQ) && CFP->isInfinity()) {
+        FPClassTest Flag = CFP->isNegative() ? (IsFabs ? fcNone : fcNegInf)
+                                             : (IsFabs ? fcInf : fcPosInf);
+        if (Cond == ISD::SETUEQ)
+          Flag |= fcNan;
+        return DAG.getNode(ISD::IS_FPCLASS, dl, VT, Op,
+                           DAG.getTargetConstant(Flag, dl, MVT::i32));
+      }
+    }
+
     // If the condition is not legal, see if we can find an equivalent one
     // which is legal.
     if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
       // If the comparison was an awkward floating-point == or != and one of
       // the comparison operands is infinity or negative infinity, convert the
       // condition to a less-awkward <= or >=.
       if (CFP->getValueAPF().isInfinity()) {
         bool IsNegInf = CFP->getValueAPF().isNegative();

llvm/test/CodeGen/PowerPC/fp-classify.ll

 ; P8-NEXT:    lfs 1, .LCPI0_0@toc@l(3)
 ; P8-NEXT:    li 3, 0
 ; P8-NEXT:    fcmpu 0, 0, 1
 ; P8-NEXT:    iseleq 3, 4, 3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinff:
 ; P9:       # %bb.0: # %entry
-; P9-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; P9-NEXT:    xsabsdp 0, 1
-; P9-NEXT:    li 4, 1
-; P9-NEXT:    lfs 1, .LCPI0_0@toc@l(3)
+; P9-NEXT:    xststdcsp 0, 1, 48
 ; P9-NEXT:    li 3, 0
-; P9-NEXT:    fcmpu 0, 0, 1
+; P9-NEXT:    li 4, 1
 ; P9-NEXT:    iseleq 3, 4, 3
 ; P9-NEXT:    blr
 entry:
   %0 = tail call float @llvm.fabs.f32(float %x)
   %cmpinf = fcmp oeq float %0, 0x7FF0000000000000
   ret i1 %cmpinf
 }
 
 define zeroext i1 @abs_isinf(double %x) {
 ; P8-LABEL: abs_isinf:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; P8-NEXT:    xsabsdp 0, 1
 ; P8-NEXT:    li 4, 1
 ; P8-NEXT:    lfs 1, .LCPI1_0@toc@l(3)
 ; P8-NEXT:    li 3, 0
 ; P8-NEXT:    fcmpu 0, 0, 1
 ; P8-NEXT:    iseleq 3, 4, 3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinf:
 ; P9:       # %bb.0: # %entry
-; P9-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
-; P9-NEXT:    xsabsdp 0, 1
-; P9-NEXT:    li 4, 1
-; P9-NEXT:    lfs 1, .LCPI1_0@toc@l(3)
+; P9-NEXT:    xststdcdp 0, 1, 48
 ; P9-NEXT:    li 3, 0
-; P9-NEXT:    fcmpu 0, 0, 1
+; P9-NEXT:    li 4, 1
 ; P9-NEXT:    iseleq 3, 4, 3
 ; P9-NEXT:    blr
 entry:
   %0 = tail call double @llvm.fabs.f64(double %x)
   %cmpinf = fcmp oeq double %0, 0x7FF0000000000000
   ret i1 %cmpinf
 }
 

 ; P8-NEXT:    srwi 3, 3, 5
 ; P8-NEXT:    addi 1, 1, 48
 ; P8-NEXT:    ld 0, 16(1)
 ; P8-NEXT:    mtlr 0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinfq:
 ; P9:       # %bb.0: # %entry
-; P9-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; P9-NEXT:    xsabsqp 2, 2
-; P9-NEXT:    li 4, 1
-; P9-NEXT:    addi 3, 3, .LCPI2_0@toc@l
-; P9-NEXT:    lxv 35, 0(3)
+; P9-NEXT:    xststdcqp 0, 2, 48
 ; P9-NEXT:    li 3, 0
-; P9-NEXT:    xscmpuqp 0, 2, 3
+; P9-NEXT:    li 4, 1
 ; P9-NEXT:    iseleq 3, 4, 3
 ; P9-NEXT:    blr
 entry:
   %0 = tail call fp128 @llvm.fabs.f128(fp128 %x)
   %cmpinf = fcmp oeq fp128 %0, 0xL00000000000000007FFF000000000000
   ret i1 %cmpinf
 }
 
 define zeroext i1 @abs_isinfornanf(float %x) {
 ; P8-LABEL: abs_isinfornanf:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; P8-NEXT:    xsabsdp 0, 1
 ; P8-NEXT:    lfs 1, .LCPI3_0@toc@l(3)
 ; P8-NEXT:    li 3, 1
 ; P8-NEXT:    fcmpu 0, 0, 1
 ; P8-NEXT:    isellt 3, 0, 3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinfornanf:
 ; P9:       # %bb.0: # %entry
-; P9-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; P9-NEXT:    xsabsdp 0, 1
-; P9-NEXT:    lfs 1, .LCPI3_0@toc@l(3)
-; P9-NEXT:    li 3, 1
-; P9-NEXT:    fcmpu 0, 0, 1
-; P9-NEXT:    isellt 3, 0, 3
+; P9-NEXT:    xststdcsp 0, 1, 112
+; P9-NEXT:    li 3, 0
+; P9-NEXT:    li 4, 1
+; P9-NEXT:    iseleq 3, 4, 3
 ; P9-NEXT:    blr
 entry:
   %0 = tail call float @llvm.fabs.f32(float %x)
   %cmpinf = fcmp ueq float %0, 0x7FF0000000000000
   ret i1 %cmpinf
 }
 
 define zeroext i1 @abs_isinfornan(double %x) {
 ; P8-LABEL: abs_isinfornan:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
 ; P8-NEXT:    xsabsdp 0, 1
 ; P8-NEXT:    lfs 1, .LCPI4_0@toc@l(3)
 ; P8-NEXT:    li 3, 1
 ; P8-NEXT:    fcmpu 0, 0, 1
 ; P8-NEXT:    isellt 3, 0, 3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinfornan:
 ; P9:       # %bb.0: # %entry
-; P9-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; P9-NEXT:    xsabsdp 0, 1
-; P9-NEXT:    lfs 1, .LCPI4_0@toc@l(3)
-; P9-NEXT:    li 3, 1
-; P9-NEXT:    fcmpu 0, 0, 1
-; P9-NEXT:    isellt 3, 0, 3
+; P9-NEXT:    xststdcdp 0, 1, 112
+; P9-NEXT:    li 3, 0
+; P9-NEXT:    li 4, 1
+; P9-NEXT:    iseleq 3, 4, 3
 ; P9-NEXT:    blr
 entry:
   %0 = tail call double @llvm.fabs.f64(double %x)
   %cmpinf = fcmp ueq double %0, 0x7FF0000000000000
   ret i1 %cmpinf
 }
 
 define zeroext i1 @abs_isinfornanq(fp128 %x) {

 ; P8-NEXT:    ld 30, 96(1) # 8-byte Folded Reload
 ; P8-NEXT:    addi 1, 1, 112
 ; P8-NEXT:    ld 0, 16(1)
 ; P8-NEXT:    mtlr 0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinfornanq:
 ; P9:       # %bb.0: # %entry
-; P9-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; P9-NEXT:    xsabsqp 2, 2
-; P9-NEXT:    addi 3, 3, .LCPI5_0@toc@l
-; P9-NEXT:    lxv 35, 0(3)
-; P9-NEXT:    li 3, 1
-; P9-NEXT:    xscmpuqp 0, 2, 3
-; P9-NEXT:    isellt 3, 0, 3
+; P9-NEXT:    xststdcqp 0, 2, 112
+; P9-NEXT:    li 3, 0
+; P9-NEXT:    li 4, 1
+; P9-NEXT:    iseleq 3, 4, 3
 ; P9-NEXT:    blr
 entry:
   %0 = tail call fp128 @llvm.fabs.f128(fp128 %x)
   %cmpinf = fcmp ueq fp128 %0, 0xL00000000000000007FFF000000000000
   ret i1 %cmpinf
 }
 
 define <4 x i1> @abs_isinfv4f32(<4 x float> %x) {

llvm/test/CodeGen/PowerPC/is_fpclass.ll

 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516)  ; 0x204 = "inf"
   ret i1 %1
 }
 
 define i1 @isinf_ppc_fp128(ppc_fp128 %x) nounwind {
 ; CHECK-LABEL: isinf_ppc_fp128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
-; CHECK-NEXT:    xsabsdp 0, 1
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    lfs 1, .LCPI9_0@toc@l(3)
+; CHECK-NEXT:    xststdcdp 0, 1, 48
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    fcmpu 0, 0, 1
+; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 516)  ; 0x204 = "inf"
   ret i1 %1
 }
 
 define i1 @isinf_f128(fp128 %x) nounwind {
 ; CHECK-LABEL: isinf_f128: