[DAGCombine] Fold setcc equal to infinity into is.fpclass

[arsenm]

I think this is a backwards canonicalization decision and fabs + fcmp will be more broadly understood

llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll

1160

This improvement will be picked up whenever my patch to combine class+fcmp lands

[qiucf]

In D144534#4144155, @arsenm wrote:

I think this is a backwards canonicalization decision and fabs + fcmp will be more broadly understood

Do you think this peephole should exist in backend? For targets with hardware instruction supporting is.fpclass, the intrinsic is more efficient than fabs+fcmp. Or, after __builtin_isinf_sign producing is.fpclass from frontend, this will not be needed?

[arsenm]

In D144534#4146290, @qiucf wrote:

In D144534#4144155, @arsenm wrote:

I think this is a backwards canonicalization decision and fabs + fcmp will be more broadly understood

Do you think this peephole should exist in backend? For targets with hardware instruction supporting is.fpclass, the intrinsic is more efficient than fabs+fcmp. Or, after __builtin_isinf_sign producing is.fpclass from frontend, this will not be needed?

Yes, the backend should handle optimally lowering fcmp and is.fpclass depending on instruction availability

[arsenm]

I think this is better done in the backend. D143198 is the opposite direction but we could use both paths in the backend

[qiucf]

Implement in backend.

[arsenm]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4969 ↗

(On Diff #534885)

Is the advantage that you avoid materializing the inf constant? Can you check if the constantfp is legal?

4972 ↗

(On Diff #534885)

Could also handle the unordered case

4976 ↗

(On Diff #534885)

getTargetConstant

llvm/test/CodeGen/AMDGPU/fp-classify.ll

616 ↗

(On Diff #534885)

The result is the same but I’d somewhat prefer to keep the original isa. The infinity constant is more likely reusable with other uses in the program

[qiucf]

llvm/test/CodeGen/AMDGPU/fp-classify.ll

616 ↗

(On Diff #534885)

Fpclass checks are be better if the constant is used one or more times only in such comparison, I think?

[arsenm]

llvm/test/CodeGen/AMDGPU/fp-classify.ll

616 ↗

(On Diff #534885)

These have identical code size and cycles. I think an infinity constant is more likely to appear from unrelated function uses. Plus fcmp is a better canonical form. You should avoid this if you base on only doing the transform if the constant is illegal

[arsenm]

Should check if the constant is legal. Also handling the unordered case isn't much more work

[qiucf]

Migrated to https://github.com/llvm/llvm-project/pull/67829

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

 
   // Get swapped predicate if necessary.
   if (C->isNegative())
     Pred = I.getSwappedPredicate();
 
   return new FCmpInst(Pred, LHSI->getOperand(1), RHSC, "", &I);
 }
 
-/// Optimize fabs(X) compared with zero.
-static Instruction *foldFabsWithFcmpZero(FCmpInst &I, InstCombinerImpl &IC) {
+/// Optimize fabs(X) compared with zero or infinities.
+static Instruction *foldFabsWithFcmp(FCmpInst &I, InstCombinerImpl &IC) {
   Value *X;
   if (!match(I.getOperand(0), m_FAbs(m_Value(X))))
     return nullptr;
 
   const APFloat *C;
   if (!match(I.getOperand(1), m_APFloat(C)))
     return nullptr;
 
+  if (C->isPosInfinity() && I.getPredicate() == CmpInst::FCMP_OEQ)
+    return CallInst::Create(
+        Intrinsic::getDeclaration(I.getModule(), Intrinsic::is_fpclass,
+                                  X->getType()),
+        {X, ConstantInt::get(Type::getInt32Ty(I.getContext()), fcInf)});
+
   if (!C->isPosZero()) {
     if (!C->isSmallestNormalized())
       return nullptr;
 
     const Function *F = I.getFunction();
     DenormalMode Mode = F->getDenormalMode(C->getSemantics());
     if (Mode.Input == DenormalMode::PreserveSign ||
         Mode.Input == DenormalMode::PositiveZero) {

         if (auto *GV = dyn_cast<GlobalVariable>(GEP->getOperand(0)))
           if (Instruction *Res = foldCmpLoadFromIndexedGlobal(
                   cast<LoadInst>(LHSI), GEP, GV, I))
             return Res;
       break;
   }
   }
 
-  if (Instruction *R = foldFabsWithFcmpZero(I, *this))
+  if (Instruction *R = foldFabsWithFcmp(I, *this))
     return R;
 
   if (match(Op0, m_FNeg(m_Value(X)))) {
     // fcmp pred (fneg X), C --> fcmp swap(pred) X, -C
     Constant *C;
     if (match(Op1, m_Constant(C)))
       if (Constant *NegC = ConstantFoldUnaryOpOperand(Instruction::FNeg, C, DL))
         return new FCmpInst(I.getSwappedPredicate(), X, NegC, "", &I);

llvm/test/Transforms/InstCombine/and-fcmp.ll

   %cmp = fcmp ule half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
 ; ueq -> oeq
 define i1 @clang_builtin_isnormal_inf_check_ueq(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_ueq(
-; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp ueq half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }

   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp ole half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_oeq(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_oeq(
-; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[CMP:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
+; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp oeq half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 

llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll

   %cmpzero = fcmp oeq <2 x half> %x, zeroinitializer
   %class = or <2 x i1> %cmpinf, %cmpzero
   ret <2 x i1> %class
 }
 
 ; Positive test
 define i1 @oeq_isinf_or_oeq_zero(half %x) {
 ; CHECK-LABEL: @oeq_isinf_or_oeq_zero(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
 ; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
 ; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmpzero = fcmp oeq half %x, 0xH0000
   %class = or i1 %cmpzero, %cmpinf

   %cmpzero = fcmp oeq half %x, 0xH0000
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }
 
 ; Extra fabs.
 define i1 @oeq_isinf_or_fabs_oeq_zero(half %x) {
 ; CHECK-LABEL: @oeq_isinf_or_fabs_oeq_zero(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
 ; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
 ; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmpzero = fcmp oeq half %fabs, 0xH0000
   %class = or i1 %cmpzero, %cmpinf

   %cmpzero = fcmp une half %x, 0.0
   %cmpinf = fcmp une half %x, 0xHFC00
   %or = or i1 %cmpzero, %cmpinf
   ret i1 %or
 }
 
 define i1 @issubnormal_or_inf(half %x) {
 ; CHECK-LABEL: @issubnormal_or_inf(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
+; CHECK-NEXT:    ret i1 [[CMPINF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
   %class = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %class
 }
 
 define i1 @olt_smallest_normal_or_inf(half %x) {
 ; CHECK-LABEL: @olt_smallest_normal_or_inf(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 764)
+; CHECK-NEXT:    ret i1 [[CMPINF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp olt half %x, 0xH0400 ; missing fabs
   %class = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %class
 }
 

   %cmpinf = fcmp une half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp uge half %fabs, 0xH0400
   %not = and i1 %cmp.smallest.normal, %cmpinf
   ret i1 %not
 }
 
 define i1 @issubnormal_uge_or_inf(half %x) {
 ; CHECK-LABEL: @issubnormal_uge_or_inf(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[FABS]], 0xH0400
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
+; CHECK-NEXT:    ret i1 [[CMPINF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp uge half %fabs, 0xH0400
   %class = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %class
 }
 
 ; Negative test, not smallest normal
 define i1 @issubnormal_or_inf_wrong_val(half %x) {
 ; CHECK-LABEL: @issubnormal_or_inf_wrong_val(
 ; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 516)
 ; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0401
 ; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp olt half %fabs, 0xH0401
   %class = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %class
 }
 
 define i1 @issubnormal_or_inf_neg_smallest_normal(half %x) {
 ; CHECK-LABEL: @issubnormal_or_inf_neg_smallest_normal(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
 ; CHECK-NEXT:    ret i1 [[CMPINF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp olt half %fabs, 0xH8400
   %class = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %class
 }
 
 define i1 @fneg_fabs_olt_neg_smallest_normal_or_inf(half %x) {
 ; CHECK-LABEL: @fneg_fabs_olt_neg_smallest_normal_or_inf(
 ; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 516)
 ; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp ogt half [[FABS]], 0xH0400
 ; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %fneg.fabs = fneg half %fabs
   %cmp.smallest.normal = fcmp olt half %fneg.fabs, 0xH8400

 }
 
 ; --------------------------------------------------------------------
 ; Test ord/uno
 ; --------------------------------------------------------------------
 
 define i1 @is_finite_and_ord(half %x) {
 ; CHECK-LABEL: @is_finite_and_ord(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %is.finite = fcmp ueq half %fabs, 0xH7C00
   %ord = fcmp ord half %x, %x
   %and = and i1 %ord, %is.finite
   ret i1 %and
 }
 

   %is.finite = fcmp ueq half %fabs, 0xH7C00
   %uno = fcmp uno half %x, %x
   %or = or i1 %uno, %is.finite
   ret i1 %or
 }
 
 define i1 @oeq_isinf_or_uno(half %x) {
 ; CHECK-LABEL: @oeq_isinf_or_uno(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPINF]], [[UNO]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 519)
+; CHECK-NEXT:    ret i1 [[CMPINF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %uno = fcmp uno half %x, 0xH0000
   %class = or i1 %cmpinf, %uno
   ret i1 %class
 }
 
 define i1 @oeq_isinf_or_ord(half %x) {
 ; CHECK-LABEL: @oeq_isinf_or_ord(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[UNO:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPINF]], [[UNO]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT:    ret i1 [[CMPINF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %uno = fcmp ord half %x, 0xH0000
   %class = or i1 %cmpinf, %uno
   ret i1 %class
 }
 
 define i1 @oeq_isinf_and_uno(half %x) {
 ; CHECK-LABEL: @oeq_isinf_and_uno(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMPINF]], [[UNO]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    ret i1 false
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %uno = fcmp uno half %x, 0xH0000
   %and = and i1 %cmpinf, %uno
   ret i1 %and
 }
 
 define i1 @oeq_isinf_and_ord(half %x) {
 ; CHECK-LABEL: @oeq_isinf_and_ord(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[UNO:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMPINF]], [[UNO]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[CMPINF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
+; CHECK-NEXT:    ret i1 [[CMPINF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %uno = fcmp ord half %x, 0xH0000
   %and = and i1 %cmpinf, %uno
   ret i1 %and
 }
 

   %is.une = fcmp une half %x, 0xH0000
   %or = or i1 %is.une, %is.normal.inf
   ret i1 %or
 }
 
 ; -> normal | inf
 define i1 @isnormalinf_or_inf(half %x) #0 {
 ; CHECK-LABEL: @isnormalinf_or_inf(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[FABS]], 0xH0400
-; CHECK-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[IS_NORMAL_INF]], [[IS_INF]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[IS_INF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 780)
+; CHECK-NEXT:    ret i1 [[IS_INF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %is.normal.inf = fcmp oge half %fabs, 0xH0400
   %is.inf = fcmp oeq half %fabs, 0xH7C00
   %or = or i1 %is.normal.inf, %is.inf
   ret i1 %or
 }
 
 ; -> pinf | pnormal
 define i1 @posisnormalinf_or_posinf(half %x) #0 {
 ; CHECK-LABEL: @posisnormalinf_or_posinf(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[IS_POS_NORMAL_INF:%.*]] = fcmp oge half [[X]], 0xH0400
-; CHECK-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[IS_POS_NORMAL_INF]], [[IS_INF]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[IS_INF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 772)
+; CHECK-NEXT:    ret i1 [[IS_INF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %is.pos.normal.inf = fcmp oge half %x, 0xH0400
   %is.inf = fcmp oeq half %fabs, 0xH7C00
   %or = or i1 %is.pos.normal.inf, %is.inf
   ret i1 %or
 }
 

   %is.pos.inf = fcmp oeq half %x, 0xH7C00
   %or = or i1 %is.normal.inf, %is.pos.inf
   ret i1 %or
 }
 
 ; -> pinf|ninf
 define i1 @isnormalinf_and_inf(half %x) #0 {
 ; CHECK-LABEL: @isnormalinf_and_inf(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[FABS]], 0xH0400
-; CHECK-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[IS_NORMAL_INF]], [[IS_INF]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[IS_INF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
+; CHECK-NEXT:    ret i1 [[IS_INF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %is.normal.inf = fcmp oge half %fabs, 0xH0400
   %is.inf = fcmp oeq half %fabs, 0xH7C00
   %and = and i1 %is.normal.inf, %is.inf
   ret i1 %and
 }
 
 ; -> pinf
 define i1 @posisnormalinf_and_posinf(half %x) #0 {
 ; CHECK-LABEL: @posisnormalinf_and_posinf(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[IS_POS_NORMAL_INF:%.*]] = fcmp oge half [[X]], 0xH0400
-; CHECK-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[IS_POS_NORMAL_INF]], [[IS_INF]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[IS_INF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 512)
+; CHECK-NEXT:    ret i1 [[IS_INF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %is.pos.normal.inf = fcmp oge half %x, 0xH0400
   %is.inf = fcmp oeq half %fabs, 0xH7C00
   %and = and i1 %is.pos.normal.inf, %is.inf
   ret i1 %and
 }
 

   %is.uno = fcmp uno half %x, 0.0
   %or = or i1 %not.is.normal.inf, %is.uno
   ret i1 %or
 }
 
 ; -> ~pnormal
 define i1 @not_negisnormalinf_or_inf(half %x) #0 {
 ; CHECK-LABEL: @not_negisnormalinf_or_inf(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[NOT_IS_NEG_NORMAL_INF:%.*]] = fcmp ult half [[X]], 0xH0400
-; CHECK-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[NOT_IS_NEG_NORMAL_INF]], [[IS_INF]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[IS_INF:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
+; CHECK-NEXT:    ret i1 [[IS_INF]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %not.is.neg.normal.inf = fcmp ult half %x, 0xH0400
   %is.inf = fcmp oeq half %fabs, 0xH7C00
   %or = or i1 %not.is.neg.normal.inf, %is.inf
   ret i1 %or
 }