This new register class can contain all valid vector VTs but only
single vector register will be allocated to it.
This is a potential approach to model instructions that ignore LMUL
and vector register groups like vmv.s.x/vfmv.s.f and reductions
instructions. See D139656.
The key point is how we handle reg-to-reg copies between this new
register class and other register classes. As what the diffs have
shown, there are a lot of redundant vmv1r.v instuctions which can
I post this patch here to discuss if this approach is feasible.