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[LegalizeVectorOps][X86][RISCV] Expand vector S/USHLSAT instead of unrolling.
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Authored by craig.topper on Oct 21 2022, 11:28 AM.

Details

Summary

Not entirely sure if this is generaly good given X86's poor variable
shuffle support in earlier SSE versions.

These are very undertested intrinsics. I can improve that, but wanted
to get feedback if this generally made sense or if we needed a way
to limit to cases that have good variable shift support.

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Event Timeline

craig.topper created this revision.Oct 21 2022, 11:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 21 2022, 11:28 AM
craig.topper requested review of this revision.Oct 21 2022, 11:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 21 2022, 11:28 AM
craig.topper retitled this revision from [LegalizeDAG][X86] Expand vector S/USHLSAT instead of unrolling. to [LegalizeVectorOps][X86][WIP] Expand vector S/USHLSAT instead of unrolling..Oct 21 2022, 11:29 AM

I was wondering if we could use saturated add/sub (or unpack/ext + left-shift + pack?) ops somehow to better detect overflow (as x86 has really poor right shifts), but I can't think of anything :(

Please can you rebase after rGb483349c5f4f61a67cfd9add21dbee2d69833b77 so we have better coverage than just v4i32?

LGTM - the patch is still labeled WIP - are you intending to add test coverage on other targets?

Rebase on fixed vector tests for RISC-V.
Add scalable vector tests that crash without this patch.

craig.topper retitled this revision from [LegalizeVectorOps][X86][WIP] Expand vector S/USHLSAT instead of unrolling. to [LegalizeVectorOps][X86][RISCV] Expand vector S/USHLSAT instead of unrolling..Oct 26 2022, 2:22 PM
RKSimon accepted this revision.Oct 27 2022, 1:56 AM

LGTM - cheers

This revision is now accepted and ready to land.Oct 27 2022, 1:56 AM