[libunwind][RISCV] Support reading of VLENB CSR register

[kachkov98]

Summary

Support read of VLENB (vector byte length) control register (CSR number: 0xC22, DWARF register number: 0x1C22 according to RISC-V DWARF specification: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc). This support is needed for correct unwinding of RVV objects on stack.

Required for fix of https://github.com/llvm/llvm-project/issues/58356

[kito-cheng]

LGTM, just one nit :)

libunwind/src/Registers.hpp

4105

nit: __asm__("csrr %0, 0xC22" : "=r"(vlenb));

[kachkov98]

Review changes

[kito-cheng]

Still LGTM, I guess we need some libunwind guy to approve that?

[MaskRay]

Can you write a test? Run tests with ninja check-unwind

Changing _LIBUNWIND_HIGHEST_DWARF_REGISTER to such a large integer makes
RegisterLocation savedRegisters[kMaxRegisterNumber + 1]; consume a lot of stack space and harms performance.

libunwind/include/libunwind.h

1026

[MaskRay]

Please mention in the summary the official document defining UNW_RISCV_VLENB. Why is it so large?

[kachkov98]

Add test and review fixes

[kachkov98]

In D136264#3881329, @MaskRay wrote:

Please mention in the summary the official document defining UNW_RISCV_VLENB. Why is it so large?

Link to the documentation: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc - it's already placed before RISC-V registers enum, I've also added it to the commit message and copied DWARF numbers from the table to the enum comment

[kachkov98]

In D136264#3881323, @MaskRay wrote:

Can you write a test? Run tests with ninja check-unwind

Changing _LIBUNWIND_HIGHEST_DWARF_REGISTER to such a large integer makes
RegisterLocation savedRegisters[kMaxRegisterNumber + 1]; consume a lot of stack space and harms performance.

Thank you, I didn't noticed that. Fortunately, this register is read-only and we don't need to save it, so in this particular case it looks ok to not change MaxRegisterNumber at all. Looks like NEC's Vector Engine target in libunwind already does the same thing for the UNW_VE_VIXR, UNW_VE_VL registers.

[kachkov98]

Ping

[kachkov98]

Ping

[MaskRay]

Support read of VLENB (vector byte length) control register (CSR number: 0xC22, DWARF register number: 0x1C22 according to RISC-V DWARF specification: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc). This support is needed for correct unwinding of RVV objects on stack.

I don't find 0x1C22 on https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc

No, please don't share false information.

[craig.topper]

In D136264#3939348, @MaskRay wrote:

Support read of VLENB (vector byte length) control register (CSR number: 0xC22, DWARF register number: 0x1C22 according to RISC-V DWARF specification: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc). This support is needed for correct unwinding of RVV objects on stack.

I don't find 0x1C22 on https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc

No, please don't share false information.

The DWARF spec generically says CSRs are assigned their CSR address plus 4096.

[MaskRay]

In D136264#3939352, @craig.topper wrote:

In D136264#3939348, @MaskRay wrote:

Support read of VLENB (vector byte length) control register (CSR number: 0xC22, DWARF register number: 0x1C22 according to RISC-V DWARF specification: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc). This support is needed for correct unwinding of RVV objects on stack.

I don't find 0x1C22 on https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc

No, please don't share false information.

The DWARF spec generically says CSRs are assigned their CSR address plus 4096.

This information helps but is still unsatisfactory.

The RISC-V specification defines a total of 4096 CSRs (see <<riscv-priv>>).
Each CSR is assigned a DWARF register number corresponding to its specified CSR
number plus 4096.

[bibliography]
== References

* [[[riscv-priv]]] "The RISC-V Instruction Set Manual, Volume II: Privileged
Architecture, Document", Editors Andrew Waterman, Krste Asanovi´c, and
John Hauser, RISC-V International.

I don't think [[riscv-priv] assigns 0xc22 to VLENB. Referencing v-spec.adoc in riscv-elf-psabi-doc will probably help.

[kachkov98]

Added link to v-spec with VLENB definition

[kachkov98]

Ping

[MaskRay]

libunwind/test/unwind_scalable_vectors.pass.cpp

16 ↗

(On Diff #476823)

static

16 ↗

(On Diff #476823)

Add a comment what this function does.

[kachkov98]

Addressing review comments

[kachkov98]

Fix diff

[MaskRay]

libunwind/test/unwind_scalable_vectors.pass.cpp

32 ↗

(On Diff #480090)

This is: DW_OP_breg 0 DW_OP_bregx 0x3822 0 DW_OP_plus.

Why is 0x3822 used?

[MaskRay]

Looks great!

libunwind/test/unwind_scalable_vectors.pass.cpp

32 ↗

(On Diff #480090)

Ah, sorry, it's DW_OP_breg2 0 DW_OP_bregx 0x1C22 0 DW_OP_plus. This is correct.

[MaskRay]

libunwind/test/unwind_scalable_vectors.pass.cpp

26 ↗

(On Diff #480090)

Since we use // REQUIRES: linux && target={{riscv64-.+}}, the #if is unneeded.

[whitequark]

I think this revision introduces a bug: namely, without Zicsr enabled, the code would not compile.

The code in getRegister should be wrapped in #if defined(__riscv_v) and if it's not enabled then 0 would be returned.

libunwind/include/__libunwind_config.h

 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64     116
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64     95
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM       287
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K      32
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS      65
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC     31
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64   31
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON   34
-#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV     64
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV     8191
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE        143
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_S390X     83
 
 #if defined(_LIBUNWIND_IS_NATIVE_ONLY)
 # if defined(__linux__)
 #  define _LIBUNWIND_TARGET_LINUX 1
 # endif
 # if defined(__i386__)

libunwind/include/libunwind.h

enum {
   UNW_RISCV_F24 = 56,
   UNW_RISCV_F25 = 57,
   UNW_RISCV_F26 = 58,
   UNW_RISCV_F27 = 59,
   UNW_RISCV_F28 = 60,
   UNW_RISCV_F29 = 61,
   UNW_RISCV_F30 = 62,
   UNW_RISCV_F31 = 63,
+  UNW_RISCV_VLENB = 0x1C22
 };
 
 // VE register numbers
 enum {
   UNW_VE_S0   = 0,
   UNW_VE_S1   = 1,
   UNW_VE_S2   = 2,
   UNW_VE_S3   = 3,

libunwind/src/Registers.hpp

 
 inline bool Registers_riscv::validRegister(int regNum) const {
   if (regNum == UNW_REG_IP)
     return true;
   if (regNum == UNW_REG_SP)
     return true;
   if (regNum < 0)
     return false;
+  if (regNum == UNW_RISCV_VLENB)
+    return true;
   if (regNum > UNW_RISCV_F31)
     return false;
   return true;
 }
 
 inline reg_t Registers_riscv::getRegister(int regNum) const {
   if (regNum == UNW_REG_IP)
     return _registers[0];
   if (regNum == UNW_REG_SP)
     return _registers[2];
   if (regNum == UNW_RISCV_X0)
     return 0;
   if ((regNum > 0) && (regNum < 32))
     return _registers[regNum];
+  if (regNum == UNW_RISCV_VLENB) {
+    reg_t vlenb;
+    __asm__("csrr %0, 0xC22" : "=r"(vlenb));
+    return vlenb;
+  }
   _LIBUNWIND_ABORT("unsupported riscv register");
 }
 
 inline void Registers_riscv::setRegister(int regNum, reg_t value) {
   if (regNum == UNW_REG_IP)
     _registers[0] = value;
   else if (regNum == UNW_REG_SP)
     _registers[2] = value;
inline const char *Registers_riscv::getRegisterName(int regNum) {
   case UNW_RISCV_F28:
     return "ft8";
   case UNW_RISCV_F29:
     return "ft9";
   case UNW_RISCV_F30:
     return "ft10";
   case UNW_RISCV_F31:
     return "ft11";
+  case UNW_RISCV_VLENB:
+    return "vlenb";
   default:
     return "unknown register";
   }
 }
 
 inline bool Registers_riscv::validFloatRegister(int regNum) const {
 # if defined(__riscv_flen)
   if (regNum < UNW_RISCV_F0)