[RISCV] Support CSRs of AIA ext

[sunshaoce]

Summary

Spec: https://github.com/riscv/riscv-aia/

[jrtc27]

Initial comment is your naming seems to be inconsistent with what's already in the file (and you can't even decide on Foo-Level vs Foo-level vs Foo Level); the current naming, taking from the ISA manual, does not use "level" anywhere, it's just "Machine Trap Handling" etc. Presumably these CSRs are currently defined in the evolving AIA spec and so aren't properly categorised with uniform names?

[sunshaoce]

In D133018#3761087, @jrtc27 wrote:

Initial comment is your naming seems to be inconsistent with what's already in the file (and you can't even decide on Foo-Level vs Foo-level vs Foo Level); the current naming, taking from the ISA manual, does not use "level" anywhere, it's just "Machine Trap Handling" etc. Presumably these CSRs are currently defined in the evolving AIA spec and so aren't properly categorised with uniform names?

Thanks for your review. I'll update the revision when the spec are ratified.

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 
 //===----------------------------------------------------------------------===//
 // Supervisor Configuration
 //===----------------------------------------------------------------------===//
 
 def : SysReg<"senvcfg", 0x10A>;
 
 //===----------------------------------------------------------------------===//
+// Supervisor-Level High-Half CSRs for Interrupts 32-63 (RV32 only)
+//===----------------------------------------------------------------------===//
+
+let isRV32Only = 1 in {
+def : SysReg<"sieh", 0x114>;
+def : SysReg<"siph", 0x154>;
+} // isRV32Only = 1
+
+//===----------------------------------------------------------------------===//
 // Supervisor Trap Handling
 //===----------------------------------------------------------------------===//
 def : SysReg<"sscratch", 0x140>;
 def : SysReg<"sepc", 0x141>;
 def : SysReg<"scause", 0x142>;
 let DeprecatedName = "sbadaddr" in
 def : SysReg<"stval", 0x143>;
 def : SysReg<"sip", 0x144>;
 
 //===----------------------------------------------------------------------===//
+// Supervisor-level CSRs
+//===----------------------------------------------------------------------===//
+
+def : SysReg<"siselect", 0x150>;
+def : SysReg<"sireg", 0x151>;
+
+//===----------------------------------------------------------------------===//
+// Supervisor-Level Interrupts
+//===----------------------------------------------------------------------===//
+
+def : SysReg<"stopei", 0x15C>;
+def : SysReg<"stopi", 0xDB0>;
+
+//===----------------------------------------------------------------------===//
 // Supervisor Protection and Translation
 //===----------------------------------------------------------------------===//
 let DeprecatedName = "sptbr" in
 def : SysReg<"satp", 0x180>;
 
 //===----------------------------------------------------------------------===//
 // Debug/Trace Registers
 //===----------------------------------------------------------------------===//

 def : SysReg<"hstatus", 0x600>;
 def : SysReg<"hedeleg", 0x602>;
 def : SysReg<"hideleg", 0x603>;
 def : SysReg<"hie", 0x604>;
 def : SysReg<"hcounteren", 0x606>;
 def : SysReg<"hgeie", 0x607>;
 
 //===----------------------------------------------------------------------===//
+// Virtual Interrupts and Interrupt Priorities for VS Level
+//===----------------------------------------------------------------------===//
+
+def : SysReg<"hvien", 0x608>;
+def : SysReg<"hvictl", 0x609>;
+def : SysReg<"hviprio1", 0x646>;
+def : SysReg<"hviprio2", 0x647>;
+
+//===----------------------------------------------------------------------===//
+// Hypervisor and VS-Level High-Half CSRs (RV32 only)
+//===----------------------------------------------------------------------===//
+
+let isRV32Only = 1 in {
+def : SysReg<"hidelegh", 0x613>;
+def : SysReg<"hvienh", 0x618>;
+def : SysReg<"hviph", 0x655>;
+def : SysReg<"hviprio1h", 0x656>;
+def : SysReg<"hviprio2h", 0x657>;
+def : SysReg<"vsieh", 0x214>;
+def : SysReg<"vsiph", 0x254>;
+} // isRV32Only = 1 
+
+//===----------------------------------------------------------------------===//
 // Hypervisor Trap Handling
 //===----------------------------------------------------------------------===//
 
 def : SysReg<"htval", 0x643>;
 def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;

 def : SysReg<"vstval", 0x243>;
 def : SysReg<"vsip", 0x244>;
 def : SysReg<"vstimecmp", 0x24D>;
 let isRV32Only = 1 in
 def : SysReg<"vstimecmph", 0x25D>;
 def : SysReg<"vsatp", 0x280>;
 
 //===----------------------------------------------------------------------===//
+// VS-Level Window to Indirectly Accessed Registers
+//===----------------------------------------------------------------------===//
+
+def : SysReg<"vsiselect", 0x250>;
+def : SysReg<"vsireg", 0x251>;
+
+//===----------------------------------------------------------------------===//
+// VS-Level Interrupts
+//===----------------------------------------------------------------------===//
+
+def : SysReg<"vstopei", 0x25C>;
+def : SysReg<"vstopi", 0xEB0>;
+
+//===----------------------------------------------------------------------===//
 // Machine Information Registers
 //===----------------------------------------------------------------------===//
 
 def : SysReg<"mvendorid", 0xF11>;
 def : SysReg<"marchid", 0xF12>;
 def : SysReg<"mimpid", 0xF13>;
 def : SysReg<"mhartid", 0xF14>;
 def : SysReg<"mconfigptr", 0xF15>;
 
 //===----------------------------------------------------------------------===//
 // Machine Trap Setup
 //===----------------------------------------------------------------------===//
 def : SysReg<"mstatus", 0x300>;
 def : SysReg<"misa", 0x301>;
 def : SysReg<"medeleg", 0x302>;
 def : SysReg<"mideleg", 0x303>;
 def : SysReg<"mie", 0x304>;
 def : SysReg<"mtvec", 0x305>;
 def : SysReg<"mcounteren", 0x306>;
 let isRV32Only = 1 in
 def : SysReg<"mstatush", 0x310>;
 
 //===----------------------------------------------------------------------===//
+// Virtual Interrupts for Supervisor Level
+//===----------------------------------------------------------------------===//
+
+def : SysReg<"mvien", 0x308>;
+def : SysReg<"mvip", 0x309>;
+
+//===----------------------------------------------------------------------===//
+// Machine-Level High-Half CSRs for Interrupts 32-63 (RV32 only)
+//===----------------------------------------------------------------------===//
+
+let isRV32Only = 1 in {
+def : SysReg<"midelegh", 0x313>;
+def : SysReg<"mieh", 0x314>;
+def : SysReg<"mvienh", 0x318>;
+def : SysReg<"mviph", 0x319>;
+def : SysReg<"miph", 0x354>;
+} // isRV32Only = 1
+
+//===----------------------------------------------------------------------===//
 // Machine Trap Handling
 //===----------------------------------------------------------------------===//
 def : SysReg<"mscratch", 0x340>;
 def : SysReg<"mepc", 0x341>;
 def : SysReg<"mcause", 0x342>;
 let DeprecatedName = "mbadaddr" in
 def : SysReg<"mtval", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
 
 //===----------------------------------------------------------------------===//
+// Machine-Level Window to Indirectly Accessed Registers
+//===----------------------------------------------------------------------===//
+
+def : SysReg<"miselect", 0x350>;
+def : SysReg<"mireg", 0x351>;
+
+//===----------------------------------------------------------------------===//
+// Machine-Level Interrupts
+//===----------------------------------------------------------------------===//
+
+def : SysReg<"mtopei", 0x35C>;
+def : SysReg<"mtopi", 0xFB0>;
+
+//===----------------------------------------------------------------------===//
 // Machine Configuration
 //===----------------------------------------------------------------------===//
 
 def : SysReg<"menvcfg", 0x30A>;
 let isRV32Only = 1 in
 def : SysReg<"menvcfgh", 0x31A>;
 def : SysReg<"mseccfg", 0x747>;
 let isRV32Only = 1 in

llvm/test/MC/RISCV/hypervisor-csr-names.s

 # CHECK-INST: csrrs t2, hgeie, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x70,0x60]
 # CHECK-INST-ALIAS: csrr t2, hgeie
 # name
 csrrs t1, hgeie, zero
 # uimm12
 csrrs t2, 0x607, zero
 
+#########################################
+# Virtual Interrupts and Interrupt Priorities for VS Level
+#########################################
+
+# hvien
+# name
+# CHECK-INST: csrrs t1, hvien, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x60]
+# CHECK-INST-ALIAS: csrr t1, hvien
+# uimm12
+# CHECK-INST: csrrs t2, hvien, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x60]
+# CHECK-INST-ALIAS: csrr t2, hvien
+# name
+csrrs t1, hvien, zero
+# uimm12
+csrrs t2, 0x608, zero
+
+# hvictl
+# name
+# CHECK-INST: csrrs t1, hvictl, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x60]
+# CHECK-INST-ALIAS: csrr t1, hvictl
+# uimm12
+# CHECK-INST: csrrs t2, hvictl, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x60]
+# CHECK-INST-ALIAS: csrr t2, hvictl
+# name
+csrrs t1, hvictl, zero
+# uimm12
+csrrs t2, 0x609, zero
+
+# hviprio1
+# name
+# CHECK-INST: csrrs t1, hviprio1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x60,0x64]
+# CHECK-INST-ALIAS: csrr t1, hviprio1
+# uimm12
+# CHECK-INST: csrrs t2, hviprio1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x64]
+# CHECK-INST-ALIAS: csrr t2, hviprio1
+# name
+csrrs t1, hviprio1, zero
+# uimm12
+csrrs t2, 0x646, zero
+
+# hviprio2
+# name
+# CHECK-INST: csrrs t1, hviprio2, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x64]
+# CHECK-INST-ALIAS: csrr t1, hviprio2
+# uimm12
+# CHECK-INST: csrrs t2, hviprio2, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x64]
+# CHECK-INST-ALIAS: csrr t2, hviprio2
+# name
+csrrs t1, hviprio2, zero
+# uimm12
+csrrs t2, 0x647, zero
+
 ##################################
 # Hypervisor Trap Handling
 ##################################
 
 # htval
 # name
 # CHECK-INST: csrrs t1, htval, zero
 # CHECK-ENC: encoding: [0x73,0x23,0x30,0x64]

 # CHECK-INST: csrrs t2, vsatp, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x00,0x28]
 # CHECK-INST-ALIAS: csrr t2, vsatp
 # name
 csrrs t1, vsatp, zero
 # uimm12
 csrrs t2, 0x280, zero
 
+###################################################
+# VS-Level Window to Indirectly Accessed Registers
+###################################################
+
+# vsiselect
+# name
+# CHECK-INST: csrrs t1, vsiselect, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x25]
+# CHECK-INST-ALIAS: csrr t1, vsiselect
+# uimm12
+# CHECK-INST: csrrs t2, vsiselect, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x25]
+# CHECK-INST-ALIAS: csrr t2, vsiselect
+# name
+csrrs t1, vsiselect, zero
+# uimm12
+csrrs t2, 0x250, zero
+
+# vsireg
+# name
+# CHECK-INST: csrrs t1, vsireg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x25]
+# CHECK-INST-ALIAS: csrr t1, vsireg
+# uimm12
+# CHECK-INST: csrrs t2, vsireg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x25]
+# CHECK-INST-ALIAS: csrr t2, vsireg
+# name
+csrrs t1, vsireg, zero
+# uimm12
+csrrs t2, 0x251, zero
+
+#######################
+# VS-Level Interrupts
+#######################
+
+# vstopei
+# name
+# CHECK-INST: csrrs t1, vstopei, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x25]
+# CHECK-INST-ALIAS: csrr t1, vstopei
+# uimm12
+# CHECK-INST: csrrs t2, vstopei, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x25]
+# CHECK-INST-ALIAS: csrr t2, vstopei
+# name
+csrrs t1, vstopei, zero
+# uimm12
+csrrs t2, 0x25C, zero
+
+# vstopi
+# name
+# CHECK-INST: csrrs t1, vstopi, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xeb]
+# CHECK-INST-ALIAS: csrr t1, vstopi
+# uimm12
+# CHECK-INST: csrrs t2, vstopi, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xeb]
+# CHECK-INST-ALIAS: csrr t2, vstopi
+# name
+csrrs t1, vstopi, zero
+# uimm12
+csrrs t2, 0xEB0, zero
+
 #########################################
 # State Enable Extension (Smstateen)
 #########################################
 
 # hstateen0
 # name
 # CHECK-INST: csrrs t1, hstateen0, zero
 # CHECK-ENC: encoding: [0x73,0x23,0xc0,0x60]

llvm/test/MC/RISCV/machine-csr-names.s

 # CHECK-INST: csrrs t2, mtval2, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x34]
 # CHECK-INST-ALIAS: csrr t2, mtval2
 # name
 csrrs t1, mtval2, zero
 # uimm12
 csrrs t2, 0x34B, zero
 
+########################################################
+# Machine-Level Window to Indirectly Accessed Registers
+########################################################
+
+# miselect
+# name
+# CHECK-INST: csrrs t1, miselect, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x35]
+# CHECK-INST-ALIAS: csrr t1, miselect
+# uimm12
+# CHECK-INST: csrrs t2, miselect, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x35]
+# CHECK-INST-ALIAS: csrr t2, miselect
+# name
+csrrs t1, miselect, zero
+# uimm12
+csrrs t2, 0x350, zero
+
+# mireg
+# name
+# CHECK-INST: csrrs t1, mireg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x35]
+# CHECK-INST-ALIAS: csrr t1, mireg
+# uimm12
+# CHECK-INST: csrrs t2, mireg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x35]
+# CHECK-INST-ALIAS: csrr t2, mireg
+# name
+csrrs t1, mireg, zero
+# uimm12
+csrrs t2, 0x351, zero
+
+############################
+# Machine-Level Interrupts
+############################
+
+# mtopei
+# name
+# CHECK-INST: csrrs t1, mtopei, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x35]
+# CHECK-INST-ALIAS: csrr t1, mtopei
+# uimm12
+# CHECK-INST: csrrs t2, mtopei, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x35]
+# CHECK-INST-ALIAS: csrr t2, mtopei
+# name
+csrrs t1, mtopei, zero
+# uimm12
+csrrs t2, 0x35C, zero
+
+# mtopi
+# name
+# CHECK-INST: csrrs t1, mtopi, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xfb]
+# CHECK-INST-ALIAS: csrr t1, mtopi
+# uimm12
+# CHECK-INST: csrrs t2, mtopi, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xfb]
+# CHECK-INST-ALIAS: csrr t2, mtopi
+# name
+csrrs t1, mtopi, zero
+# uimm12
+csrrs t2, 0xFB0, zero
+
+##########################################
+# Virtual Interrupts for Supervisor Level
+##########################################
+
+# mvien
+# name
+# CHECK-INST: csrrs t1, mvien, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x30]
+# CHECK-INST-ALIAS: csrr t1, mvien
+# uimm12
+# CHECK-INST: csrrs t2, mvien, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x30]
+# CHECK-INST-ALIAS: csrr t2, mvien
+# name
+csrrs t1, mvien, zero
+# uimm12
+csrrs t2, 0x308, zero
+
+# mvip
+# name
+# CHECK-INST: csrrs t1, mvip, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x30]
+# CHECK-INST-ALIAS: csrr t1, mvip
+# uimm12
+# CHECK-INST: csrrs t2, mvip, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x30]
+# CHECK-INST-ALIAS: csrr t2, mvip
+# name
+csrrs t1, mvip, zero
+# uimm12
+csrrs t2, 0x309, zero
+
 #########################
 # Machine Configuration
 #########################
 
 # menvcfg
 # name
 # CHECK-INST: csrrs t1, menvcfg, zero
 # CHECK-ENC: encoding: [0x73,0x23,0xa0,0x30]

llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s

 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
+#########################################
+# Hypervisor and VS-Level High-Half CSRs
+#########################################
+
+# hidelegh
+# name
+# CHECK-INST: csrrs t1, hidelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x61]
+# CHECK-INST-ALIAS: csrr t1, hidelegh
+# uimm12
+# CHECK-INST: csrrs t2, hidelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x61]
+# CHECK-INST-ALIAS: csrr t2, hidelegh
+# name
+csrrs t1, hidelegh, zero
+# uimm12
+csrrs t2, 0x613, zero
+
+# hvienh
+# name
+# CHECK-INST: csrrs t1, hvienh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x61]
+# CHECK-INST-ALIAS: csrr t1, hvienh
+# uimm12
+# CHECK-INST: csrrs t2, hvienh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x61]
+# CHECK-INST-ALIAS: csrr t2, hvienh
+# name
+csrrs t1, hvienh, zero
+# uimm12
+csrrs t2, 0x618, zero
+
+# hviph
+# name
+# CHECK-INST: csrrs t1, hviph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x50,0x65]
+# CHECK-INST-ALIAS: csrr t1, hviph
+# uimm12
+# CHECK-INST: csrrs t2, hviph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x65]
+# CHECK-INST-ALIAS: csrr t2, hviph
+# name
+csrrs t1, hviph, zero
+# uimm12
+csrrs t2, 0x655, zero
+
+# hviprio1h
+# name
+# CHECK-INST: csrrs t1, hviprio1h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x60,0x65]
+# CHECK-INST-ALIAS: csrr t1, hviprio1h
+# uimm12
+# CHECK-INST: csrrs t2, hviprio1h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x65]
+# CHECK-INST-ALIAS: csrr t2, hviprio1h
+# name
+csrrs t1, hviprio1h, zero
+# uimm12
+csrrs t2, 0x656, zero
+
+# hviprio2h
+# name
+# CHECK-INST: csrrs t1, hviprio2h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x65]
+# CHECK-INST-ALIAS: csrr t1, hviprio2h
+# uimm12
+# CHECK-INST: csrrs t2, hviprio2h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x65]
+# CHECK-INST-ALIAS: csrr t2, hviprio2h
+# name
+csrrs t1, hviprio2h, zero
+# uimm12
+csrrs t2, 0x657, zero
+
+# vsieh
+# name
+# CHECK-INST: csrrs t1, vsieh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x21]
+# CHECK-INST-ALIAS: csrr t1, vsieh
+# uimm12
+# CHECK-INST: csrrs t2, vsieh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x21]
+# CHECK-INST-ALIAS: csrr t2, vsieh
+# name
+csrrs t1, vsieh, zero
+# uimm12
+csrrs t2, 0x214, zero
+
+# vsiph
+# name
+# CHECK-INST: csrrs t1, vsiph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x25]
+# CHECK-INST-ALIAS: csrr t1, vsiph
+# uimm12
+# CHECK-INST: csrrs t2, vsiph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x25]
+# CHECK-INST-ALIAS: csrr t2, vsiph
+# name
+csrrs t1, vsiph, zero
+# uimm12
+csrrs t2, 0x254, zero
+
 ##################################
 # Hypervisor Configuration
 ##################################
 
 # henvcfgh
 # name
 # CHECK-INST: csrrs t1, henvcfgh, zero
 # CHECK-ENC: encoding: [0x73,0x23,0xa0,0x61]

llvm/test/MC/RISCV/rv32-machine-csr-names.s

 # CHECK-INST: csrrs t2, mstatush, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x00,0x31]
 # CHECK-INST-ALIAS: csrr t2, mstatush
 # name
 csrrs t1, mstatush, zero
 # uimm12
 csrrs t2, 0x310, zero
 
+####################################################
+# Machine-Level High-Half CSRs for Interrupts 32-63
+####################################################
+
+# midelegh
+# name
+# CHECK-INST: csrrs t1, midelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x31]
+# CHECK-INST-ALIAS: csrr t1, midelegh
+# uimm12
+# CHECK-INST: csrrs t2, midelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x31]
+# CHECK-INST-ALIAS: csrr t2, midelegh
+# name
+csrrs t1, midelegh, zero
+# uimm12
+csrrs t2, 0x313, zero
+
+# mieh
+# name
+# CHECK-INST: csrrs t1, mieh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x31]
+# CHECK-INST-ALIAS: csrr t1, mieh
+# uimm12
+# CHECK-INST: csrrs t2, mieh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x31]
+# CHECK-INST-ALIAS: csrr t2, mieh
+# name
+csrrs t1, mieh, zero
+# uimm12
+csrrs t2, 0x314, zero
+
+# mvienh
+# name
+# CHECK-INST: csrrs t1, mvienh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x31]
+# CHECK-INST-ALIAS: csrr t1, mvienh
+# uimm12
+# CHECK-INST: csrrs t2, mvienh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x31]
+# CHECK-INST-ALIAS: csrr t2, mvienh
+# name
+csrrs t1, mvienh, zero
+# uimm12
+csrrs t2, 0x318, zero
+
+# mviph
+# name
+# CHECK-INST: csrrs t1, mviph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x31]
+# CHECK-INST-ALIAS: csrr t1, mviph
+# uimm12
+# CHECK-INST: csrrs t2, mviph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x31]
+# CHECK-INST-ALIAS: csrr t2, mviph
+# name
+csrrs t1, mviph, zero
+# uimm12
+csrrs t2, 0x319, zero
+
+# miph
+# name
+# CHECK-INST: csrrs t1, miph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x35]
+# CHECK-INST-ALIAS: csrr t1, miph
+# uimm12
+# CHECK-INST: csrrs t2, miph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x35]
+# CHECK-INST-ALIAS: csrr t2, miph
+# name
+csrrs t1, miph, zero
+# uimm12
+csrrs t2, 0x354, zero
+
 #########################
 # Machine Configuration
 #########################
 
 # menvcfgh
 # name
 # CHECK-INST: csrrs t1, menvcfgh, zero
 # CHECK-ENC: encoding: [0x73,0x23,0xa0,0x31]

llvm/test/MC/RISCV/rv32-supervisor-csr-names.s

 # uimm12
 # CHECK-INST: csrrs t2, stimecmph, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x15]
 # CHECK-INST-ALIAS: csrr t2, stimecmph
 # name
 csrrs t1, stimecmph, zero
 # uimm12
 csrrs t2, 0x15D, zero
+
+#######################################################
+# Supervisor-Level High-Half CSRs for Interrupts 32-63
+#######################################################
+
+# sieh
+# name
+# CHECK-INST: csrrs t1, sieh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x11]
+# CHECK-INST-ALIAS: csrr t1, sieh
+# uimm12
+# CHECK-INST: csrrs t2, sieh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x11]
+# CHECK-INST-ALIAS: csrr t2, sieh
+# name
+csrrs t1, sieh, zero
+# uimm12
+csrrs t2, 0x114, zero
+
+# siph
+# name
+# CHECK-INST: csrrs t1, siph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x15]
+# CHECK-INST-ALIAS: csrr t1, siph
+# uimm12
+# CHECK-INST: csrrs t2, siph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x15]
+# CHECK-INST-ALIAS: csrr t2, siph
+# name
+csrrs t1, siph, zero
+# uimm12
+csrrs t2, 0x154, zero

llvm/test/MC/RISCV/rvi-aliases-valid.s

 rdinstret x26
 # CHECK-S-OBJ-NOALIAS: csrrs s8, cycle, zero
 # CHECK-S-OBJ: rdcycle s8
 rdcycle x24
 # CHECK-S-OBJ-NOALIAS: csrrs s9, time, zero
 # CHECK-S-OBJ: rdtime s9
 rdtime x25
 
-# CHECK-S-OBJ-NOALIAS: csrrs  s0, 336, zero
-# CHECK-S-OBJ: csrr s0, 336
+# CHECK-S-OBJ-NOALIAS: csrrs  s0, siselect, zero
+# CHECK-S-OBJ: csrr s0, siselect
 csrr x8, 0x150
 # CHECK-S-OBJ-NOALIAS: csrrw zero, sscratch, s1
 # CHECK-S-OBJ: csrw sscratch, s1
 csrw 0x140, x9
 # CHECK-S-OBJ-NOALIAS: csrrs zero, 4095, s6
 # CHECK-S-OBJ: csrs 4095, s6
 csrs 0xfff, x22
 # CHECK-S-OBJ-NOALIAS: csrrc zero, 4095, s7
 # CHECK-S-OBJ: csrc 4095, s7
 csrc 0xfff, x23
 
-# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 15
-# CHECK-S-OBJ: csrwi 336, 15
+# CHECK-S-OBJ-NOALIAS: csrrwi zero, siselect, 15
+# CHECK-S-OBJ: csrwi siselect, 15
 csrwi 0x150, 0xf
 # CHECK-S-OBJ-NOALIAS: csrrsi zero, 4095, 16
 # CHECK-S-OBJ: csrsi 4095, 16
 csrsi 0xfff, 0x10
 # CHECK-S-OBJ-NOALIAS: csrrci zero, sscratch, 17
 # CHECK-S-OBJ: csrci sscratch, 17
 csrci 0x140, 0x11
 
-# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 7
-# CHECK-S-OBJ: csrwi 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrwi zero, siselect, 7
+# CHECK-S-OBJ: csrwi siselect, 7
 csrw 0x150, 7
-# CHECK-S-OBJ-NOALIAS: csrrsi zero, 336, 7
-# CHECK-S-OBJ: csrsi 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrsi zero, siselect, 7
+# CHECK-S-OBJ: csrsi siselect, 7
 csrs 0x150, 7
-# CHECK-S-OBJ-NOALIAS: csrrci zero, 336, 7
-# CHECK-S-OBJ: csrci 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrci zero, siselect, 7
+# CHECK-S-OBJ: csrci siselect, 7
 csrc 0x150, 7
 
-# CHECK-S-OBJ-NOALIAS: csrrwi t0, 336, 15
-# CHECK-S-OBJ: csrrwi t0, 336, 15
+# CHECK-S-OBJ-NOALIAS: csrrwi t0, siselect, 15
+# CHECK-S-OBJ: csrrwi t0, siselect, 15
 csrrw t0, 0x150, 0xf
 # CHECK-S-OBJ-NOALIAS: csrrsi t0, 4095, 16
 # CHECK-S-OBJ: csrrsi t0, 4095, 16
 csrrs t0, 0xfff, 0x10
 # CHECK-S-OBJ-NOALIAS: csrrci t0, sscratch, 17
 # CHECK-S-OBJ: csrrci t0, sscratch, 17
 csrrc t0, 0x140, 0x11
 

llvm/test/MC/RISCV/supervisor-csr-names.s

 # uimm12
 # CHECK-INST: csrrs t2, sip, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x40,0x14]
 # CHECK-INST-ALIAS: csrr t2, sip
 csrrs t1, sip, zero
 # uimm12
 csrrs t2, 0x144, zero
 
+########################
+# Supervisor-level CSRs
+########################
+
+# siselect
+# name
+# CHECK-INST: csrrs t1, siselect, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x15]
+# CHECK-INST-ALIAS: csrr t1, siselect
+# uimm12
+# CHECK-INST: csrrs t2, siselect, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x15]
+# CHECK-INST-ALIAS: csrr t2, siselect
+csrrs t1, siselect, zero
+# uimm12
+csrrs t2, 0x150, zero
+
+# sireg
+# name
+# CHECK-INST: csrrs t1, sireg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x15]
+# CHECK-INST-ALIAS: csrr t1, sireg
+# uimm12
+# CHECK-INST: csrrs t2, sireg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x15]
+# CHECK-INST-ALIAS: csrr t2, sireg
+csrrs t1, sireg, zero
+# uimm12
+csrrs t2, 0x151, zero
+
+##############################
+# Supervisor-Level Interrupts
+##############################
+
+# stopei
+# name
+# CHECK-INST: csrrs t1, stopei, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x15]
+# CHECK-INST-ALIAS: csrr t1, stopei
+# uimm12
+# CHECK-INST: csrrs t2, stopei, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x15]
+# CHECK-INST-ALIAS: csrr t2, stopei
+csrrs t1, stopei, zero
+# uimm12
+csrrs t2, 0x15C, zero
+
+# stopi
+# name
+# CHECK-INST: csrrs t1, stopi, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xdb]
+# CHECK-INST-ALIAS: csrr t1, stopi
+# uimm12
+# CHECK-INST: csrrs t2, stopi, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xdb]
+# CHECK-INST-ALIAS: csrr t2, stopi
+csrrs t1, stopi, zero
+# uimm12
+csrrs t2, 0xDB0, zero
 
 #########################################
 # Supervisor Protection and Translation
 #########################################
 
 # satp
 # name
 # CHECK-INST: csrrs t1, satp, zero