[RISCV] Don't outline pcrel-lo operand.

[kito-cheng]

Summary

This issue is found by build llvm-testsuite with -Oz, linker will complain
dangerous relocation: %pcrel_lo missing matching %pcrel_hi and that
turn out cause by we outlined pcrel-lo, but leave pcrel-hi there, that's
not problem in general, but the problem is they put into different section, they
pcrel-hi and pcrel-lo pair (e.g. AUIPC+ADDI) *MUST* put be present in same
section due to the implementation.

Outlined function will put into .text name, but the source functions
will put in .text.<function-name> if function-section is enabled or the
function has comdat attribute.

There are few solutions for this issue:

1. Always disallow instructions with pcrel-lo flags.
2. Only disallow instructions with pcrel-lo flags that when function-section is enabled or this function has comdat attribute.
3. Check the corresponding instruction with pcrel-high also included in the outlining candidate sequence or not, and allow that only when pcrel-high is included in the outlining candidate.

First one is most conservative, that might lose some optimization
opportunities, and second one could save those opportunities, and last
one is hard to implement, and don't have any benefits since pcrel-high
are using different label even accessing same symbol.

Use custom section name might also cause this problem, but that already
filtered by RISCVInstrInfo::isFunctionSafeToOutlineFrom.

[kito-cheng]

NOTE: This issue is appeared since https://reviews.llvm.org/D123265, pcrel-lo will propagated into other instructions after that.

[• pcwang-thead]

I met similar problem before when doing random testing via csmith, but I didn't have time to take a deep look. I think it looks great to me and thanks for the fix. :-)

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1417

Nit: This line can be merged with line 1324, I think.

[kito-cheng]

Address @pcwang-thead's comment

[luismarques]

LGTM. Thanks Kito, I didn't realize that D123265 would have this interaction.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1422

Nit: "seperated" -> "separate". Also, "pcrel-high"-> "pcrel_hi", "pcrel-lo" -> "pcrel_lo".

[luismarques]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1422

I guess the "-" (vs "_") is fine, so it's just the "high" -> "hi".

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 
 outliner::InstrType
 RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI,
                                  unsigned Flags) const {
   MachineInstr &MI = *MBBI;
   MachineBasicBlock *MBB = MI.getParent();
   const TargetRegisterInfo *TRI =
       MBB->getParent()->getSubtarget().getRegisterInfo();
+  const auto &F = MI.getMF()->getFunction();
 
   // Positions generally can't safely be outlined.
   if (MI.isPosition()) {
     // We can manually strip out CFI instructions later.
     if (MI.isCFIInstruction())
       // If current function has exception handling code, we can't outline &
       // strip these CFI instructions since it may break .eh_frame section
       // needed in unwinding.
-      return MI.getMF()->getFunction().needsUnwindTableEntry()
-                 ? outliner::InstrType::Illegal
+      return F.needsUnwindTableEntry() ? outliner::InstrType::Illegal
                                        : outliner::InstrType::Invisible;
 
     return outliner::InstrType::Illegal;
   }
 
   // Don't trust the user to write safe inline assembly.
   if (MI.isInlineAsm())
     return outliner::InstrType::Illegal;
 
   // We can't outline branches to other basic blocks.
   if (MI.isTerminator() && !MBB->succ_empty())
     return outliner::InstrType::Illegal;
 
   // We need support for tail calls to outlined functions before return
   // statements can be allowed.
   if (MI.isReturn())
     return outliner::InstrType::Illegal;
 
   // Don't allow modifying the X5 register which we use for return addresses for
   // these outlined functions.
   if (MI.modifiesRegister(RISCV::X5, TRI) ||
       MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
     return outliner::InstrType::Illegal;
 
+  const auto &TM =
+      static_cast<const RISCVTargetMachine &>(MI.getMF()->getTarget());
   // Make sure the operands don't reference something unsafe.
-  for (const auto &MO : MI.operands())
+  for (const auto &MO : MI.operands()) {
     if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI() || MO.isJTI())
       return outliner::InstrType::Illegal;
 
+    // pcrel-hi and pcrel-lo can't put in separate sections, filter that out
+    // if any possible.
+    if (MO.getTargetFlags() == RISCVII::MO_PCREL_LO &&
+        (TM.getFunctionSections() || F.hasComdat() || F.hasSection()))
+      return outliner::InstrType::Illegal;
+  }
+
   // Don't allow instructions which won't be materialized to impact outlining
   // analysis.
   if (MI.isMetaInstruction())
     return outliner::InstrType::Invisible;
 
   return outliner::InstrType::Legal;
 }
 

llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir

body:             |
   ; CHECK-NEXT:   PseudoBR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3:
   ; CHECK-NEXT:   PseudoRET
   ; CHECK-FS-LABEL: name: foo
   ; CHECK-FS: bb.0:
   ; CHECK-FS-NEXT:   liveins: $x10, $x11, $x13
   ; CHECK-FS-NEXT: {{  $}}
-  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
+  ; CHECK-FS-NEXT:   $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
   ; CHECK-FS-NEXT:   PseudoBR %bb.3
   ; CHECK-FS-NEXT: {{  $}}
   ; CHECK-FS-NEXT: bb.1:
   ; CHECK-FS-NEXT:   liveins: $x10, $x11, $x13
   ; CHECK-FS-NEXT: {{  $}}
-  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
+  ; CHECK-FS-NEXT:   $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
   ; CHECK-FS-NEXT:   PseudoBR %bb.3
   ; CHECK-FS-NEXT: {{  $}}
   ; CHECK-FS-NEXT: bb.2:
   ; CHECK-FS-NEXT:   liveins: $x10, $x11, $x13
   ; CHECK-FS-NEXT: {{  $}}
-  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
+  ; CHECK-FS-NEXT:   $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
   ; CHECK-FS-NEXT:   PseudoBR %bb.3
   ; CHECK-FS-NEXT: {{  $}}
   ; CHECK-FS-NEXT: bb.3:
   ; CHECK-FS-NEXT:   PseudoRET
   bb.0:
     liveins: $x10, $x11, $x13
 
     $x11 = ORI $x11, 1023

 ---
 name:            foo2
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: foo2
   ; CHECK: bb.0:
   ; CHECK-NEXT:   liveins: $x10, $x11, $x13
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+  ; CHECK-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
+  ; CHECK-NEXT:   $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
   ; CHECK-NEXT:   PseudoBR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   liveins: $x10, $x11, $x13
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+  ; CHECK-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
+  ; CHECK-NEXT:   $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
   ; CHECK-NEXT:   PseudoBR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   liveins: $x10, $x11, $x13
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+  ; CHECK-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
+  ; CHECK-NEXT:   $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
   ; CHECK-NEXT:   PseudoBR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3:
   ; CHECK-NEXT:   PseudoRET
   ; CHECK-FS-LABEL: name: foo2
   ; CHECK-FS: bb.0:
   ; CHECK-FS-NEXT:   liveins: $x10, $x11, $x13
   ; CHECK-FS-NEXT: {{  $}}
-  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
+  ; CHECK-FS-NEXT:   $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
   ; CHECK-FS-NEXT:   PseudoBR %bb.3
   ; CHECK-FS-NEXT: {{  $}}
   ; CHECK-FS-NEXT: bb.1:
   ; CHECK-FS-NEXT:   liveins: $x10, $x11, $x13
   ; CHECK-FS-NEXT: {{  $}}
-  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
+  ; CHECK-FS-NEXT:   $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
   ; CHECK-FS-NEXT:   PseudoBR %bb.3
   ; CHECK-FS-NEXT: {{  $}}
   ; CHECK-FS-NEXT: bb.2:
   ; CHECK-FS-NEXT:   liveins: $x10, $x11, $x13
   ; CHECK-FS-NEXT: {{  $}}
-  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+  ; CHECK-FS-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
+  ; CHECK-FS-NEXT:   $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
   ; CHECK-FS-NEXT:   PseudoBR %bb.3
   ; CHECK-FS-NEXT: {{  $}}
   ; CHECK-FS-NEXT: bb.3:
   ; CHECK-FS-NEXT:   PseudoRET
   bb.0:
     liveins: $x10, $x11, $x13
 
     $x11 = ORI $x11, 1023