This is an archive of the discontinued LLVM Phabricator instance.

Differential D132527

[RISCV] Precommit test for machine outliner issue for instruction with pcrel-lo.
ClosedPublic

Authored by kito-cheng on Aug 23 2022, 9:09 PM.

Details

Reviewers
None
Commits
rGf054cbfe9194: [RISCV] Precommit test for machine outliner issue for instruction with pcrel-lo.

Diff Detail

Event Timeline

kito-cheng created this revision.Aug 23 2022, 9:09 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2022, 9:09 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 27 others. · View Herald Transcript
kito-cheng requested review of this revision.Aug 23 2022, 9:09 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2022, 9:09 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
kito-cheng added a child revision: D132528: [RISCV] Don't outline pcrel-lo operand..Aug 23 2022, 9:14 PM
Harbormaster completed remote builds in B183012: Diff 455065.Aug 23 2022, 10:47 PM
This revision was not accepted when it landed; it landed in state Needs Review.Aug 24 2022, 6:16 AM
Closed by commit rGf054cbfe9194: [RISCV] Precommit test for machine outliner issue for instruction with pcrel-lo. (authored by kito-cheng). · Explain Why
This revision was automatically updated to reflect the committed changes.
kito-cheng added a commit: rGf054cbfe9194: [RISCV] Precommit test for machine outliner issue for instruction with pcrel-lo..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
282 lines

Diff 455179

llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck %s
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck %s
# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=CHECK-FS %s
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=CHECK-FS %s
--- |
; Cannot outline instructions with pcrel-lo operands if function section
; enabled.
@bar = dso_local local_unnamed_addr global i32 0, align 4
define i32 @foo(i32 %a, i32 %b) { ret i32 0 }
$foo2 = comdat any
define i32 @foo2(i32 %a, i32 %b) comdat { ret i32 0 }
define i32 @foo3(i32 %a, i32 %b) section ".abc" { ret i32 0 }
...
---
name: foo
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: foo
; CHECK: bb.0:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: PseudoRET
; CHECK-FS-LABEL: name: foo
; CHECK-FS: bb.0:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-FS-NEXT: PseudoBR %bb.3
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: bb.1:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-FS-NEXT: PseudoBR %bb.3
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: bb.2:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-FS-NEXT: PseudoBR %bb.3
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: bb.3:
; CHECK-FS-NEXT: PseudoRET
bb.0:
liveins: $x10, $x11, $x13
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
PseudoBR %bb.3
bb.1:
liveins: $x10, $x11, $x13
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
PseudoBR %bb.3
bb.2:
liveins: $x10, $x11, $x13
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
PseudoBR %bb.3
bb.3:
PseudoRET
...
---
name: foo2
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: foo2
; CHECK: bb.0:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: PseudoRET
; CHECK-FS-LABEL: name: foo2
; CHECK-FS: bb.0:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-FS-NEXT: PseudoBR %bb.3
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: bb.1:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-FS-NEXT: PseudoBR %bb.3
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: bb.2:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-FS-NEXT: PseudoBR %bb.3
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: bb.3:
; CHECK-FS-NEXT: PseudoRET
bb.0:
liveins: $x10, $x11, $x13
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
PseudoBR %bb.3
bb.1:
liveins: $x10, $x11, $x13
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
PseudoBR %bb.3
bb.2:
liveins: $x10, $x11, $x13
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
PseudoBR %bb.3
bb.3:
PseudoRET
...
---
name: foo3
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: foo3
; CHECK: bb.0:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x11 = ORI $x11, 1023
; CHECK-NEXT: $x12 = ADDI $x10, 17
; CHECK-NEXT: $x11 = AND $x12, $x11
; CHECK-NEXT: $x10 = SUB $x10, $x11
; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x11 = ORI $x11, 1023
; CHECK-NEXT: $x12 = ADDI $x10, 17
; CHECK-NEXT: $x11 = AND $x12, $x11
; CHECK-NEXT: $x10 = SUB $x10, $x11
; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x11 = ORI $x11, 1023
; CHECK-NEXT: $x12 = ADDI $x10, 17
; CHECK-NEXT: $x11 = AND $x12, $x11
; CHECK-NEXT: $x10 = SUB $x10, $x11
; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: PseudoRET
; CHECK-FS-LABEL: name: foo3
; CHECK-FS: bb.0:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: $x11 = ORI $x11, 1023
; CHECK-FS-NEXT: $x12 = ADDI $x10, 17
; CHECK-FS-NEXT: $x11 = AND $x12, $x11
; CHECK-FS-NEXT: $x10 = SUB $x10, $x11
; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
; CHECK-FS-NEXT: PseudoBR %bb.3
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: bb.1:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: $x11 = ORI $x11, 1023
; CHECK-FS-NEXT: $x12 = ADDI $x10, 17
; CHECK-FS-NEXT: $x11 = AND $x12, $x11
; CHECK-FS-NEXT: $x10 = SUB $x10, $x11
; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
; CHECK-FS-NEXT: PseudoBR %bb.3
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: bb.2:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: $x11 = ORI $x11, 1023
; CHECK-FS-NEXT: $x12 = ADDI $x10, 17
; CHECK-FS-NEXT: $x11 = AND $x12, $x11
; CHECK-FS-NEXT: $x10 = SUB $x10, $x11
; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
; CHECK-FS-NEXT: PseudoBR %bb.3
; CHECK-FS-NEXT: {{ $}}
; CHECK-FS-NEXT: bb.3:
; CHECK-FS-NEXT: PseudoRET
bb.0:
liveins: $x10, $x11, $x13
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
PseudoBR %bb.3
bb.1:
liveins: $x10, $x11, $x13
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
PseudoBR %bb.3
bb.2:
liveins: $x10, $x11, $x13
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
PseudoBR %bb.3
bb.3:
PseudoRET
...