[AArch64] Add Missing v8.8a ALLINT PSTATE

[lenary]

Summary

I noticed, on close reading of the Arm ARM, that llvm is missing
assembly support for a recently-added PSTATE: ALLINT from FEAT_NMI.

This patch:

• Adds the missing PSTATE
• Aligns the decoder more closely with the Arm ARM Decoder pseudocode, including allowing 4-bit immediates for all PSTATES except those explicitly noted (ALLINT, and the SVCRs that we handle separately).
• Tries to centralise the information about the immediates accepted by a given named PSTATE, rather than spreading it around the LLVM codebase.
• Updates tests for existing pstates to reflect these changes.
• Adds another missing system register, from GIC v3.3. It is enabled with FEAT_NMI because it's from FEAT_GICv3_NMI which implies FEAT_NMI.

Parts of this patch are by David Candler and Tomas Matheson.

[lenary]

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

3147

This is using the wrong accessor. I will update the patch with the right one after the first set of feedback comes in.

[lenary]

Sorry, more changes are needed, it turns out. I've missed at least one relevant sysreg.

[lenary]

ping

[peter.smith]

A reference I found helpful when looking at this in revision ia of the Arm ARM (https://developer.arm.com/documentation/ddi0487/ia/?lang=en) Instructions for accessing the PSTATE fields

CFINV ; Inverts the value of PSTATE.C
MSR DAIFSet, #Imm4 ; Used to set any or all of DAIF to 1
MSR DAIFClr, #Imm4 ; Used to clear any or all of DAIF to 0
MSR SPSel, #Imm4 ; Used to select the Stack Pointer, between SP_EL0 and SP_ELx
MSR UAO, #Imm4 ; Used to set the value of PSTATE.UAO
MSR PAN, #Imm4 ; Used to set the value of PSTATE.PAN
MSR DIT, #Imm4 ; Used to set the value of PSTATE.DIT
MSR SSBS, #Imm4 ; Used to set the value of PSTATE.SSBS
MSR TCO, #Imm4 ; Used to set the value of PSTATE.TCO
MSR ALLINT, #Imm1 ; Used to set the value of PSTATE.ALLINT

I think the disassembler changes to decode the field as 4-bits looks fine. Changing the assembler to accept 4-bit fields for the fields that are logically on or off, while closer to the architecture, makes it possible to write assembler that isn't going to assemble on the GNU assembler which only accepts 0 or 1. I think that if we change we should at least inform GNU of the change. Personally I don't think that any human will choose to use anything other than 0 or 1 so I don't necessarily think this is going to be a problem in practice.

Hope I've understood that correctly.

[tmatheson]

Couple of suggestions but otherwise LGTM.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

1125

Please write the type name explicitly where auto is not obvious.

llvm/test/MC/AArch64/armv8.1a-pan.s

18

Maybe keep the tests with non-0/1 but valid immediates.

[lenary]

In D131389#3789376, @peter.smith wrote:

A reference I found helpful when looking at this in revision ia of the Arm ARM (https://developer.arm.com/documentation/ddi0487/ia/?lang=en) Instructions for accessing the PSTATE fields

CFINV ; Inverts the value of PSTATE.C
MSR DAIFSet, #Imm4 ; Used to set any or all of DAIF to 1
MSR DAIFClr, #Imm4 ; Used to clear any or all of DAIF to 0
MSR SPSel, #Imm4 ; Used to select the Stack Pointer, between SP_EL0 and SP_ELx
MSR UAO, #Imm4 ; Used to set the value of PSTATE.UAO
MSR PAN, #Imm4 ; Used to set the value of PSTATE.PAN
MSR DIT, #Imm4 ; Used to set the value of PSTATE.DIT
MSR SSBS, #Imm4 ; Used to set the value of PSTATE.SSBS
MSR TCO, #Imm4 ; Used to set the value of PSTATE.TCO
MSR ALLINT, #Imm1 ; Used to set the value of PSTATE.ALLINT

I think the disassembler changes to decode the field as 4-bits looks fine. Changing the assembler to accept 4-bit fields for the fields that are logically on or off, while closer to the architecture, makes it possible to write assembler that isn't going to assemble on the GNU assembler which only accepts 0 or 1. I think that if we change we should at least inform GNU of the change. Personally I don't think that any human will choose to use anything other than 0 or 1 so I don't necessarily think this is going to be a problem in practice.

Hope I've understood that correctly.

I think you have.

I have informed our binutils maintainers, but they're not receptive to updating their implementation. I think we should press ahead anyway.

llvm/test/MC/AArch64/armv8.1a-pan.s

18

these are the "invalid value" tests, but yes, I should have added a check for msr pan, #15. will do when I commit.

[lenary]

Due to changes in v8.9a/v9.4a, this patch has got more complex and we'll be starting over with the changes. The new patch will come some time this week.

llvm/lib/Target/AArch64/AArch64.td

def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
     "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">;
 
 def FeatureHBC : SubtargetFeature<"hbc", "HasHBC",
     "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
 
 def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS",
     "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">;
 
+def FeatureNMI : SubtargetFeature<"nmi", "HasNMI",
+    "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">;
+
 def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
     "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">;
 
 def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
     "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">;
 
 def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
     "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">;
def HasV8_6aOps : SubtargetFeature<
    FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
 
 def HasV8_7aOps : SubtargetFeature<
   "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
   [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
 
 def HasV8_8aOps : SubtargetFeature<
   "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
-  [HasV8_7aOps, FeatureHBC, FeatureMOPS]>;
+  [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>;
 
 def HasV9_0aOps : SubtargetFeature<
   "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
   [HasV8_5aOps, FeatureSVE2]>;
 
 def HasV9_1aOps : SubtargetFeature<
   "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
   [HasV8_6aOps, HasV9_0aOps]>;

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

bool AArch64DAGToDAGISel::tryWriteRegister(SDNode *N) {
   }
 
   // Check if the register was one of those allowed as the pstatefield value in
   // the MSR (immediate) instruction. To accept the values allowed in the
   // pstatefield for the MSR (immediate) instruction, we also require that an
   // immediate value has been provided as an argument, we know that this is
   // the case as it has been ensured by semantic checking.
   auto PMapper = AArch64PState::lookupPStateByName(RegString->getString());
-  if (PMapper) {
+  if (PMapper && PMapper->haveFeatures(Subtarget->getFeatureBits())) {
     assert (isa<ConstantSDNode>(N->getOperand(2))
               && "Expected a constant integer expression.");
     unsigned Reg = PMapper->Encoding;
     uint64_t Immed = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
     unsigned State;
-    if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO || Reg == AArch64PState::SSBS) {
+    if (PMapper->hasZeroOneImm()) {
       assert(Immed < 2 && "Bad imm");
       State = AArch64::MSRpstateImm1;
     } else {
       assert(Immed < 16 && "Bad imm");
       State = AArch64::MSRpstateImm4;
     }
     ReplaceNode(N, CurDAG->getMachineNode(
                        State, DL, MVT::Other,

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : ExactFPImm<"half", "0.5", 0x1>;
 def : ExactFPImm<"one",  "1.0", 0x2>;
 def : ExactFPImm<"two",  "2.0", 0x3>;
 
 //===----------------------------------------------------------------------===//
 // PState instruction options.
 //===----------------------------------------------------------------------===//
 
-class PState<string name, bits<5> encoding> : SearchableTable {
+class PState<string name, bits<3> op1, bits<3> op2> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
   string Name = name;
-  bits<5> Encoding;
-  let Encoding = encoding;
+  bits<6> Encoding;
+  let Encoding{5-3} = op1;
+  let Encoding{2-0} = op2;
   code Requires = [{ {} }];
 }
 
-def : PState<"SPSel",   0b00101>;
-def : PState<"DAIFSet", 0b11110>;
-def : PState<"DAIFClr", 0b11111>;
+def : PState<"SPSel",   0b000, 0b101>;
+def : PState<"DAIFSet", 0b011, 0b110>;
+def : PState<"DAIFClr", 0b011, 0b111>;
 // v8.1a "Privileged Access Never" extension-specific PStates
 let Requires = [{ {AArch64::FeaturePAN} }] in
-def : PState<"PAN",     0b00100>;
+def : PState<"PAN",     0b000, 0b100>;
 
 // v8.2a "User Access Override" extension-specific PStates
 let Requires = [{ {AArch64::FeaturePsUAO} }] in
-def : PState<"UAO",     0b00011>;
+def : PState<"UAO",     0b000, 0b011>;
 // v8.4a timing insensitivity of data processing instructions
 let Requires = [{ {AArch64::FeatureDIT} }] in
-def : PState<"DIT",     0b11010>;
+def : PState<"DIT",     0b011, 0b010>;
 // v8.5a Spectre Mitigation
 let Requires = [{ {AArch64::FeatureSSBS} }] in
-def : PState<"SSBS",    0b11001>;
+def : PState<"SSBS",    0b011, 0b001>;
 // v8.5a Memory Tagging Extension
 let Requires = [{ {AArch64::FeatureMTE} }] in
-def : PState<"TCO",     0b11100>;
+def : PState<"TCO",     0b011, 0b100>;
+// v8.8a Non-Maskable Interrupts
+let Requires = [{ {AArch64::FeatureNMI} }] in
+def : PState<"ALLINT",  0b001, 0b000>;
 
 //===----------------------------------------------------------------------===//
 // SVCR instruction options.
 //===----------------------------------------------------------------------===//
 
 class SVCR<string name, bits<3> encoding> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";

 def : RWSysReg<"TPIDR2_EL0",       0b11, 0b011, 0b1101, 0b0000, 0b101>;
 } // HasSME
 
 // v8.4a MPAM and SME registers
 //                              Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in {
 def : RWSysReg<"MPAMSM_EL1",    0b11, 0b000, 0b1010, 0b0101, 0b011>;
 } // HasMPAM, HasSME
+
+// v8.8a Non-Maskable Interrupts
+let Requires = [{ {AArch64::FeatureNMI} }] in {
+  //                               Op0   Op1    CRn     CRm     Op2
+  def : RWSysReg<"ALLINT",         0b11, 0b000, 0b0100, 0b0011, 0b000>;
+  def : ROSysReg<"ICC_NMIAR1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b101>; // FEAT_GICv3_NMI
+}

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

public:
 
   bool isMSRSystemRegister() const {
     if (!isSysReg()) return false;
     return SysReg.MSRReg != -1U;
   }
 
   bool isSystemPStateFieldWithImm0_1() const {
     if (!isSysReg()) return false;
-    return (SysReg.PStateField == AArch64PState::PAN ||
-            SysReg.PStateField == AArch64PState::DIT ||
-            SysReg.PStateField == AArch64PState::UAO ||
-            SysReg.PStateField == AArch64PState::SSBS);
+    if (SysReg.PStateField == -1U)
+      return false;
+
+    auto PState = AArch64PState::lookupPStateByEncoding(SysReg.PStateField);
+    if (!PState)
+      return false;
+    return PState->hasZeroOneImm();
   }
 
   bool isSystemPStateFieldWithImm0_15() const {
-    if (!isSysReg() || isSystemPStateFieldWithImm0_1()) return false;
-    return SysReg.PStateField != -1U;
+    if (!isSysReg())
+      return false;
+    if (SysReg.PStateField == -1U)
+      return false;
+    return !isSystemPStateFieldWithImm0_1();
   }
 
   bool isSVCR() const {
     if (Kind != k_SVCR)
       return false;
     return SVCR.PStateField != -1U;
   }
 

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

 static DecodeStatus
 DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
                               const MCDisassembler *Decoder) {
   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
   uint64_t crm = fieldFromInstruction(insn, 8, 4);
   uint64_t pstate_field = (op1 << 3) | op2;
 
-  switch (pstate_field) {
-  case 0x01: // XAFlag
-  case 0x02: // AXFlag
+  if (op1 == 0) {
+    switch (op2) {
+    case 0b000: // CFINV
+    case 0b001: // XAFLAG
+    case 0b010: // AXFLAG
       return Fail;
     }
+  }
+
+  auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
+  if (!PState ||
+      !PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
+    return Fail;
 
-  if ((pstate_field == AArch64PState::PAN  ||
-       pstate_field == AArch64PState::UAO  ||
-       pstate_field == AArch64PState::SSBS) && crm > 1)
+  if (PState->hasZeroOneImm() && crm > 1)
     return Fail;
 
   Inst.addOperand(MCOperand::createImm(pstate_field));
   Inst.addOperand(MCOperand::createImm(crm));
 
-  auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
-  if (PState &&
-      PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
-    return Success;
-  return Fail;
 }
 
 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
                                         uint64_t Addr,
                                         const MCDisassembler *Decoder) {
   uint64_t Rt = fieldFromInstruction(insn, 0, 5);
   uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
   bit |= fieldFromInstruction(insn, 19, 5);

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

struct ExactFPImm {
     int Enum;
     const char *Repr;
   };
 #define GET_EXACTFPIMM_DECL
 #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64PState {
-  struct PState : SysAlias{
-    using SysAlias::SysAlias;
-  };
-  #define GET_PSTATE_DECL
-  #include "AArch64GenSystemOperands.inc"
+struct PState;
+#define GET_PSTATE_DECL
+#include "AArch64GenSystemOperands.inc"
+
+struct PState : SysAlias {
+
+  bool hasZeroOneImm() const { return Encoding == AArch64PState::ALLINT; }
 }
 
 namespace AArch64PSBHint {
   struct PSB : SysAlias {
     using SysAlias::SysAlias;
   };
   #define GET_PSB_DECL
   #include "AArch64GenSystemOperands.inc"

llvm/test/MC/AArch64/armv8.1a-pan.s

// CHECK:  msr PAN, #0           // encoding: [0x9f,0x40,0x00,0xd5]
   msr pan, #1
 // CHECK:  msr PAN, #1           // encoding: [0x9f,0x41,0x00,0xd5]
   msr pan, x5
 // CHECK:  msr PAN, x5           // encoding: [0x65,0x42,0x18,0xd5]
   mrs x13, pan
 // CHECK:  mrs x13, PAN          // encoding: [0x6d,0x42,0x38,0xd5]
 
   msr pan, #-1
-  msr pan, #2
+  msr pan, #16
   msr pan, w0
   mrs w0, pan
-// CHECK-ERROR: error: immediate must be an integer in range [0, 1].
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
 // CHECK-ERROR:   msr pan, #-1
 // CHECK-ERROR:            ^
-// CHECK-ERROR: error: immediate must be an integer in range [0, 1].
-// CHECK-ERROR:   msr pan, #2
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
+// CHECK-ERROR:   msr pan, #16
 // CHECK-ERROR:            ^
-// CHECK-ERROR: error: immediate must be an integer in range [0, 1].
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
 // CHECK-ERROR:   msr pan, w0
 // CHECK-ERROR:            ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:   mrs w0, pan
 // CHECK-ERROR:       ^

llvm/test/MC/AArch64/armv8.2a-uao.s

 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s 2> %t | FileCheck %s
 // RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r -o - %s 2> %t | FileCheck %s
 // RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
 
   msr uao, #0
   msr uao, #1
 // CHECK: msr     UAO, #0                 // encoding: [0x7f,0x40,0x00,0xd5]
 // CHECK: msr     UAO, #1                 // encoding: [0x7f,0x41,0x00,0xd5]
 
-  msr uao, #2
-// CHECK-ERROR: error: immediate must be an integer in range [0, 1].
-// CHECK-ERROR:   msr uao, #2
+  msr uao, #16
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
+// CHECK-ERROR:   msr uao, #16
 // CHECK-ERROR:            ^
 
   msr uao, x1
   mrs x2, uao
 // CHECK: msr     UAO, x1                 // encoding: [0x81,0x42,0x18,0xd5]
 // CHECK: mrs     x2, UAO                 // encoding: [0x82,0x42,0x38,0xd5]

llvm/test/MC/AArch64/armv8.4a-dit.s

 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t  | FileCheck %s --check-prefix=CHECK
 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
 
 //------------------------------------------------------------------------------
 // ARMV8.4-A Timing insensitivity of data processing instructions
 //------------------------------------------------------------------------------
 
 msr DIT, #1
 msr DIT, x0
 mrs x0, DIT
 
 //CHECK:      msr DIT, #1                 // encoding: [0x5f,0x41,0x03,0xd5]
 //CHECK-NEXT: msr DIT, x0                 // encoding: [0xa0,0x42,0x1b,0xd5]
 //CHECK-NEXT: mrs x0, DIT                 // encoding: [0xa0,0x42,0x3b,0xd5]
 
-msr DIT, #2
+msr DIT, #16
 msr DIT, #-1
 
-//CHECK-ERROR:      error: immediate must be an integer in range [0, 1].
-//CHECK-ERROR-NEXT: msr DIT, #2
+//CHECK-ERROR:      error: immediate must be an integer in range [0, 15].
+//CHECK-ERROR-NEXT: msr DIT, #16
 //CHECK-ERROR-NEXT:          ^
-//CHECK-ERROR-NEXT: error: immediate must be an integer in range [0, 1].
+//CHECK-ERROR-NEXT: error: immediate must be an integer in range [0, 15].
 //CHECK-ERROR-NEXT: msr DIT, #-1
 //CHECK-ERROR-NEXT:          ^
 
 //CHECK-NO-V84:      error: expected writable system register or pstate
 //CHECK-NO-V84-NEXT: msr DIT, #1
 //CHECK-NO-V84-NEXT:     ^
 //CHECK-NO-V84-NEXT: error: expected writable system register or pstate
 //CHECK-NO-V84-NEXT: msr DIT, x0
 //CHECK-NO-V84-NEXT:     ^
 //CHECK-NO-V84-NEXT: error: expected readable system register
 //CHECK-NO-V84-NEXT: mrs x0, DIT
 //CHECK-NO-V84-NEXT:         ^
 //CHECK-NO-V84-NEXT: error: expected writable system register or pstate
-//CHECK-NO-V84-NEXT: msr DIT, #2
+//CHECK-NO-V84-NEXT: msr DIT, #16
 //CHECK-NO-V84-NEXT:     ^
 //CHECK-NO-V84-NEXT: error: expected writable system register or pstate
 //CHECK-NO-V84-NEXT: msr DIT, #-1
 //CHECK-NO-V84-NEXT:     ^
 

llvm/test/MC/AArch64/armv8.5a-ssbs-error.s

 // RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs  < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs  < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
 
-msr SSBS, #2
+msr SSBS, #16
 
-// CHECK:         error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT:    msr SSBS, #2
+// CHECK:         error: immediate must be an integer in range [0, 15].
+// CHECK-NEXT:    msr SSBS, #16
 // NOSPECID:      error: expected writable system register or pstate
-// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #2
+// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #16

llvm/test/MC/AArch64/armv8.8a-nmi-error.s

+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+nmi   < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.8a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding               < %s 2>&1 | FileCheck %s --check-prefix=NO_NMI
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-nmi   < %s 2>&1 | FileCheck %s --check-prefix=NO_NMI
+
+msr ALLINT, #1
+msr ALLINT, #2
+msr ALLINT, x3
+mrs x2, ALLINT
+mrs x11, icc_nmiar1_el1
+msr icc_nmiar1_el1, x12
+
+// CHECK:         error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT:    msr ALLINT, #2
+// CHECK-NEXT:    ^
+// CHECK-NEXT:         error: expected writable system register or pstate
+// CHECK-NEXT:    msr icc_nmiar1_el1, x12
+// CHECK-NEXT:    ^
+
+// NO_NMI:      error: expected writable system register or pstate
+// NO_NMI-NEXT: msr {{allint|ALLINT}}, #1
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected writable system register or pstate
+// NO_NMI-NEXT: msr {{allint|ALLINT}}, #2
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected writable system register or pstate
+// NO_NMI-NEXT: msr {{allint|ALLINT}}, x3
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected readable system register
+// NO_NMI-NEXT: mrs x2, {{allint|ALLINT}}
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected readable system register
+// NO_NMI-NEXT: mrs x11, {{icc_nmiar1_el1|ICC_NMIAR1_EL1}}
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected writable system register or pstate
+// NO_NMI-NEXT: msr {{icc_nmiar1_el1|ICC_NMIAR1_EL1}}, x12

llvm/test/MC/AArch64/armv8.8a-nmi.s

+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+nmi   < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.8a < %s | FileCheck %s
+
+mrs x2, ALLINT
+msr ALLINT, x3
+msr ALLINT, #1
+mrs x7, ICC_NMIAR1_EL1
+
+// CHECK:       mrs x2, {{allint|ALLINT}} // encoding: [0x02,0x43,0x38,0xd5]
+// CHECK:       msr {{allint|ALLINT}}, x3 // encoding: [0x03,0x43,0x18,0xd5]
+// CHECK:       msr {{allint|ALLINT}}, #1 // encoding: [0x1f,0x41,0x01,0xd5]
+// CHECK:       mrs x7, {{icc_nmiar1_el1|ICC_NMIAR1_EL1}} // encoding: [0xa7,0xc9,0x38,0xd5]

llvm/test/MC/Disassembler/AArch64/armv8.1a-pan.txt

 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
 
 0x9f,0x40,0x00,0xd5
 0x9f,0x41,0x00,0xd5
-0x9f,0x42,0x00,0xd5
+0x9f,0x4f,0x00,0xd5
 0x65,0x42,0x18,0xd5
 0x6d,0x42,0x38,0xd5
 # CHECK:  msr PAN, #0
 # CHECK:  msr PAN, #1
-# CHECK-NOT: msr PAN, #2
+# CHECK:  msr PAN, #15
 # CHECK:  msr PAN, x5
 # CHECK:  mrs x13, PAN

llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt

 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s 2>&1 | FileCheck --check-prefix=NO_V82A %s
 
 [0x7f,0x40,0x00,0xd5]
 [0x7f,0x41,0x00,0xd5]
-[0x7f,0x42,0x00,0xd5]
+[0x7f,0x4f,0x00,0xd5]
 # CHECK: msr UAO, #0
 # CHECK: msr UAO, #1
-# CHECK: msr S0_0_C4_C2_3, xzr
+# CHECK: msr UAO, #15
 # NO_V82A: msr S0_0_C4_C0_3, xzr
 # NO_V82A: msr S0_0_C4_C1_3, xzr
-# NO_V82A: msr S0_0_C4_C2_3, xzr
+# NO_V82A: msr S0_0_C4_C15_3, xzr
 
 [0x81,0x42,0x18,0xd5]
 [0x82,0x42,0x38,0xd5]
 # CHECK: msr UAO, x1
 # CHECK: mrs x2, UAO
 # NO_V82A: msr S3_0_C4_C2_4, x1
 # NO_V82A: mrs x2, S3_0_C4_C2_4

llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt

+# RUN: llvm-mc -triple=aarch64 -mattr=+nmi   -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64               -disassemble %s | FileCheck %s --check-prefix=NO-NMI
+
+
+[0x03,0x43,0x38,0xd5]
+# CHECK:  mrs x3, ALLINT
+# NO-NMI: mrs x3, S3_0_C4_C3_0
+
+[0x06,0x43,0x18,0xd5]
+# CHECK:  msr ALLINT, x6
+# NO-NMI: msr S3_0_C4_C3_0, x6
+
+[0x1f,0x40,0x01,0xd5]
+# CHECK:  msr ALLINT, #0
+# NO-NMI: msr S0_1_C4_C0_0, xzr
+
+[0x1f,0x41,0x01,0xd5]
+# CHECK:  msr ALLINT, #1
+# NO-NMI: msr S0_1_C4_C1_0, xzr
+
+# Regression test for a defect, where the bit-pattern, which should have allowed
+# only ALLSTATE, allowed SPSel (and others).
+[0xbf,0x51,0x00,0xd5]
+# CHECK:  msr S0_0_C5_C1_5, xzr
+# NO-NMI: msr S0_0_C5_C1_5, xzr
+
+[0xa7,0xc9,0x38,0xd5]
+# CHECK:  mrs x7, ICC_NMIAR1_EL1
+# NO-NMI: mrs x7, S3_0_C12_C9_5