[AArch64] Add missing v8.8a Non-maskable Interrupts feature

[pratlucas]

Summary

This adds support for the missing Non-maskable Interrupts (FEAT_NMI)
feature from armv8.8-A, which consists of the ALLINT pstate register.

This is a second iteration of the patch from D131389, building on top of
the D139925 changes that enable better support for msr (immediate)
instructions that take 1-bit immediates.

Contributors:

• David Candler
• Tomas Matheson
• Sam Elliott

llvm/lib/Target/AArch64/AArch64.td

def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
     "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">;
 
 def FeatureHBC : SubtargetFeature<"hbc", "HasHBC",
     "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
 
 def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS",
     "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">;
 
+def FeatureNMI : SubtargetFeature<"nmi", "HasNMI",
+    "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">;
+
 def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
     "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">;
 
 def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
     "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">;
 
 def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
     "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">;
def HasV8_6aOps : SubtargetFeature<
    FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
 
 def HasV8_7aOps : SubtargetFeature<
   "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
   [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
 
 def HasV8_8aOps : SubtargetFeature<
   "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
-  [HasV8_7aOps, FeatureHBC, FeatureMOPS]>;
+  [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>;
 
 def HasV8_9aOps : SubtargetFeature<
   "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
   [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2,
    FeatureCSSC, FeatureRASv2]>;
 
 def HasV9_0aOps : SubtargetFeature<
   "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 let Requires = [{ {AArch64::FeatureDIT} }] in
 def : PStateImm0_15<"DIT",     0b011, 0b010>;
 // v8.5a Spectre Mitigation
 let Requires = [{ {AArch64::FeatureSSBS} }] in
 def : PStateImm0_15<"SSBS",    0b011, 0b001>;
 // v8.5a Memory Tagging Extension
 let Requires = [{ {AArch64::FeatureMTE} }] in
 def : PStateImm0_15<"TCO",     0b011, 0b100>;
+// v8.8a Non-Maskable Interrupts
+let Requires = [{ {AArch64::FeatureNMI} }] in
+def : PStateImm0_1<"ALLINT",   0b001, 0b000, 0b000>;
 // v9.4a Exception-based event profiling
 //                  Name,      Op1,   Op2,   Crm_high
 def : PStateImm0_1<"PM",       0b001, 0b000, 0b001>;
 
 //===----------------------------------------------------------------------===//
 // SVCR instruction options.
 //===----------------------------------------------------------------------===//
 

 } // HasSME
 
 // v8.4a MPAM and SME registers
 //                              Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in {
 def : RWSysReg<"MPAMSM_EL1",    0b11, 0b000, 0b1010, 0b0101, 0b011>;
 } // HasMPAM, HasSME
 
+// v8.8a Non-Maskable Interrupts
+let Requires = [{ {AArch64::FeatureNMI} }] in {
+  //                               Op0   Op1    CRn     CRm     Op2
+  def : RWSysReg<"ALLINT",         0b11, 0b000, 0b0100, 0b0011, 0b000>;
+  def : ROSysReg<"ICC_NMIAR1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b101>; // FEAT_GICv3_NMI
+}
+
 // v8.9a/v9.4a Memory Attribute Index Enhancement (FEAT_AIE)
 //                            Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"AMAIR2_EL1",  0b11, 0b000, 0b1010, 0b0011, 0b001>;
 def : RWSysReg<"AMAIR2_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b001>;
 def : RWSysReg<"AMAIR2_EL2",  0b11, 0b100, 0b1010, 0b0011, 0b001>;
 def : RWSysReg<"AMAIR2_EL3",  0b11, 0b110, 0b1010, 0b0011, 0b001>;
 def : RWSysReg<"MAIR2_EL1",   0b11, 0b000, 0b1010, 0b0010, 0b001>;
 def : RWSysReg<"MAIR2_EL12",  0b11, 0b101, 0b1010, 0b0010, 0b001>;

llvm/test/MC/AArch64/armv8.8a-nmi-error.s

+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+nmi   < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.8a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding               < %s 2>&1 | FileCheck %s --check-prefix=NO_NMI
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-nmi   < %s 2>&1 | FileCheck %s --check-prefix=NO_NMI
+
+msr ALLINT, #1
+msr ALLINT, #2
+msr ALLINT, x3
+mrs x2, ALLINT
+mrs x11, icc_nmiar1_el1
+msr icc_nmiar1_el1, x12
+
+// CHECK:         error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT:    msr ALLINT, #2
+// CHECK-NEXT:    ^
+// CHECK-NEXT:         error: expected writable system register or pstate
+// CHECK-NEXT:    msr icc_nmiar1_el1, x12
+// CHECK-NEXT:    ^
+
+// NO_NMI:      error: expected writable system register or pstate
+// NO_NMI-NEXT: msr {{allint|ALLINT}}, #1
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected writable system register or pstate
+// NO_NMI-NEXT: msr {{allint|ALLINT}}, #2
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected writable system register or pstate
+// NO_NMI-NEXT: msr {{allint|ALLINT}}, x3
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected readable system register
+// NO_NMI-NEXT: mrs x2, {{allint|ALLINT}}
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected readable system register
+// NO_NMI-NEXT: mrs x11, {{icc_nmiar1_el1|ICC_NMIAR1_EL1}}
+// NO_NMI-NEXT: ^
+// NO_NMI-NEXT: error: expected writable system register or pstate
+// NO_NMI-NEXT: msr {{icc_nmiar1_el1|ICC_NMIAR1_EL1}}, x12

llvm/test/MC/AArch64/armv8.8a-nmi.s

+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+nmi   < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.8a < %s | FileCheck %s
+
+mrs x2, ALLINT
+msr ALLINT, x3
+msr ALLINT, #1
+mrs x7, ICC_NMIAR1_EL1
+
+// CHECK:       mrs x2, {{allint|ALLINT}} // encoding: [0x02,0x43,0x38,0xd5]
+// CHECK:       msr {{allint|ALLINT}}, x3 // encoding: [0x03,0x43,0x18,0xd5]
+// CHECK:       msr {{allint|ALLINT}}, #1 // encoding: [0x1f,0x41,0x01,0xd5]
+// CHECK:       mrs x7, {{icc_nmiar1_el1|ICC_NMIAR1_EL1}} // encoding: [0xa7,0xc9,0x38,0xd5]

llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt

+# RUN: llvm-mc -triple=aarch64 -mattr=+nmi   -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64               -disassemble %s | FileCheck %s --check-prefix=NO-NMI
+
+
+[0x03,0x43,0x38,0xd5]
+# CHECK:  mrs x3, ALLINT
+# NO-NMI: mrs x3, S3_0_C4_C3_0
+
+[0x06,0x43,0x18,0xd5]
+# CHECK:  msr ALLINT, x6
+# NO-NMI: msr S3_0_C4_C3_0, x6
+
+[0x1f,0x40,0x01,0xd5]
+# CHECK:  msr ALLINT, #0
+# NO-NMI: msr S0_1_C4_C0_0, xzr
+
+[0x1f,0x41,0x01,0xd5]
+# CHECK:  msr ALLINT, #1
+# NO-NMI: msr S0_1_C4_C1_0, xzr
+
+# Regression test for a defect, where the bit-pattern, which should have allowed
+# only ALLSTATE, allowed SPSel (and others).
+[0xbf,0x51,0x00,0xd5]
+# CHECK:  msr S0_0_C5_C1_5, xzr
+# NO-NMI: msr S0_0_C5_C1_5, xzr
+
+[0xa7,0xc9,0x38,0xd5]
+# CHECK:  mrs x7, ICC_NMIAR1_EL1
+# NO-NMI: mrs x7, S3_0_C12_C9_5