[X86][DAGISel] Don't widen shuffle element with AVX512

[LuoYuanke]

Summary

Currently the X86 shuffle lowering would widen the element type for
shuffle if the mask element value is adjacent. For below example

  %t2 = add nsw <16 x i32> %t0, %t1
  %t3 = sub nsw <16 x i32> %t0, %t1
  %t4 = shufflevector <16 x i32> %t2, <16 x i32> %t3,
                      <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 4,
                       i32 5, i32 6, i32 7, i32 8, i32 9, i32 10,
                       i32 11, i32 12, i32 13, i32 14, i32 15>

  ret <16 x i32> %t4

Compiler would transform the shuffle to
  %t4 = shufflevector <8 x i64> %t2, <8 x i64> %t3,
                      <8 x i64> <i32 8, i32 1, i32 2, i32 3, i32 4,
                                 i32 5, i32 6, i32 7>
This may lose the oppotunity to let ISel select mask instruction when
avx512 is enabled.

This patch is to prevent the tranform when avx512 feature is enabled.

[LuoYuanke]

Rebase.

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

44372

This doesn't look right - shouldn't it be something like:

APInt Mask = APIntOps::ScaleBitMask(ConstCond->getAPIntValue(), NumElts * 2) ?

[LuoYuanke]

llvm/lib/Target/X86/X86ISelLowering.cpp

44372

Thanks, Simon. ScaleBitMask perfectly fit this coputation.

[LuoYuanke]

Address Simon's comments.

[RKSimon]

I think we can probably generalize this very easily to any legal widening, e.g. to handle: https://gcc.godbolt.org/z/Pjz5qfYT7 (v32i16 -> v16i32)

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

44346

Check if N->getOpcode() == ISD::VSELECT

44350

auto *ConstCond = dyn_cast<ConstantSDNode>(Cond.getOperand(0));
if (!ConstCond)
  return SDValue();

[LuoYuanke]

llvm/lib/Target/X86/X86ISelLowering.cpp

44346

Is it possible that CondVT is not vXi1 for ISD::VSELECT? I ask the question becasue the comments for ISD::VSELECT says "targets may change the condition type".

/// At first, the VSELECT condition is of vXi1 type. Later, targets may
/// change the condition type in order to match the VSELECT node using a
/// pattern. The condition follows the BooleanContent format of the target.

[LuoYuanke]

Address Simon's comments.

[LuoYuanke]

In D129537#3659947, @RKSimon wrote:

I think we can probably generalize this very easily to any legal widening, e.g. to handle: https://gcc.godbolt.org/z/Pjz5qfYT7 (v32i16 -> v16i32)

Good suggestion. Let me take a look at it.

[LuoYuanke]

Address Simon's address to generalize the blend/select combine.

[LuoYuanke]

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

129

For this case not sure if it is worse than left side code (previous code).

[RKSimon]

I've added some additional test coverage to shuffle-blend.ll - please can you rebase?

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

129

Add a 128-bit vector limit?

[RKSimon]

Please can you update the patch title/summary?

[LuoYuanke]

Rebase and update test case.

[LuoYuanke]

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

129

I'll add 128-bit vector limit. However in this case it is 128-bit vector.

[LuoYuanke]

Limit the vector bit width >=128 and add test cases.

[RKSimon]

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

4–5

CHECK,AVX512BW,X86-AVX512BW
CHECK,AVX512BW,X64-AVX512BW

[LuoYuanke]

Address Simon's comments.

[LuoYuanke]

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

94

retl can be merged to retq by ret{{[l|q]}}. Not sure why utils/update_llc_test_checks.py doesn't merge.

[RKSimon]

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

151

regression? you might need to improve the 128-bit limit logic to account for vXi16 specifically

[LuoYuanke]

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

151

There is PBLENDW, but there is no PBLENDB instruction, so it is better to widen to v2Xi16 from vXi8. Besides there is more instruction for 16-bit element (e.g., movsh). I'll investigate more on this issue.

[LuoYuanke]

Specially handling for vXi8, because vXi16 can be applied PBLENDW while vXi8 can't.

[RKSimon]

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

94

"kmovd %eax" vs "kmovq %rax"

243

pre-commit these additional tests

[LuoYuanke]

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

94

Got it. :)

243

Sure. I'll do it.

[LuoYuanke]

Rebase

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

19328

This list is going to get longer, and we're likely to miss patterns that only fold to target nodes later on - I'm wondering whether we could consider accepting any TLI.isBinOp() case here?

[RKSimon]

LGTM - with one minor comment for future work

llvm/lib/Target/X86/X86ISelLowering.cpp

19328

Please can you add a TODO about maybe converting this to TLI.isBinOp()?

[LuoYuanke]

Address Simon's comments.

[LuoYuanke]

llvm/test/CodeGen/X86/haddsub-undef.ll

1053 ↗

(On Diff #447318)

This looks a regression, I'll take a look at it.

[LuoYuanke]

llvm/lib/Target/X86/X86ISelLowering.cpp

19328

Thank Simon for the suggestion. It seems there is regression on some cases, I'll take a look at the regression.

[RKSimon]

Yeah - that was what I saw as well - if you want to get this in for 15.x I'd recommend going back to the old switch statement - then investigate the binop general case later (if you solve it soon enough you request a merge)

[LuoYuanke]

Revert to previous version and add TODO for checking TLI.isBinOp().

[LuoYuanke]

In D129537#3676257, @RKSimon wrote:

Yeah - that was what I saw as well - if you want to get this in for 15.x I'd recommend going back to the old switch statement - then investigate the binop general case later (if you solve it soon enough you request a merge)

Thank Simon for the review. All the comments are valuable. Let me land the old switch statement version first and then investigate the general binop.

[fhahn]

This patch unfortunately causes crashes when building llvm-test-suite optimizing for AVX512.

Reproducer for llc:

target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx"

define i32 @test(<32 x i32> %0) #0 {
entry:
  %1 = mul <32 x i32> %0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
  %2 = tail call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %1)
  ret i32 %2
}

; Function Attrs: nocallback nofree nosync nounwind readnone willreturn
declare i32 @llvm.vector.reduce.add.v32i32(<32 x i32>) #1

attributes #0 = { "min-legal-vector-width"="0" "target-cpu"="skylake-avx512" }
attributes #1 = { nocallback nofree nosync nounwind readnone willreturn }

I've reverted the patch in the meantime to get current main back into a good state.

llvm/lib/Target/X86/X86ISelLowering.cpp

if (LowV2Elements == LowV1Elements) {
           return true;
       }
     }
   }
 
   return false;
 }
 
+static bool canCombineAsMaskOperation(SDValue V1, SDValue V2,
+                                      const X86Subtarget &Subtarget) {
+  if (!Subtarget.hasAVX512())
+    return false;
+
+  MVT VT = V1.getSimpleValueType().getScalarType();
+  if ((VT == MVT::i16 || VT == MVT::i8) && !Subtarget.hasBWI())
+    return false;
+
+  // i8 is better to be widen to i16, because there is PBLENDW for vXi16
+  // when the vector bit size is 128 or 256.
+  if (VT == MVT::i8 && V1.getSimpleValueType().getSizeInBits() < 512)
+    return false;
+
+  auto HasMaskOperation = [&](SDValue V) {
+    // TODO: Currently we only check limited opcode. We probably extend
+    // it to all binary operation by checking TLI.isBinOp().
+    switch (V->getOpcode()) {
+    default:
+      return false;
+    case ISD::ADD:
+    case ISD::SUB:
+    case ISD::AND:
+    case ISD::XOR:
+      break;
+    }
+    if (!V->hasOneUse())
+      return false;
+
+    return true;
+  };
+
+  if (HasMaskOperation(V1) || HasMaskOperation(V2))
+    return true;
+
+  return false;
+}
+
 // Forward declaration.
 static SDValue canonicalizeShuffleMaskWithHorizOp(
     MutableArrayRef<SDValue> Ops, MutableArrayRef<int> Mask,
     unsigned RootSizeInBits, const SDLoc &DL, SelectionDAG &DAG,
     const X86Subtarget &Subtarget);
 
     /// Top-level lowering for x86 vector shuffles.
 ///
static SDValue lowerVECTOR_SHUFFLE(SDValue Op, const X86Subtarget &Subtarget,
   bool V2IsZero = !V2IsUndef && ISD::isBuildVectorAllZeros(V2.getNode());
 
   // Try to collapse shuffles into using a vector type with fewer elements but
   // wider element types. We cap this to not form integers or floating point
   // elements wider than 64 bits. It does not seem beneficial to form i128
   // integers to handle flipping the low and high halves of AVX 256-bit vectors.
   SmallVector<int, 16> WidenedMask;
   if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
+      !canCombineAsMaskOperation(V1, V2, Subtarget) &&
       canWidenShuffleElements(OrigMask, Zeroable, V2IsZero, WidenedMask)) {
     // Shuffle mask widening should not interfere with a broadcast opportunity
     // by obfuscating the operands with bitcasts.
     // TODO: Avoid lowering directly from this top-level function: make this
     // a query (canLowerAsBroadcast) and defer lowering to the type-based calls.
     if (SDValue Broadcast = lowerShuffleAsBroadcast(DL, VT, V1, V2, OrigMask,
                                                     Subtarget, DAG))
       return Broadcast;
static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG,
   SDValue Cond = N->getOperand(0);
   if ((N->getOpcode() != ISD::VSELECT &&
        N->getOpcode() != X86ISD::BLENDV) ||
       ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
     return SDValue();
 
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   unsigned BitWidth = Cond.getScalarValueSizeInBits();
   EVT VT = N->getValueType(0);
 
   // We can only handle the cases where VSELECT is directly legal on the
   // subtarget. We custom lower VSELECT nodes with constant conditions and
   // this makes it hard to see whether a dynamic VSELECT will correctly
   // lower, so we both check the operation's status and explicitly handle the
   // cases where a *dynamic* blend will fail even though a constant-condition
   // blend could be custom lowered.
   // FIXME: We should find a better way to handle this class of problems.
   // Potentially, we should combine constant-condition vselect nodes
   // pre-legalization into shuffles and not mark as many types as custom
   // lowered.
   if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
     return SDValue();
   // FIXME: We don't support i16-element blends currently. We could and
   // should support them by making *all* the bits in the condition be set
   // rather than just the high bit and using an i8-element blend.
   if (VT.getVectorElementType() == MVT::i16)
     return SDValue();
   // Dynamic blending was only available from SSE4.1 onward.
   if (VT.is128BitVector() && !Subtarget.hasSSE41())
     return SDValue();
   // Byte blends are only available in AVX2
   if (VT == MVT::v32i8 && !Subtarget.hasAVX2())
     return SDValue();
   // There are no 512-bit blend instructions that use sign bits.
   if (VT.is512BitVector())
     return SDValue();
 
   // Don't optimize before the condition has been transformed to a legal type
   // and don't ever optimize vector selects that map to AVX512 mask-registers.
   if (BitWidth < 8 || BitWidth > 64)
     return SDValue();
 
   auto OnlyUsedAsSelectCond = [](SDValue Cond) {

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512F,X86-AVX512F
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512F,X64-AVX512F
-; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512BW
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512BW
+; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512BW,X86-AVX512BW
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512BW,X64-AVX512BW
 
 define <16 x i32> @shuffle_v8i64(<16 x i32> %t0, <16 x i32> %t1) {
-; AVX512F-LABEL: shuffle_v8i64:
-; AVX512F:       # %bb.0: # %entry
-; AVX512F-NEXT:    vpaddd %zmm1, %zmm0, %zmm2
-; AVX512F-NEXT:    vpsubd %zmm1, %zmm0, %zmm0
-; AVX512F-NEXT:    movb $-86, %al
-; AVX512F-NEXT:    kmovw %eax, %k1
-; AVX512F-NEXT:    vmovdqa64 %zmm0, %zmm2 {%k1}
-; AVX512F-NEXT:    vmovdqa64 %zmm2, %zmm0
-; AVX512F-NEXT:    ret{{[l|q]}}
-;
-; AVX512BW-LABEL: shuffle_v8i64:
-; AVX512BW:       # %bb.0: # %entry
-; AVX512BW-NEXT:    vpaddd %zmm1, %zmm0, %zmm2
-; AVX512BW-NEXT:    vpsubd %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT:    movb $-86, %al
-; AVX512BW-NEXT:    kmovd %eax, %k1
-; AVX512BW-NEXT:    vmovdqa64 %zmm0, %zmm2 {%k1}
-; AVX512BW-NEXT:    vmovdqa64 %zmm2, %zmm0
-; AVX512BW-NEXT:    ret{{[l|q]}}
+; CHECK-LABEL: shuffle_v8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpaddd %zmm1, %zmm0, %zmm2
+; CHECK-NEXT:    vpsubd %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    vshufps {{.*#+}} zmm0 = zmm2[0,1],zmm0[2,3],zmm2[4,5],zmm0[6,7],zmm2[8,9],zmm0[10,11],zmm2[12,13],zmm0[14,15]
+; CHECK-NEXT:    ret{{[l|q]}}
 entry:
   %t2 = add nsw <16 x i32> %t0, %t1
   %t3 = sub nsw <16 x i32> %t0, %t1
   %t4 = shufflevector <16 x i32> %t2, <16 x i32> %t3, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 4, i32 5, i32 22, i32 23, i32 8, i32 9, i32 26, i32 27, i32 12, i32 13, i32 30, i32 31>
   ret <16 x i32> %t4
 }
 
 define <8 x i32> @shuffle_v4i64(<8 x i32> %t0, <8 x i32> %t1) {

 ; X64-AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
 ; X64-AVX512F-NEXT:    vpaddb %ymm2, %ymm3, %ymm2
 ; X64-AVX512F-NEXT:    vpaddb %ymm1, %ymm0, %ymm3
 ; X64-AVX512F-NEXT:    vinserti64x4 $1, %ymm2, %zmm3, %zmm2
 ; X64-AVX512F-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
 ; X64-AVX512F-NEXT:    vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
 ; X64-AVX512F-NEXT:    retq
 ;
-; AVX512BW-LABEL: addb_selectw_64xi8:
-; AVX512BW:       # %bb.0:
-; AVX512BW-NEXT:    vpaddb %zmm1, %zmm0, %zmm2
-; AVX512BW-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT:    movl $1, %eax
-; AVX512BW-NEXT:    kmovd %eax, %k1
-; AVX512BW-NEXT:    vmovdqu16 %zmm0, %zmm2 {%k1}
-; AVX512BW-NEXT:    vmovdqa64 %zmm2, %zmm0
-; AVX512BW-NEXT:    ret{{[l|q]}}
+; X86-AVX512BW-LABEL: addb_selectw_64xi8:
+; X86-AVX512BW:       # %bb.0:
+; X86-AVX512BW-NEXT:    vpaddb %zmm1, %zmm0, %zmm2
+; X86-AVX512BW-NEXT:    movl $3, %eax
+; X86-AVX512BW-NEXT:    kmovd %eax, %k0
+; X86-AVX512BW-NEXT:    kmovd %k0, %k1
+; X86-AVX512BW-NEXT:    vpsubb %zmm1, %zmm0, %zmm2 {%k1}
+; X86-AVX512BW-NEXT:    vmovdqa64 %zmm2, %zmm0
+; X86-AVX512BW-NEXT:    retl
+;
+; X64-AVX512BW-LABEL: addb_selectw_64xi8:
+; X64-AVX512BW:       # %bb.0:
+; X64-AVX512BW-NEXT:    vpaddb %zmm1, %zmm0, %zmm2
+; X64-AVX512BW-NEXT:    movl $3, %eax
+; X64-AVX512BW-NEXT:    kmovq %rax, %k1
+; X64-AVX512BW-NEXT:    vpsubb %zmm1, %zmm0, %zmm2 {%k1}
+; X64-AVX512BW-NEXT:    vmovdqa64 %zmm2, %zmm0
+; X64-AVX512BW-NEXT:    retq
   %t2 = add nsw <64 x i8> %t0, %t1
   %t3 = sub nsw <64 x i8> %t0, %t1
   %t4 = shufflevector <64 x i8> %t2, <64 x i8> %t3, <64 x i32> <i32 64, i32 65, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
   ret <64 x i8> %t4
 }
 
 define <32 x i8> @addb_selectw_32xi8(<32 x i8> %t0, <32 x i8> %t1) {
 ; CHECK-LABEL: addb_selectw_32xi8:
; CHECK-NEXT:    ret{{[l|q]}}
   ret <32 x i8> %t4
 }
 
 define <16 x i8> @addb_selectw_16xi8(<16 x i8> %t0, <16 x i8> %t1) {
 ; CHECK-LABEL: addb_selectw_16xi8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vpaddb %xmm1, %xmm0, %xmm2
 ; CHECK-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3,4,5,6,7]
 ; CHECK-NEXT:    ret{{[l|q]}}
   %t2 = add nsw <16 x i8> %t0, %t1
   %t3 = sub nsw <16 x i8> %t0, %t1
   %t4 = shufflevector <16 x i8> %t2, <16 x i8> %t3, <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %t4
 }
 
 define <8 x i8> @addb_selectw_8xi8(<8 x i8> %t0, <8 x i8> %t1) {
 ; CHECK-LABEL: addb_selectw_8xi8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vpaddb %xmm1, %xmm0, %xmm2
 ; CHECK-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3,4,5,6,7]
 ; CHECK-NEXT:    ret{{[l|q]}}
   %t2 = add nsw <8 x i8> %t0, %t1
   %t3 = sub nsw <8 x i8> %t0, %t1
   %t4 = shufflevector <8 x i8> %t2, <8 x i8> %t3, <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i8> %t4
 }
 
 define <32 x i16> @addw_selectd_32xi16(<32 x i16> %t0, <32 x i16> %t1) {
 ; AVX512F-LABEL: addw_selectd_32xi16:
 ; AVX512F:       # %bb.0:
 ; AVX512F-NEXT:    vextracti64x4 $1, %zmm1, %ymm2
 ; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
 ; AVX512F-NEXT:    vpaddw %ymm2, %ymm3, %ymm2
 ; AVX512F-NEXT:    vpaddw %ymm1, %ymm0, %ymm3
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm2, %zmm3, %zmm2
 ; AVX512F-NEXT:    vpsubw %ymm1, %ymm0, %ymm0
 ; AVX512F-NEXT:    movw $1, %ax
 ; AVX512F-NEXT:    kmovw %eax, %k1
 ; AVX512F-NEXT:    vmovdqa32 %zmm0, %zmm2 {%k1}
 ; AVX512F-NEXT:    vmovdqa64 %zmm2, %zmm0
 ; AVX512F-NEXT:    ret{{[l|q]}}
 ;
 ; AVX512BW-LABEL: addw_selectd_32xi16:
 ; AVX512BW:       # %bb.0:
 ; AVX512BW-NEXT:    vpaddw %zmm1, %zmm0, %zmm2
-; AVX512BW-NEXT:    vpsubw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT:    movw $1, %ax
+; AVX512BW-NEXT:    movl $3, %eax
 ; AVX512BW-NEXT:    kmovd %eax, %k1
-; AVX512BW-NEXT:    vmovdqa32 %zmm0, %zmm2 {%k1}
+; AVX512BW-NEXT:    vpsubw %zmm1, %zmm0, %zmm2 {%k1}
 ; AVX512BW-NEXT:    vmovdqa64 %zmm2, %zmm0
 ; AVX512BW-NEXT:    ret{{[l|q]}}
   %t2 = add nsw <32 x i16> %t0, %t1
   %t3 = sub nsw <32 x i16> %t0, %t1
   %t4 = shufflevector <32 x i16> %t2, <32 x i16> %t3, <32 x i32> <i32 32, i32 33, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <32 x i16> %t4
 }
 
; CHECK-NEXT:    ret{{[l|q]}}
   %t4 = shufflevector <16 x i16> %t2, <16 x i16> %t3, <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i16> %t4
 }
 
 define <16 x i32> @addd_selectq_16xi32(<16 x i32> %t0, <16 x i32> %t1) {
 ; AVX512F-LABEL: addd_selectq_16xi32:
 ; AVX512F:       # %bb.0:
 ; AVX512F-NEXT:    vpaddd %zmm1, %zmm0, %zmm2
-; AVX512F-NEXT:    vpsubd %zmm1, %zmm0, %zmm0
-; AVX512F-NEXT:    movb $1, %al
+; AVX512F-NEXT:    movw $3, %ax
 ; AVX512F-NEXT:    kmovw %eax, %k1
-; AVX512F-NEXT:    vmovdqa64 %zmm0, %zmm2 {%k1}
+; AVX512F-NEXT:    vpsubd %zmm1, %zmm0, %zmm2 {%k1}
 ; AVX512F-NEXT:    vmovdqa64 %zmm2, %zmm0
 ; AVX512F-NEXT:    ret{{[l|q]}}
 ;
 ; AVX512BW-LABEL: addd_selectq_16xi32:
 ; AVX512BW:       # %bb.0:
 ; AVX512BW-NEXT:    vpaddd %zmm1, %zmm0, %zmm2
-; AVX512BW-NEXT:    vpsubd %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT:    movb $1, %al
+; AVX512BW-NEXT:    movw $3, %ax
 ; AVX512BW-NEXT:    kmovd %eax, %k1
-; AVX512BW-NEXT:    vmovdqa64 %zmm0, %zmm2 {%k1}
+; AVX512BW-NEXT:    vpsubd %zmm1, %zmm0, %zmm2 {%k1}
 ; AVX512BW-NEXT:    vmovdqa64 %zmm2, %zmm0
 ; AVX512BW-NEXT:    ret{{[l|q]}}
   %t2 = add nsw <16 x i32> %t0, %t1
   %t3 = sub nsw <16 x i32> %t0, %t1
   %t4 = shufflevector <16 x i32> %t2, <16 x i32> %t3, <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
 
   ret <16 x i32> %t4
 }

 ; CHECK-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]
 ; CHECK-NEXT:    ret{{[l|q]}}
   %t2 = add nsw <4 x i32> %t0, %t1
   %t3 = sub nsw <4 x i32> %t0, %t1
   %t4 = shufflevector <4 x i32> %t2, <4 x i32> %t3, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
 
   ret <4 x i32> %t4
 }

llvm/test/CodeGen/X86/combine-sdiv.ll

 ;
 ; AVX1-LABEL: combine_vec_sdiv_nonuniform7:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpsubw %xmm0, %xmm1, %xmm1
 ; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
 ; AVX1-NEXT:    retq
 ;
-; AVX2ORLATER-LABEL: combine_vec_sdiv_nonuniform7:
-; AVX2ORLATER:       # %bb.0:
-; AVX2ORLATER-NEXT:    vpxor %xmm1, %xmm1, %xmm1
-; AVX2ORLATER-NEXT:    vpsubw %xmm0, %xmm1, %xmm1
-; AVX2ORLATER-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
-; AVX2ORLATER-NEXT:    retq
+; AVX2-LABEL: combine_vec_sdiv_nonuniform7:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpsubw %xmm0, %xmm1, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
+; AVX2-NEXT:    retq
+;
+; AVX512F-LABEL: combine_vec_sdiv_nonuniform7:
+; AVX512F:       # %bb.0:
+; AVX512F-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512F-NEXT:    vpsubw %xmm0, %xmm1, %xmm1
+; AVX512F-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
+; AVX512F-NEXT:    retq
+;
+; AVX512BW-LABEL: combine_vec_sdiv_nonuniform7:
+; AVX512BW:       # %bb.0:
+; AVX512BW-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512BW-NEXT:    vpsubw %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
+; AVX512BW-NEXT:    retq
 ;
 ; XOP-LABEL: combine_vec_sdiv_nonuniform7:
 ; XOP:       # %bb.0:
 ; XOP-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; XOP-NEXT:    vpsubw %xmm0, %xmm1, %xmm1
 ; XOP-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
 ; XOP-NEXT:    retq
   %1 = sdiv <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 1, i16 1, i16 1, i16 1>