[X86][FP16] Fix crash when lowering copysign for f16

[pengfei]

Summary

This is to address the assertion fail reported in https://reviews.llvm.org/D107082#3635612
Not sure if it is a problem of promoting FCOPYSIGN + libcall FP_ROUND.
The promoting will set the rounding mode to 1 https://github.com/llvm/llvm-project/blob/a442c628882eb07fffff8c9f7c87a317af14555a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp#L4810-L4814
While libcall cannot handle the rounding mode equals to 1 https://github.com/llvm/llvm-project/blob/a442c628882eb07fffff8c9f7c87a317af14555a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp#L4324-L4328
So changing the action to Expand to workaround the problem.

[clementval]

Thanks for the quick fix.

[MaskRay]

Seems that the codegen improves a bit with Expand.

[pengfei]

Thanks @clementval and @MaskRay !

llvm/lib/Target/X86/X86ISelLowering.cpp

for (auto VT : { MVT::f32, MVT::f64 }) {
       setOperationAction(ISD::FSIN   , VT, Expand);
       setOperationAction(ISD::FCOS   , VT, Expand);
       setOperationAction(ISD::FSINCOS, VT, Expand);
     }
 
     // Half type will be promoted by default.
     setOperationAction(ISD::FABS, MVT::f16, Promote);
     setOperationAction(ISD::FNEG, MVT::f16, Promote);
-    setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
+    setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
     setOperationAction(ISD::FADD, MVT::f16, Promote);
     setOperationAction(ISD::FSUB, MVT::f16, Promote);
     setOperationAction(ISD::FMUL, MVT::f16, Promote);
     setOperationAction(ISD::FDIV, MVT::f16, Promote);
     setOperationAction(ISD::FREM, MVT::f16, Promote);
     setOperationAction(ISD::FMA, MVT::f16, Promote);
     setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
     setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);

llvm/test/CodeGen/X86/half.ll

entry:
   %4 = select i1 undef, <4 x i16> undef, <4 x i16> %3
   %5 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> %4
   %6 = bitcast <4 x i16> %5 to <4 x half>
   %7 = select <4 x i1> %2, <4 x half> <half 0xH7E00, half 0xH7E00, half 0xH7E00, half 0xH7E00>, <4 x half> %6
   store <4 x half> %7, ptr undef, align 16
   ret void
 }
 
+define half @fcopysign(half %x, half %y) {
+; CHECK-LIBCALL-LABEL: fcopysign:
+; CHECK-LIBCALL:       # %bb.0:
+; CHECK-LIBCALL-NEXT:    pextrw $0, %xmm1, %eax
+; CHECK-LIBCALL-NEXT:    andl $-32768, %eax # imm = 0x8000
+; CHECK-LIBCALL-NEXT:    pextrw $0, %xmm0, %ecx
+; CHECK-LIBCALL-NEXT:    andl $32767, %ecx # imm = 0x7FFF
+; CHECK-LIBCALL-NEXT:    orl %eax, %ecx
+; CHECK-LIBCALL-NEXT:    pinsrw $0, %ecx, %xmm0
+; CHECK-LIBCALL-NEXT:    retq
+;
+; BWON-F16C-LABEL: fcopysign:
+; BWON-F16C:       # %bb.0:
+; BWON-F16C-NEXT:    vpextrw $0, %xmm1, %eax
+; BWON-F16C-NEXT:    andl $-32768, %eax # imm = 0x8000
+; BWON-F16C-NEXT:    vpextrw $0, %xmm0, %ecx
+; BWON-F16C-NEXT:    andl $32767, %ecx # imm = 0x7FFF
+; BWON-F16C-NEXT:    orl %eax, %ecx
+; BWON-F16C-NEXT:    vpinsrw $0, %ecx, %xmm0, %xmm0
+; BWON-F16C-NEXT:    retq
+;
+; CHECK-I686-LABEL: fcopysign:
+; CHECK-I686:       # %bb.0:
+; CHECK-I686-NEXT:    movl $-32768, %eax # imm = 0x8000
+; CHECK-I686-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-I686-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; CHECK-I686-NEXT:    andl $32767, %ecx # imm = 0x7FFF
+; CHECK-I686-NEXT:    orl %eax, %ecx
+; CHECK-I686-NEXT:    pinsrw $0, %ecx, %xmm0
+; CHECK-I686-NEXT:    retl
+  %a = call half @llvm.copysign.f16(half %x, half %y)
+  ret half %a
+}
+
 declare half @llvm.fabs.f16(half)
+declare half @llvm.copysign.f16(half, half)
 
 attributes #0 = { nounwind }