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Differential D125988

[x86][SelectionDAG] Unroll vectorized FREM instructions which will be lowered to libcalls
ClosedPublic

Authored by n-omer on May 19 2022, 9:33 AM.

Details

Reviewers
RKSimon
andreadb
craig.topper
efriedma
spatel
Commits
rG8b5d9cbbfedc: [x86][DAG] Unroll vectorized FREMs that will become libcalls
Summary

Currently, two element vectors produced as the result of a binary op are
widened to four element vectors on x86 by
DAGTypeLegalizer::WidenVecRes_BinaryCanTrap. If the op still isn't legal
after widening it is unrolled into scalar 4 scalar ops in selectionDAG before
being converted into a libcall. This way we end up with 4 libcalls (two of them
on known undef elements) instead of the original two libcalls.

This patch modifies DAGTypeLegalizer::WidenVectorResult to ensure
that if it is known that an binary op will be turned into a libcall, it is
unrolled instead of being widened. This prevents the creation of the extra
scalar instructions on known undef elements and (eventually) libcalls with
known undef parameters which would otherwise be created when the op gets
expanded post widening.

llvm/test/CodeGen/X86/frem-libcall.ll:

Regression test for the change.

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:

The change in SelectionDAG as mentioned above.

Diff Detail

Event Timeline

n-omer created this revision.May 19 2022, 9:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 19 2022, 9:33 AM
Herald added subscribers: StephenFan, ecnelises, pengfei, hiraditya. · View Herald Transcript
n-omer requested review of this revision.May 19 2022, 9:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 19 2022, 9:33 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B165353: Diff 430716.May 19 2022, 9:34 AM
RKSimon added reviewers: efriedma, spatel.May 19 2022, 9:37 AM
RKSimon added a comment.May 19 2022, 9:41 AM

Probably pull out the frem.ll and frem-libcall.ll tests into their own phab for review first - frem-libcall.ll in particular doesn't show the current problem in trunk (it generates 4 fmodf calls atm).

llvm/test/CodeGen/X86/frem-libcall.ll
5

Sort this to keep the description more easy to notice:

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu < %s  | FileCheck %s

; Ensure vectorized FREMs are not widened/unrolled such that they get lowered
; into libcalls on undef elements.
llvm/test/CodeGen/X86/frem.ll
4 ↗(On Diff #430716)

Sort this to keep the description more easy to notice:

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu < %s  | FileCheck %s

; Basic test coverage for FREM
95 ↗(On Diff #430716)

very pedantic - but maybe sort the vector tests by size - the v8f16/v4f32/v2f64 first - then the 256 / 512-bit variants.

309 ↗(On Diff #430716)

frem_v4f32

efriedma added a comment.May 19 2022, 12:09 PM

This makes the names and conventions here seem very confusing. The function is called WidenVecRes_BinaryCanTrap, but we're dealing with operations that can't actually trap. And it now has two different ways of unrolling an operation, depending on whether we're generating a libcall: the existing codepath uses smaller vectors, and the new one completely unrolls.

Can we unify the determination of whether we want to generate operations involving undef? And can we unify how we unroll an operation?

craig.topper added a comment.May 19 2022, 9:42 PM

Why do we need to anything more than what we do for ISD::FSIN and friends already? LegalizeDAG.cpp doesn't have an Expand other than libcall for ISD::FREM. So checking TLI.isOperationExpand like we do for FSIN should be sufficient right?

n-omer mentioned this in D126055: [X86] Add tests for FREM.May 20 2022, 2:34 AM

Hi @RKSimon, I've updated the tests for the current trunk and split them off into https://reviews.llvm.org/D126055.

jmorse mentioned this in rGaed49eac87b8: [X86] Add tests for FREM.May 20 2022, 8:28 AM
n-omer updated this revision to Diff 431000.EditedMay 20 2022, 9:34 AM

Updating the diff for completeness because D126055. Still looking into the reviewers comments.

Harbormaster completed remote builds in B165542: Diff 431000.May 20 2022, 9:34 AM
n-omer updated this revision to Diff 431365.May 23 2022, 7:27 AM

Update diff based on review comments.

n-omer updated this revision to Diff 431367.May 23 2022, 7:30 AM

Add context to diff.

n-omer edited the summary of this revision. (Show Details)May 23 2022, 7:33 AM
n-omer updated this revision to Diff 431371.May 23 2022, 7:36 AM

Remove FIXME from test.

RKSimon added a comment.May 23 2022, 7:59 AM

LGTM - its annoying that we can't reuse the similar code for the unary ops, but not a big issue. I think we will probably need to add FPOW and the integer division/remainder, but we can address that later.

@craig.topper @efriedma Any comments?

Harbormaster completed remote builds in B165839: Diff 431371.May 23 2022, 8:54 AM
spatel added inline comments.May 23 2022, 9:34 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
3682

Instead of copying this block, create a lambda above the switch and call it from here and the existing code?

auto unrollExpandedOp = [&]() {
  // We're going to widen this vector op to a legal type by padding with undef
  // elements. If the wide vector op is eventually going to be expanded to
  // scalar libcalls, then unroll into scalar ops now to avoid unnecessary
  // libcalls on the undef elements.
  EVT VT = N->getValueType(0);
  EVT WideVecVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
  if (!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) &&
      TLI.isOperationExpand(N->getOpcode(), VT.getScalarType())) {
    Res = DAG.UnrollVectorOp(N, WideVecVT.getVectorNumElements());
    return true;
  }
  return false;
};
n-omer updated this revision to Diff 431415.May 23 2022, 10:01 AM

Update diff based on reviewer's comments.

Thanks @spatel.

Harbormaster completed remote builds in B165871: Diff 431415.May 23 2022, 10:37 AM
RKSimon added inline comments.May 24 2022, 12:14 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
3703

remove these braces now?

3796

these braces can go now?

n-omer updated this revision to Diff 431616.May 24 2022, 1:49 AM

Update diff based on reviewer's comments.

Thanks @RKSimon.

Harbormaster completed remote builds in B166009: Diff 431616.May 24 2022, 2:24 AM
RKSimon accepted this revision.May 24 2022, 2:24 AM

LGTM

This revision is now accepted and ready to land.May 24 2022, 2:24 AM
RKSimon mentioned this in rG64186e9b351a: [X86] Add test showing failure to expand <2 x float> fpow without widening to….May 24 2022, 2:58 AM
This revision was landed with ongoing or failed builds.May 24 2022, 5:35 AM
Closed by commit rG8b5d9cbbfedc: [x86][DAG] Unroll vectorized FREMs that will become libcalls (authored by n-omer, committed by jmorse). · Explain Why
This revision was automatically updated to reflect the committed changes.
jmorse added a commit: rG8b5d9cbbfedc: [x86][DAG] Unroll vectorized FREMs that will become libcalls.
RKSimon mentioned this in rG11455e475889: [DAG] Unroll vectorized FPOW instructions before widening that will scalarize….May 24 2022, 7:45 AM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
LegalizeVectorTypes.cpp
LegalizeVectorTypes.cpp
10 lines
Target/
X86/
X86ISelLowering.cpp
X86ISelLowering.cpp
19 lines
test/
Analysis/
CostModel/
X86/
arith-fp.ll
arith-fp.ll
112 lines
CodeGen/
X86/
frem-libcall.ll
frem-libcall.ll
22 lines

Diff 431000

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Context not available.
VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
} }
// If the widened op is not legal and the scalar variants
// will be turned into libcalls, unroll the op to prevent
// widening so that we don't end up with libcalls on
// undef elements.
if (!TLI.isOperationLegal(Opcode, VT) &&
TLI.getOperationAction(Opcode, VT.getScalarType()) ==
TargetLowering::LibCall) {
return DAG.UnrollVectorOp(N, VT.getVectorNumElements());
}
if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
// Operation doesn't trap so just widen as normal. // Operation doesn't trap so just widen as normal.
SDValue InOp1 = GetWidenedVector(N->getOperand(0)); SDValue InOp1 = GetWidenedVector(N->getOperand(0));
Context not available.

llvm/lib/Target/X86/X86ISelLowering.cpp

Context not available.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
setOperationAction(ISD::FREM , MVT::f32 , Expand); setOperationAction(ISD::FREM , MVT::f32 , LibCall);
setOperationAction(ISD::FREM , MVT::f64 , Expand); setOperationAction(ISD::FREM , MVT::f64 , LibCall);
setOperationAction(ISD::FREM , MVT::f80 , Expand); setOperationAction(ISD::FREM , MVT::f80 , Expand);
setOperationAction(ISD::FREM , MVT::f128 , Expand); setOperationAction(ISD::FREM , MVT::f128 , Expand);
Context not available.
// This is what the CRT headers do - `fmodf` is an inline header // This is what the CRT headers do - `fmodf` is an inline header
// function casting to f64 and calling `fmod`. // function casting to f64 and calling `fmod`.
if (Subtarget.is32Bit() && if (Subtarget.is32Bit() &&
(Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium())) (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium())) {
for (ISD::NodeType Op : for (ISD::NodeType Op :
{ISD::FCEIL, ISD::STRICT_FCEIL, {ISD::FCEIL, ISD::STRICT_FCEIL,
ISD::FCOS, ISD::STRICT_FCOS, ISD::FCOS, ISD::STRICT_FCOS,
ISD::FEXP, ISD::STRICT_FEXP, ISD::FEXP, ISD::STRICT_FEXP,
ISD::FFLOOR, ISD::STRICT_FFLOOR, ISD::FFLOOR, ISD::STRICT_FFLOOR,
ISD::FREM, ISD::STRICT_FREM,
ISD::FLOG, ISD::STRICT_FLOG, ISD::FLOG, ISD::STRICT_FLOG,
ISD::FLOG10, ISD::STRICT_FLOG10, ISD::FLOG10, ISD::STRICT_FLOG10,
ISD::FPOW, ISD::STRICT_FPOW, ISD::FPOW, ISD::STRICT_FPOW,
ISD::FSIN, ISD::STRICT_FSIN}) ISD::FSIN, ISD::STRICT_FSIN})
if (isOperationExpand(Op, MVT::f32)) if (isOperationExpand(Op, MVT::f32))
setOperationAction(Op, MVT::f32, Promote); setOperationAction(Op, MVT::f32, Promote);
// The default action for f32 FREMs on X86 is LibCall
// so these need to be explicitly changed to Promote.
setOperationAction(ISD::FREM, MVT::f32, Promote);
setOperationAction(ISD::STRICT_FREM, MVT::f32, Promote);
}
// We have target-specific dag combine patterns for the following nodes: // We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE, setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
Context not available.

llvm/test/Analysis/CostModel/X86/arith-fp.ll

Context not available.
define i32 @frem(i32 %arg) { define i32 @frem(i32 %arg) {
; SSE1-LABEL: 'frem' ; SSE1-LABEL: 'frem'
; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef ; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = frem float undef, undef
; SSE1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef ; SSE1-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4F32 = frem <4 x float> undef, undef
; SSE1-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef ; SSE1-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8F32 = frem <8 x float> undef, undef
; SSE1-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef ; SSE1-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V16F32 = frem <16 x float> undef, undef
; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef ; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = frem double undef, undef
; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = frem <2 x double> undef, undef ; SSE1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = frem <2 x double> undef, undef
; SSE1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = frem <4 x double> undef, undef ; SSE1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4F64 = frem <4 x double> undef, undef
; SSE1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F64 = frem <8 x double> undef, undef ; SSE1-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V8F64 = frem <8 x double> undef, undef
; SSE1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; SSE1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
; ;
; SSE2-LABEL: 'frem' ; SSE2-LABEL: 'frem'
; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef ; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = frem float undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef ; SSE2-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4F32 = frem <4 x float> undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef ; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8F32 = frem <8 x float> undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef ; SSE2-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V16F32 = frem <16 x float> undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef ; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = frem double undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef ; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F64 = frem <2 x double> undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = frem <4 x double> undef, undef ; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = frem <4 x double> undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = frem <8 x double> undef, undef ; SSE2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8F64 = frem <8 x double> undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
; ;
; SSE42-LABEL: 'frem' ; SSE42-LABEL: 'frem'
; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef ; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = frem float undef, undef
; SSE42-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef ; SSE42-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4F32 = frem <4 x float> undef, undef
; SSE42-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef ; SSE42-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8F32 = frem <8 x float> undef, undef
; SSE42-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef ; SSE42-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V16F32 = frem <16 x float> undef, undef
; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef ; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = frem double undef, undef
; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef ; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F64 = frem <2 x double> undef, undef
; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = frem <4 x double> undef, undef ; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = frem <4 x double> undef, undef
; SSE42-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = frem <8 x double> undef, undef ; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8F64 = frem <8 x double> undef, undef
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
; ;
; AVX-LABEL: 'frem' ; AVX-LABEL: 'frem'
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef ; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = frem float undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef ; AVX-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4F32 = frem <4 x float> undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8F32 = frem <8 x float> undef, undef ; AVX-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %V8F32 = frem <8 x float> undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 68 for instruction: %V16F32 = frem <16 x float> undef, undef ; AVX-NEXT: Cost Model: Found an estimated cost of 100 for instruction: %V16F32 = frem <16 x float> undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef ; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = frem double undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef ; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F64 = frem <2 x double> undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F64 = frem <4 x double> undef, undef ; AVX-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V4F64 = frem <4 x double> undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V8F64 = frem <8 x double> undef, undef ; AVX-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8F64 = frem <8 x double> undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
; ;
; AVX512-LABEL: 'frem' ; AVX512-LABEL: 'frem'
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef ; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = frem float undef, undef
; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef ; AVX512-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4F32 = frem <4 x float> undef, undef
; AVX512-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8F32 = frem <8 x float> undef, undef ; AVX512-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %V8F32 = frem <8 x float> undef, undef
; AVX512-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %V16F32 = frem <16 x float> undef, undef ; AVX512-NEXT: Cost Model: Found an estimated cost of 104 for instruction: %V16F32 = frem <16 x float> undef, undef
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef ; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = frem double undef, undef
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef ; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F64 = frem <2 x double> undef, undef
; AVX512-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F64 = frem <4 x double> undef, undef ; AVX512-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V4F64 = frem <4 x double> undef, undef
; AVX512-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8F64 = frem <8 x double> undef, undef ; AVX512-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V8F64 = frem <8 x double> undef, undef
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
; ;
; SLM-LABEL: 'frem' ; SLM-LABEL: 'frem'
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef ; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = frem float undef, undef
; SLM-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef ; SLM-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4F32 = frem <4 x float> undef, undef
; SLM-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef ; SLM-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8F32 = frem <8 x float> undef, undef
; SLM-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef ; SLM-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V16F32 = frem <16 x float> undef, undef
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef ; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = frem double undef, undef
; SLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef ; SLM-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F64 = frem <2 x double> undef, undef
; SLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = frem <4 x double> undef, undef ; SLM-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = frem <4 x double> undef, undef
; SLM-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = frem <8 x double> undef, undef ; SLM-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8F64 = frem <8 x double> undef, undef
; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
; ;
; GLM-LABEL: 'frem' ; GLM-LABEL: 'frem'
; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = frem float undef, undef ; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = frem float undef, undef
; GLM-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4F32 = frem <4 x float> undef, undef ; GLM-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4F32 = frem <4 x float> undef, undef
; GLM-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8F32 = frem <8 x float> undef, undef ; GLM-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8F32 = frem <8 x float> undef, undef
; GLM-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V16F32 = frem <16 x float> undef, undef ; GLM-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V16F32 = frem <16 x float> undef, undef
; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = frem double undef, undef ; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = frem double undef, undef
; GLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = frem <2 x double> undef, undef ; GLM-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F64 = frem <2 x double> undef, undef
; GLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = frem <4 x double> undef, undef ; GLM-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = frem <4 x double> undef, undef
; GLM-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = frem <8 x double> undef, undef ; GLM-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8F64 = frem <8 x double> undef, undef
; GLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; GLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
; ;
%F32 = frem float undef, undef %F32 = frem float undef, undef
Context not available.

llvm/test/CodeGen/X86/frem-libcall.ll

Context not available.
; CHECK-LABEL: frem: ; CHECK-LABEL: frem:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $80, %rsp ; CHECK-NEXT: subq $64, %rsp
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: divps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload ; CHECK-NEXT: divps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; CHECK-NEXT: addss %xmm1, %xmm0 ; CHECK-NEXT: addss %xmm1, %xmm0
; CHECK-NEXT: movlps %xmm1, (%rbx) ; CHECK-NEXT: movlps %xmm1, (%rbx)
; CHECK-NEXT: addq $80, %rsp ; CHECK-NEXT: addq $64, %rsp
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%frem = frem <2 x float> %a0, %a1 %frem = frem <2 x float> %a0, %a1
Context not available.