[TableGen][DirectX] Add tableGen backend to generate map from llvm intrinsic to DXIL operation.

[python3kgae]

Summary

A new tableGen backend gen-dxil-intrinsic-map is added to generate map from llvm intrinsic to DXIL operation.

A new file "DXILIntrinsicMap.inc" will be generated when build DirectX target which include the map.

The generated map will replace the manually created map when find DXIL operation from llvm intrinsic.

[nhaehnle]

Running TableGen multiple times is a bit annoying for LLVM build times. Have you considered packing all outputs into the same .inc file?

[python3kgae]

In D125519#3517697, @nhaehnle wrote:

Running TableGen multiple times is a bit annoying for LLVM build times. Have you considered packing all outputs into the same .inc file?

Sure. I'll make all these things into one '.inc` file.
Thanks for the suggestion.

[python3kgae]

Move EmitDXILIntrinsicMap into EmitDXILOperation.

[python3kgae]

Add static for internal function.

[bogner]

llvm/lib/Target/DirectX/DXILOpLowering.cpp

67

Why do this? Since the switch statement covers all values of the enum there are nice warnings (at least if you build with clang) if someone adds another OverloadKind, and forgets to update here, whereas with the default statement that's not the case.

I guess some compilers might warn that not all paths return a value though if they think we can fall out of the switch. If you're just trying to handle that warning then it's probably best to move the llvm_unreachable + return statement out of the switch and just put break here, to get the best of both worlds.

llvm/utils/TableGen/DXILEmitter.cpp

84

Might be worth an assert that the intrinsic name starts with "int_" just in case someone makes a mistake in the td. OTOH I think we'll already error in that case because map_intrinsic won't find anything, so maybe it's fine.

165

Probably better done as a separate change, but is a SmallDenseMap really the best option here? We could probably just store this as an array of pairs and pre-sort it, then query it with std::lower_bound on the keys instead.

[python3kgae]

Update to match the comments.

[python3kgae]

llvm/utils/TableGen/DXILEmitter.cpp

165

Tried to change to array. But find it hard to get intrinsic ID in tableGen for pre-sort.
Leave it for future change.

llvm/lib/Target/DirectX/CMakeLists.txt

 add_llvm_component_group(DirectX)
 
 set(LLVM_TARGET_DEFINITIONS DirectX.td)
 
 tablegen(LLVM DirectXGenSubtargetInfo.inc -gen-subtarget)
 
 set(LLVM_TARGET_DEFINITIONS DXIL.td)
 tablegen(LLVM DXILConstants.inc -gen-dxil-enum)
+tablegen(LLVM DXILIntrinsicMap.inc -gen-dxil-intrinsic-map)
 
 add_public_tablegen_target(DirectXCommonTableGen)
 
 add_llvm_target(DirectXCodeGen
   DirectXSubtarget.cpp
   DirectXTargetMachine.cpp
   DXILOpLowering.cpp
   DXILPointerType.cpp

llvm/lib/Target/DirectX/DXILOpLowering.cpp

case OverloadKind::I16:
     return "i16";
   case OverloadKind::I32:
     return "i32";
   case OverloadKind::I64:
     return "i64";
   case OverloadKind::VOID:
   case OverloadKind::ObjectType:
   case OverloadKind::UserDefineType:
     llvm_unreachable("invalid overload type for name");
     break;
   }
 }
 
 static OverloadKind getOverloadKind(Type *Ty) {
   Type::TypeID T = Ty->getTypeID();
   switch (T) {
   case Type::VoidTyID:
for (User *U : make_early_inc_range(F.users())) {
     CI->eraseFromParent();
   }
   if (F.user_empty())
     F.eraseFromParent();
 }
 
 static bool lowerIntrinsics(Module &M) {
   bool Updated = false;
-  static SmallDenseMap<Intrinsic::ID, DXIL::OpCode> LowerMap = {
-      {Intrinsic::sin, DXIL::OpCode::Sin}};
+#include "DXILIntrinsicMap.inc"
   for (Function &F : make_early_inc_range(M.functions())) {
     if (!F.isDeclaration())
       continue;
     Intrinsic::ID ID = F.getIntrinsicID();
     auto LowerIt = LowerMap.find(ID);
     if (LowerIt == LowerMap.end())
       continue;
     lowerIntrinsic(LowerIt->second, F, M);

llvm/utils/TableGen/DXILEmitter.cpp

struct DXILOperationData {
   StringRef DXILClass; // name of the opcode class
   StringRef Category;  // classification for this instruction
   StringRef Doc;       // the documentation description of this instruction
 
   SmallVector<DXILParam> Params; // the operands that this instruction takes
   StringRef OverloadTypes;       // overload types if applicable
   StringRef FnAttr;              // attribute shorthands: rn=does not access
                                  // memory,ro=only reads from memory,
-  bool IsDeriv;                  // whether this is some kind of derivative
-  bool IsGradient;               // whether this requires a gradient calculation
-  bool IsFeedback;               // whether this is a sampler feedback op
+  StringRef Intrinsic; // The llvm intrinsic map to DXILOp. Default is "" which
+                       // means no map exist.
+  bool IsDeriv;        // whether this is some kind of derivative
+  bool IsGradient;     // whether this requires a gradient calculation
+  bool IsFeedback;     // whether this is a sampler feedback op
   bool IsWave; // whether this requires in-wave, cross-lane functionality
   bool RequiresUniformInputs; // whether this operation requires that all
                               // of its inputs are uniform across the wave
   SmallVector<StringRef, 4>
       ShaderStages; // shader stages to which this applies, empty for all.
   DXILShaderModel ShaderModel;           // minimum shader model required
   DXILShaderModel ShaderModelTranslated; // minimum shader model required with
                                          // translation by linker
   SmallVector<StringRef, 4> counters;    // counters for this inst.
   DXILOperationData(const Record *R) {
     Name = R->getValueAsString("name");
     DXILOp = R->getValueAsString("dxil_op");
     DXILOpID = R->getValueAsInt("dxil_opid");
     DXILClass = R->getValueAsString("dxil_class");
     Category = R->getValueAsString("category");
     Doc = R->getValueAsString("doc");
     ListInit *ParamList = R->getValueAsListInit("ops");
     for (unsigned i = 0; i < ParamList->size(); ++i) {
       Record *Param = ParamList->getElementAsRecord(i);
       Params.emplace_back(DXILParam(Param));
     }
     OverloadTypes = R->getValueAsString("oload_types");
     FnAttr = R->getValueAsString("fn_attr");
+    Intrinsic = R->getValueAsString("llvm_intrinsic");
   }
 };
 } // end anonymous namespace
 
 static void emitDXILOpEnum(DXILOperationData &DXILOp, raw_ostream &OS) {
   // Name = ID, // Doc
   OS << DXILOp.Name << " = " << DXILOp.DXILOpID << ", // " << DXILOp.Doc
      << "\n";
static void emitDXILEnums(std::vector<DXILOperationData> &DXILOps,
   }
   OS << "\n};\n\n";
 }
 
 namespace llvm {
 // Emit enum declaration for DXIL.
 void EmitDXILEnum(RecordKeeper &Records, raw_ostream &OS) {
   std::vector<Record *> Ops = Records.getAllDerivedDefinitions("dxil_op");
   OS << "// Generated code, do not edit.\n";
   OS << "\n";
   std::vector<DXILOperationData> DXILOps;
   DXILOps.reserve(Ops.size());
   for (auto *Record : Ops) {
     DXILOps.emplace_back(DXILOperationData(Record));
   }
   emitDXILEnums(DXILOps, OS);
   OS << "\n";
 }
 
+// Emit map from llvm intrinsic to DXIL operation.
+void EmitDXILIntrinsicMap(RecordKeeper &Records, raw_ostream &OS) {
+  std::vector<Record *> Ops = Records.getAllDerivedDefinitions("dxil_op");
+  OS << "// Generated code, do not edit.\n";
+  OS << "\n";
+  OS << "static const SmallDenseMap<Intrinsic::ID, DXIL::OpCode> LowerMap = "
+        "{\n";
+  for (auto *Record : Ops) {
+    DXILOperationData DXILOp(Record);
+    if (DXILOp.Intrinsic.empty())
+      continue;
+    // {Intrinsic::sin, DXIL::OpCode::Sin},
+    OS << "  { Intrinsic::" << DXILOp.Intrinsic
+       << ", DXIL::OpCode::" << DXILOp.DXILOp << "},\n";
+  }
+  OS << "};\n";
+  OS << "\n";
+}
+
 } // namespace llvm

llvm/utils/TableGen/TableGen.cpp

enum ActionType {
   GenX86FoldTables,
   GenX86MnemonicTables,
   GenRegisterBank,
   GenExegesis,
   GenAutomata,
   GenDirectivesEnumDecl,
   GenDirectivesEnumImpl,
   GenDXILEnum,
+  GenDXILIntrinsicMap,
 };
 
 namespace llvm {
 cl::opt<bool> EmitLongStrLiterals(
     "long-string-literals",
     cl::desc("when emitting large string tables, prefer string literals over "
              "comma-separated char literals. This can be a readability and "
              "compile-time performance win, but upsets some compilers"),
cl::values(
                    "Generate registers bank descriptions"),
         clEnumValN(GenExegesis, "gen-exegesis",
                    "Generate llvm-exegesis tables"),
         clEnumValN(GenAutomata, "gen-automata", "Generate generic automata"),
         clEnumValN(GenDirectivesEnumDecl, "gen-directive-decl",
                    "Generate directive related declaration code (header file)"),
         clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
                    "Generate directive related implementation code"),
-        clEnumValN(GenDXILEnum, "gen-dxil-enum", "Generate enum for DXIL")));
+        clEnumValN(GenDXILEnum, "gen-dxil-enum", "Generate enum for DXIL"),
+        clEnumValN(GenDXILIntrinsicMap, "gen-dxil-intrinsic-map",
+                   "Generate map from llvm intrinsic to DXIL operation")));
 
 cl::OptionCategory PrintEnumsCat("Options for -print-enums");
 cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
                            cl::value_desc("class name"),
                            cl::cat(PrintEnumsCat));
 
 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   switch (Action) {
case GenDirectivesEnumDecl:
     EmitDirectivesDecl(Records, OS);
     break;
   case GenDirectivesEnumImpl:
     EmitDirectivesImpl(Records, OS);
     break;
   case GenDXILEnum:
     EmitDXILEnum(Records, OS);
     break;
+  case GenDXILIntrinsicMap:
+    EmitDXILIntrinsicMap(Records, OS);
+    break;
   }
 
   return false;
 }
 }
 
 int main(int argc, char **argv) {
   InitLLVM X(argc, argv);

llvm/utils/TableGen/TableGenBackends.h

 void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &OS);
 void EmitX86MnemonicTables(RecordKeeper &RK, raw_ostream &OS);
 void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);
 void EmitExegesis(RecordKeeper &RK, raw_ostream &OS);
 void EmitAutomata(RecordKeeper &RK, raw_ostream &OS);
 void EmitDirectivesDecl(RecordKeeper &RK, raw_ostream &OS);
 void EmitDirectivesImpl(RecordKeeper &RK, raw_ostream &OS);
 void EmitDXILEnum(RecordKeeper &RK, raw_ostream &OS);
+void EmitDXILIntrinsicMap(RecordKeeper &RK, raw_ostream &OS);
 
 } // End llvm namespace
 
 #endif