[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI

[luismarques]

Summary

Builds upon D123264, adding support to merge the low part of the LLA address into the load/store instruction offsets.

This needs more testing and more tests. But the priority is reviewing D123264, to clarify if this is even a viable approach.

[craig.topper]

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

401

Do we need to check that the immediate operand of the load/store is 0 before we remove it?

[luismarques]

• Rebase
• Handle non-zero offsets in tail load/store instructions

[luismarques]

Nit: tweak comments.

[luismarques]

Rebase after D128599.

[craig.topper]

I think calling setOffset on the pcrel_lo offset is incorrect. That always points to the auipc it shouldn't have an offset.

llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll

365

This is incorrect. There shouldn't be a +4 on the pcrel_lo relocation.

378

Here too

417

And here

[luismarques]

Fix pointing to the AUIPC label

[craig.topper]

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

125

This should also be skipped if Hi is AUIPC

[luismarques]

Address review feedback

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

 //===----- RISCVMergeBaseOffset.cpp - Optimise address calculations  ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // Merge the offset of address calculation into the offset field
-// of instructions in a global address lowering sequence. This pass transforms:
-//   lui  vreg1, %hi(s)
-//   addi vreg2, vreg1, %lo(s)
-//   addi vreg3, verg2, Offset
-//
-//   Into:
-//   lui  vreg1, %hi(s+Offset)
-//   addi vreg2, vreg1, %lo(s+Offset)
-//
-// The transformation is carried out under certain conditions:
-// 1) The offset field in the base of global address lowering sequence is zero.
-// 2) The lowered global address has only one use.
+// of instructions in a global address lowering sequence.
 //
-// The offset field can be in a different form. This pass handles all of them.
 //===----------------------------------------------------------------------===//
 
 #include "RISCV.h"
 #include "RISCVTargetMachine.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Target/TargetOptions.h"
 #include <set>
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-merge-base-offset"
 #define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset"
 namespace {
 
 struct RISCVMergeBaseOffsetOpt : public MachineFunctionPass {
 private:
   const RISCVSubtarget *ST = nullptr;
 
 public:
   static char ID;
   bool runOnMachineFunction(MachineFunction &Fn) override;
-  bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI);
+  bool detectFoldable(MachineInstr &Hi, MachineInstr *&Lo);
 
-  bool detectAndFoldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI);
-  void foldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI, MachineInstr &Tail,
+  bool detectAndFoldOffset(MachineInstr &Hi, MachineInstr &Lo);
+  void foldOffset(MachineInstr &Hi, MachineInstr &Lo, MachineInstr &Tail,
                   int64_t Offset);
   bool matchLargeOffset(MachineInstr &TailAdd, Register GSReg, int64_t &Offset);
   bool matchShiftedOffset(MachineInstr &TailShXAdd, Register GSReg,
                           int64_t &Offset);
 
   RISCVMergeBaseOffsetOpt() : MachineFunctionPass(ID) {}
 
   MachineFunctionProperties getRequiredProperties() const override {
private:
   std::set<MachineInstr *> DeadInstrs;
 };
 } // end anonymous namespace
 
 char RISCVMergeBaseOffsetOpt::ID = 0;
 INITIALIZE_PASS(RISCVMergeBaseOffsetOpt, DEBUG_TYPE,
                 RISCV_MERGE_BASE_OFFSET_NAME, false, false)
 
-// Detect the pattern:
+// Detect either of the patterns:
+//
+// 1. (medlow pattern):
 //   lui   vreg1, %hi(s)
 //   addi  vreg2, vreg1, %lo(s)
 //
-//   Pattern only accepted if:
-//     1) ADDI has only one use.
-//     2) LUI has only one use; which is the ADDI.
-//     3) Both ADDI and LUI have GlobalAddress type which indicates that these
-//        are generated from global address lowering.
-//     4) Offset value in the Global Address is 0.
-bool RISCVMergeBaseOffsetOpt::detectLuiAddiGlobal(MachineInstr &HiLUI,
-                                                  MachineInstr *&LoADDI) {
-  if (HiLUI.getOpcode() != RISCV::LUI ||
-      HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI ||
-      !HiLUI.getOperand(1).isGlobal() ||
-      HiLUI.getOperand(1).getOffset() != 0 ||
-      !MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
-    return false;
-  Register HiLuiDestReg = HiLUI.getOperand(0).getReg();
-  LoADDI = &*MRI->use_instr_begin(HiLuiDestReg);
-  if (LoADDI->getOpcode() != RISCV::ADDI ||
-      LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO ||
-      !LoADDI->getOperand(2).isGlobal() ||
-      LoADDI->getOperand(2).getOffset() != 0)
+// 2. (medany pattern):
+// .Lpcrel_hi1:
+//   auipc vreg1, %pcrel_hi(s)
+//   addi  vreg2, vreg1, %pcrel_lo(.Lpcrel_hi1)
+//
+// The pattern is only accepted if:
+//    1) The first instruction has only one use, which is the ADDI.
+//    2) The address operands have the appropriate type, reflecting the
+//       lowering of a global address using medlow or medany.
+//    3) The offset value in the Global Address is 0.
+bool RISCVMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi,
+                                             MachineInstr *&Lo) {
+  if (Hi.getOpcode() == RISCV::LUI) {
+    if (Hi.getOperand(1).getTargetFlags() != RISCVII::MO_HI ||
+        !Hi.getOperand(1).isGlobal() || Hi.getOperand(1).getOffset() != 0 ||
+        !MRI->hasOneUse(Hi.getOperand(0).getReg()))
+      return false;
+    Register HiDestReg = Hi.getOperand(0).getReg();
+    Lo = &*MRI->use_instr_begin(HiDestReg);
+    if (Lo->getOpcode() != RISCV::ADDI ||
+        Lo->getOperand(2).getTargetFlags() != RISCVII::MO_LO ||
+        !Lo->getOperand(2).isGlobal() || Lo->getOperand(2).getOffset() != 0)
+      return false;
+    return true;
+  } else if (Hi.getOpcode() == RISCV::AUIPC) {
+    if (Hi.getOperand(1).getTargetFlags() != RISCVII::MO_PCREL_HI ||
+        !Hi.getOperand(1).isGlobal() || Hi.getOperand(1).getOffset() != 0 ||
+        !MRI->hasOneUse(Hi.getOperand(0).getReg()))
+      return false;
+    Register HiDestReg = Hi.getOperand(0).getReg();
+    Lo = &*MRI->use_instr_begin(HiDestReg);
+    if (Lo->getOpcode() != RISCV::ADDI ||
+        Lo->getOperand(2).getTargetFlags() != RISCVII::MO_PCREL_LO ||
+        Lo->getOperand(2).getType() != MachineOperand::MO_MCSymbol)
       return false;
     return true;
+  } else {
+    return false;
+  }
 }
 
-// Update the offset in HiLUI and LoADDI instructions.
+// Update the offset in Hi and Lo instructions.
 // Delete the tail instruction and update all the uses to use the
-// output from LoADDI.
-void RISCVMergeBaseOffsetOpt::foldOffset(MachineInstr &HiLUI,
-                                         MachineInstr &LoADDI,
+// output from Lo.
+void RISCVMergeBaseOffsetOpt::foldOffset(MachineInstr &Hi, MachineInstr &Lo,
                                          MachineInstr &Tail, int64_t Offset) {
   assert(isInt<32>(Offset) && "Unexpected offset");
-  // Put the offset back in HiLUI and the LoADDI
-  HiLUI.getOperand(1).setOffset(Offset);
-  LoADDI.getOperand(2).setOffset(Offset);
+  // Put the offset back in Hi and the Lo
+  Hi.getOperand(1).setOffset(Offset);
+  Lo.getOperand(2).setOffset(Offset);
   // Delete the tail instruction.
   DeadInstrs.insert(&Tail);
-  MRI->replaceRegWith(Tail.getOperand(0).getReg(),
-                      LoADDI.getOperand(0).getReg());
+  MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg());
   LLVM_DEBUG(dbgs() << "  Merged offset " << Offset << " into base.\n"
-                    << "     " << HiLUI << "     " << LoADDI;);
+                    << "     " << Hi << "     " << Lo;);
 }
 
 // Detect patterns for large offsets that are passed into an ADD instruction.
 //
 //                     Base address lowering is of the form:
 //                        HiLUI:  lui   vreg1, %hi(s)
 //                       LoADDI:  addi  vreg2, vreg1, %lo(s)
 //                       /                                  \
bool RISCVMergeBaseOffsetOpt::matchLargeOffset(MachineInstr &TailAdd,
   assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!");
   Register Rs = TailAdd.getOperand(1).getReg();
   Register Rt = TailAdd.getOperand(2).getReg();
   Register Reg = Rs == GAReg ? Rt : Rs;
 
   // Can't fold if the register has more than one use.
   if (!MRI->hasOneUse(Reg))
     return false;
-  // This can point to an ADDI or a LUI:
+  // This can point to an ADDI(W) or a LUI:
   MachineInstr &OffsetTail = *MRI->getVRegDef(Reg);
   if (OffsetTail.getOpcode() == RISCV::ADDI ||
       OffsetTail.getOpcode() == RISCV::ADDIW) {
     // The offset value has non zero bits in both %hi and %lo parts.
     // Detect an ADDI that feeds from a LUI instruction.
     MachineOperand &AddiImmOp = OffsetTail.getOperand(2);
     if (AddiImmOp.getTargetFlags() != RISCVII::MO_None)
       return false;
if (OffsetTail.getOpcode() == RISCV::ADDI ||
     Offset = SignExtend64<32>(OffsetTail.getOperand(1).getImm() << 12);
     DeadInstrs.insert(&OffsetTail);
     return true;
   }
   return false;
 }
 
 // Detect patterns for offsets that are passed into a SHXADD instruction.
-// The offset has 1,2, or 3 trailing zeros and fits in simm13, simm14, simm15.
-// The constant is created with addi    voff, x0, C, and shXadd is used to
+// The offset has 1, 2, or 3 trailing zeros and fits in simm13, simm14, simm15.
+// The constant is created with addi voff, x0, C, and shXadd is used to
 // fill insert the trailing zeros and do the addition.
 //
-// HiLUI:      lui     vreg1, %hi(s)
-// LoADDI:     addi    vreg2, vreg1, %lo(s)
+// Hi:         lui     vreg1, %hi(s)
+// Lo:         addi    vreg2, vreg1, %lo(s)
 // OffsetTail: addi    voff, x0, C
 // TailAdd:    shXadd  vreg4, voff, vreg2
 bool RISCVMergeBaseOffsetOpt::matchShiftedOffset(MachineInstr &TailShXAdd,
                                                  Register GAReg,
                                                  int64_t &Offset) {
   assert((TailShXAdd.getOpcode() == RISCV::SH1ADD ||
           TailShXAdd.getOpcode() == RISCV::SH2ADD ||
           TailShXAdd.getOpcode() == RISCV::SH3ADD) &&
bool RISCVMergeBaseOffsetOpt::matchShiftedOffset(MachineInstr &TailShXAdd,
 
   Offset = (uint64_t)Offset << ShAmt;
 
   LLVM_DEBUG(dbgs() << "  Offset Instr: " << OffsetTail);
   DeadInstrs.insert(&OffsetTail);
   return true;
 }
 
-bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI,
-                                                  MachineInstr &LoADDI) {
-  Register DestReg = LoADDI.getOperand(0).getReg();
+bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &Hi,
+                                                  MachineInstr &Lo) {
+  Register DestReg = Lo.getOperand(0).getReg();
 
   // First, look for arithmetic instructions we can get an offset from.
   // We might be able to remove the arithmetic instructions by folding the
   // offset into the LUI+ADDI.
   if (MRI->hasOneUse(DestReg)) {
-    // LoADDI has only one use.
+    // Lo has only one use.
     MachineInstr &Tail = *MRI->use_instr_begin(DestReg);
     switch (Tail.getOpcode()) {
     default:
       LLVM_DEBUG(dbgs() << "Don't know how to get offset from this instr:"
                         << Tail);
       break;
     case RISCV::ADDI: {
       // Offset is simply an immediate operand.
       int64_t Offset = Tail.getOperand(2).getImm();
 
       // We might have two ADDIs in a row.
       Register TailDestReg = Tail.getOperand(0).getReg();
       if (MRI->hasOneUse(TailDestReg)) {
         MachineInstr &TailTail = *MRI->use_instr_begin(TailDestReg);
         if (TailTail.getOpcode() == RISCV::ADDI) {
           Offset += TailTail.getOperand(2).getImm();
           LLVM_DEBUG(dbgs() << "  Offset Instrs: " << Tail << TailTail);
           DeadInstrs.insert(&Tail);
-          foldOffset(HiLUI, LoADDI, TailTail, Offset);
+          foldOffset(Hi, Lo, TailTail, Offset);
           return true;
         }
       }
 
       LLVM_DEBUG(dbgs() << "  Offset Instr: " << Tail);
-      foldOffset(HiLUI, LoADDI, Tail, Offset);
+      foldOffset(Hi, Lo, Tail, Offset);
       return true;
     }
     case RISCV::ADD: {
       // The offset is too large to fit in the immediate field of ADDI.
       // This can be in two forms:
       // 1) LUI hi_Offset followed by:
       //    ADDI lo_offset
       //    This happens in case the offset has non zero bits in
       //    both hi 20 and lo 12 bits.
       // 2) LUI (offset20)
       //    This happens in case the lower 12 bits of the offset are zeros.
       int64_t Offset;
       if (!matchLargeOffset(Tail, DestReg, Offset))
         return false;
-      foldOffset(HiLUI, LoADDI, Tail, Offset);
+      foldOffset(Hi, Lo, Tail, Offset);
       return true;
     }
     case RISCV::SH1ADD:
     case RISCV::SH2ADD:
     case RISCV::SH3ADD: {
       // The offset is too large to fit in the immediate field of ADDI.
       // It may be encoded as (SH2ADD (ADDI X0, C), DestReg) or
       // (SH3ADD (ADDI X0, C), DestReg).
       int64_t Offset;
       if (!matchShiftedOffset(Tail, DestReg, Offset))
         return false;
-      foldOffset(HiLUI, LoADDI, Tail, Offset);
+      foldOffset(Hi, Lo, Tail, Offset);
       return true;
     }
     }
   }
 
   // We didn't find an arithmetic instruction. If all the uses are memory ops
-  // with the same offset, we can transform
-  // HiLUI:  lui vreg1, %hi(foo)          --->  lui vreg1, %hi(foo+8)
-  // LoADDI: addi vreg2, vreg1, %lo(foo)  --->  lw vreg3, lo(foo+8)(vreg1)
-  // Tail:   lw vreg3, 8(vreg2)
+  // with the same offset, we can transform:
+  //
+  // 1. (medlow pattern):
+  // Hi:   lui vreg1, %hi(foo)          --->  lui vreg1, %hi(foo+8)
+  // Lo:   addi vreg2, vreg1, %lo(foo)  --->  lw vreg3, lo(foo+8)(vreg1)
+  // Tail: lw vreg3, 8(vreg2)
+  //
+  // 2. (medany pattern):
+  // Hi: 1:auipc vreg1, %pcrel_hi(s)         ---> auipc vreg1, %pcrel_hi(foo+8)
+  // Lo:   addi  vreg2, vreg1, %pcrel_lo(1b) ---> lw vreg3, %pcrel_lo(1b)(vreg1)
+  // Tail: lw vreg3, 8(vreg2)
 
   Optional<int64_t> CommonOffset;
   for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) {
     switch (UseMI.getOpcode()) {
     default:
       LLVM_DEBUG(dbgs() << "Not a load or store instruction: " << UseMI);
       return false;
     case RISCV::LB:
for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) {
     case RISCV::SH:
     case RISCV::SW:
     case RISCV::SD:
     case RISCV::FSH:
     case RISCV::FSW:
     case RISCV::FSD: {
       if (UseMI.getOperand(1).isFI())
         return false;
-      // Register defined by LoADDI should not be the value register.
+      // Register defined by Lo should not be the value register.
       if (DestReg == UseMI.getOperand(0).getReg())
         return false;
       assert(DestReg == UseMI.getOperand(1).getReg() &&
              "Expected base address use");
       // All load/store instructions must use the same offset.
       int64_t Offset = UseMI.getOperand(2).getImm();
       if (CommonOffset && Offset != CommonOffset)
         return false;
       CommonOffset = Offset;
     }
     }
   }
 
   // We found a common offset.
   // Update the offsets in global address lowering.
-  HiLUI.getOperand(1).setOffset(*CommonOffset);
-  MachineOperand &ImmOp = LoADDI.getOperand(2);
+  Hi.getOperand(1).setOffset(*CommonOffset);
+  MachineOperand &ImmOp = Lo.getOperand(2);
+  if (Hi.getOpcode() != RISCV::AUIPC)
     ImmOp.setOffset(*CommonOffset);
 
   // Update the immediate in the load/store instructions to add the offset.
   for (MachineInstr &UseMI :
        llvm::make_early_inc_range(MRI->use_instructions(DestReg))) {
     UseMI.removeOperand(2);
     UseMI.addOperand(ImmOp);
     // Update the base reg in the Tail instruction to feed from LUI.
-    // Output of HiLUI is only used in LoADDI, no need to use
-    // MRI->replaceRegWith().
-    UseMI.getOperand(1).setReg(HiLUI.getOperand(0).getReg());
+    // Output of Hi is only used in Lo, no need to use MRI->replaceRegWith().
+    UseMI.getOperand(1).setReg(Hi.getOperand(0).getReg());
   }
 
-  DeadInstrs.insert(&LoADDI);
+  DeadInstrs.insert(&Lo);
   return true;
 }
 
 bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) {
   if (skipFunction(Fn.getFunction()))
     return false;
 
   ST = &Fn.getSubtarget<RISCVSubtarget>();
 
   bool MadeChange = false;
   DeadInstrs.clear();
   MRI = &Fn.getRegInfo();
   for (MachineBasicBlock &MBB : Fn) {
     LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
-    for (MachineInstr &HiLUI : MBB) {
-      MachineInstr *LoADDI = nullptr;
-      if (!detectLuiAddiGlobal(HiLUI, LoADDI))
+    for (MachineInstr &Hi : MBB) {
+      MachineInstr *Lo = nullptr;
+      if (!detectFoldable(Hi, Lo))
         continue;
       LLVM_DEBUG(dbgs() << "  Found lowered global address: "
-                        << *LoADDI->getOperand(2).getGlobal() << "\n");
-      MadeChange |= detectAndFoldOffset(HiLUI, *LoADDI);
+                        << *Hi.getOperand(2).getGlobal() << "\n");
+      MadeChange |= detectAndFoldOffset(Hi, *Lo);
     }
   }
   // Delete dead instructions.
   for (auto *MI : DeadInstrs)
     MI->eraseFromParent();
   return MadeChange;
 }
 
 /// Returns an instance of the Merge Base Offset Optimization pass.
 FunctionPass *llvm::createRISCVMergeBaseOffsetOptPass() {
   return new RISCVMergeBaseOffsetOpt();
 }

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

 ; RV32I-SMALL-NEXT:    lui a0, %hi(G)
 ; RV32I-SMALL-NEXT:    lw a0, %lo(G)(a0)
 ; RV32I-SMALL-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: lower_global:
 ; RV32I-MEDIUM:       # %bb.0:
 ; RV32I-MEDIUM-NEXT:  .Lpcrel_hi0:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(G)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
-; RV32I-MEDIUM-NEXT:    lw a0, 0(a0)
+; RV32I-MEDIUM-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi0)(a0)
 ; RV32I-MEDIUM-NEXT:    ret
   %1 = load volatile i32, i32* @G
   ret i32 %1
 }
 
 ; Check lowering of blockaddresses
 
 @addr = global i8* null
 
 define void @lower_blockaddress() nounwind {
 ; RV32I-SMALL-LABEL: lower_blockaddress:
 ; RV32I-SMALL:       # %bb.0:
 ; RV32I-SMALL-NEXT:    lui a0, %hi(addr)
 ; RV32I-SMALL-NEXT:    li a1, 1
 ; RV32I-SMALL-NEXT:    sw a1, %lo(addr)(a0)
 ; RV32I-SMALL-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: lower_blockaddress:
 ; RV32I-MEDIUM:       # %bb.0:
 ; RV32I-MEDIUM-NEXT:  .Lpcrel_hi1:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(addr)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
 ; RV32I-MEDIUM-NEXT:    li a1, 1
-; RV32I-MEDIUM-NEXT:    sw a1, 0(a0)
+; RV32I-MEDIUM-NEXT:    sw a1, %pcrel_lo(.Lpcrel_hi1)(a0)
 ; RV32I-MEDIUM-NEXT:    ret
   store volatile i8* blockaddress(@lower_blockaddress, %block), i8** @addr
   ret void
 
 block:
   unreachable
 }
 

llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll

 ; RV64I-NEXT:    lui a0, %hi(g_0)
 ; RV64I-NEXT:    ld a0, %lo(g_0)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_g_0:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi0:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_0)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
-; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   %0 = load i64, i64* @g_0
   ret i64 %0
 }
 
 define dso_local i64 @load_g_1() nounwind {
 ; RV32I-LABEL: load_g_1:

 ; RV64I-NEXT:    lui a0, %hi(g_1)
 ; RV64I-NEXT:    ld a0, %lo(g_1)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_g_1:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi1:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_1)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
-; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi1)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   %0 = load i64, i64* @g_1
   ret i64 %0
 }
 
 define dso_local i64 @load_g_2() nounwind {
 ; RV32I-LABEL: load_g_2:

 ; RV64I-NEXT:    lui a0, %hi(g_2)
 ; RV64I-NEXT:    ld a0, %lo(g_2)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_g_2:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi2:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_2)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi2)
-; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi2)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   %0 = load i64, i64* @g_2
   ret i64 %0
 }
 
 define dso_local i64 @load_g_4() nounwind {
 ; RV32I-LABEL: load_g_4:

 ; RV64I-NEXT:    lui a0, %hi(g_4)
 ; RV64I-NEXT:    ld a0, %lo(g_4)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_g_4:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi3:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_4)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi3)
-; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi3)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   %0 = load i64, i64* @g_4
   ret i64 %0
 }
 
 define dso_local i64 @load_g_8() nounwind {
 ; RV32I-LABEL: load_g_8:

 ; RV64I-NEXT:    lui a0, %hi(g_8)
 ; RV64I-NEXT:    ld a0, %lo(g_8)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_g_8:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi4:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_8)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi4)
-; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi4)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   %0 = load i64, i64* @g_8
   ret i64 %0
 }
 
 define dso_local i64 @load_g_16() nounwind {
 ; RV32I-LABEL: load_g_16:

 ; RV64I-NEXT:    lui a0, %hi(g_16)
 ; RV64I-NEXT:    ld a0, %lo(g_16)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_g_16:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi5:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_16)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi5)
-; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi5)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   %0 = load i64, i64* @g_16
   ret i64 %0
 }
 
 define dso_local void @store_g_4() nounwind {
 ; RV32I-LABEL: store_g_4:

 ; RV64I-NEXT:    lui a0, %hi(g_4)
 ; RV64I-NEXT:    sd zero, %lo(g_4)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: store_g_4:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi6:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_4)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi6)
-; RV64I-MEDIUM-NEXT:    sd zero, 0(a0)
+; RV64I-MEDIUM-NEXT:    sd zero, %pcrel_lo(.Lpcrel_hi6)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
    store i64 0, i64* @g_4
    ret void
 }
 
 define dso_local void @store_g_8() nounwind {
 ; RV32I-LABEL: store_g_8:

 ; RV64I-NEXT:    lui a0, %hi(g_8)
 ; RV64I-NEXT:    sd zero, %lo(g_8)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: store_g_8:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi7:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_8)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi7)
-; RV64I-MEDIUM-NEXT:    sd zero, 0(a0)
+; RV64I-MEDIUM-NEXT:    sd zero, %pcrel_lo(.Lpcrel_hi7)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
    store i64 0, i64* @g_8
    ret void
 }
 
 ; Check if we can fold ADDI into the offset of store instructions,
 ; when store instructions is the root node in DAG.
 
 @g_4_i32 = global i32 0, align 4
 
 define dso_local void @inc_g_i32() nounwind {
 ; RV32I-LABEL: inc_g_i32:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(g_4_i32)
 ; RV32I-NEXT:    lw a1, %lo(g_4_i32)(a0)
 ; RV32I-NEXT:    addi a1, a1, 1
 ; RV32I-NEXT:    sw a1, %lo(g_4_i32)(a0)
 ; RV32I-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: inc_g_i32:
 ; RV32I-MEDIUM:       # %bb.0: # %entry
 ; RV32I-MEDIUM-NEXT:  .Lpcrel_hi8:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_4_i32)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi8)
-; RV32I-MEDIUM-NEXT:    lw a1, 0(a0)
+; RV32I-MEDIUM-NEXT:    lw a1, %pcrel_lo(.Lpcrel_hi8)(a0)
 ; RV32I-MEDIUM-NEXT:    addi a1, a1, 1
-; RV32I-MEDIUM-NEXT:    sw a1, 0(a0)
+; RV32I-MEDIUM-NEXT:    sw a1, %pcrel_lo(.Lpcrel_hi8)(a0)
 ; RV32I-MEDIUM-NEXT:    ret
 ;
 ; RV64I-LABEL: inc_g_i32:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    lui a0, %hi(g_4_i32)
 ; RV64I-NEXT:    lw a1, %lo(g_4_i32)(a0)
 ; RV64I-NEXT:    addiw a1, a1, 1
 ; RV64I-NEXT:    sw a1, %lo(g_4_i32)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: inc_g_i32:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi8:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g_4_i32)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi8)
-; RV64I-MEDIUM-NEXT:    lw a1, 0(a0)
+; RV64I-MEDIUM-NEXT:    lw a1, %pcrel_lo(.Lpcrel_hi8)(a0)
 ; RV64I-MEDIUM-NEXT:    addiw a1, a1, 1
-; RV64I-MEDIUM-NEXT:    sw a1, 0(a0)
+; RV64I-MEDIUM-NEXT:    sw a1, %pcrel_lo(.Lpcrel_hi8)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   %0 = load i32, i32* @g_4_i32
   %inc = add i32 %0, 1
   store i32 %inc, i32* @g_4_i32
   br label %if.end
 
 if.end:

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, %hi(ga+4)
 ; RV32I-NEXT:    lw a0, %lo(ga+4)(a0)
 ; RV32I-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: load_ga:
 ; RV32I-MEDIUM:       # %bb.0:
 ; RV32I-MEDIUM-NEXT:  .Lpcrel_hi9:
-; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi9)
-; RV32I-MEDIUM-NEXT:    lw a0, 4(a0)
+; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga+4)
+; RV32I-MEDIUM-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi9)(a0)
 ; RV32I-MEDIUM-NEXT:    ret
 ;
 ; RV64I-LABEL: load_ga:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, %hi(ga+4)
 ; RV64I-NEXT:    lw a0, %lo(ga+4)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_ga:
 ; RV64I-MEDIUM:       # %bb.0:
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi9:
-; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi9)
-; RV64I-MEDIUM-NEXT:    lw a0, 4(a0)
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga+4)
+; RV64I-MEDIUM-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi9)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
   %1 = load i32, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @ga, i32 0, i32 1), align 4
   ret i32 %1
 }
 
 ; Check for folds in accesses to the second element of an i64 array.
 
 @ga_8 = dso_local local_unnamed_addr global [2 x i64] zeroinitializer, align 8

 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    lui a0, %hi(ga_8+8)
 ; RV64I-NEXT:    ld a0, %lo(ga_8+8)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_ga_8:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi10:
-; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga_8)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi10)
-; RV64I-MEDIUM-NEXT:    ld a0, 8(a0)
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga_8+8)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi10)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   %0 = load i64, i64* getelementptr inbounds ([2 x i64], [2 x i64]* @ga_8, i32 0, i32 1)
   ret i64 %0
 }
 
 define dso_local i64 @load_ga_16() nounwind {
 ; RV32I-LABEL: load_ga_16:

 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    lui a0, %hi(ga_16)
 ; RV64I-NEXT:    ld a0, %lo(ga_16+8)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_ga_16:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi11:
-; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga_16)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi11)
-; RV64I-MEDIUM-NEXT:    ld a0, 8(a0)
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga_16+8)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi11)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   %0 = load i64, i64* getelementptr inbounds ([2 x i64], [2 x i64]* @ga_16, i32 0, i32 1)
   ret i64 %0
 }
 
 ; Check for folds in accesses to thread-local variables.
 

llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV32I %s
 ; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV64I %s
 
 ; Verifies that MachineLICM can hoist address generation pseudos out of loops.
 
 @l = protected global i32 0, align 4
 
 define void @test_lla(i32 signext %n) {
 ; RV32I-LABEL: test_lla:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:  .Lpcrel_hi0:
 ; RV32I-NEXT:    auipc a2, %pcrel_hi(l)
-; RV32I-NEXT:    addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
 ; RV32I-NEXT:  .LBB0_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    lw a3, 0(a2)
+; RV32I-NEXT:    lw a3, %pcrel_lo(.Lpcrel_hi0)(a2)
 ; RV32I-NEXT:    addi a1, a1, 1
 ; RV32I-NEXT:    blt a1, a0, .LBB0_1
 ; RV32I-NEXT:  # %bb.2: # %ret
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_lla:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:  .Lpcrel_hi0:
 ; RV64I-NEXT:    auipc a2, %pcrel_hi(l)
-; RV64I-NEXT:    addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
 ; RV64I-NEXT:  .LBB0_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    lw a3, 0(a2)
+; RV64I-NEXT:    lw a3, %pcrel_lo(.Lpcrel_hi0)(a2)
 ; RV64I-NEXT:    addiw a1, a1, 1
 ; RV64I-NEXT:    blt a1, a0, .LBB0_1
 ; RV64I-NEXT:  # %bb.2: # %ret
 ; RV64I-NEXT:    ret
 entry:
   br label %loop
 
 loop: