This is an archive of the discontinued LLVM Phabricator instance.

[AArch64] Fix AArch64TargetParser.def to match AArch64.td.
ClosedPublic

Authored by efriedma on Mar 22 2022, 5:06 PM.

Details

Summary

Currently, we have two different lists of features each CPU supports... and those lists aren't consistent. This patch assumes AArch64.td is right, and tries to fix AArch64TargetParser to match.

That said... I really have no idea which feature list is actually right. I don't have these CPUs, and I can't find documentation. So I'd appreciate input on whether my "corrections" are actually correct.

Probably we should try to unify the two lists at some point, but synchronizing them seems like a prerequisite to that anyway.

Diff Detail

Event Timeline

efriedma created this revision.Mar 22 2022, 5:06 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 22 2022, 5:06 PM
efriedma requested review of this revision.Mar 22 2022, 5:06 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 22 2022, 5:06 PM
ab accepted this revision.Mar 23 2022, 1:04 PM
ab added a subscriber: pcc.

The apple-* bits LGTM, thanks! @pcc caught a couple more in rGa8a3a43792, I still need to go over those as well

This revision is now accepted and ready to land.Mar 23 2022, 1:04 PM
tmatheson accepted this revision.Mar 28 2022, 4:53 AM

LGTM, just some comments/notes on what changes for others looking at this.

llvm/include/llvm/Support/AArch64TargetParser.def
193

Adds +spe. The processor supports it.

197

Adds +spe,+flagm,+pauth,+fp16fml to target features. Discussion on D93022 seems to support them.

210

Adds +spe (same for x1)

232

Adds +spe,+rand,+i8mm

+fp16fml is not required because +fp16 implies +fp16fml for v8.4 (D50229)

234

RCPC/RAS implied by 8.4