- User Since
- Feb 21 2020, 8:57 AM (15 w, 22 h)
Tue, May 19
Thanks, Just sent Tom an email.
I have a question here. Our customers need the TX3 support urgently, they asked me to put this TX3 support to LLVM 10.0.1 and if there is 9.0.2 release planned, they also need it there.
Wed, May 13
Joel will help me to commit it. Thanks,
Tue, May 12
Correct the wrong version of llvm/unittests/Support/TargetParserTest.cpp which causes the test failure.
- in clang/test/Driver/aarch64-cpus.c, expanded the the same tests for thunderx2t99 to thunderx3t110
- in llvm/unittest/Support/TargetParserTest.cpp, fix the missing target features
Sun, May 10
fix a typo, thunderx3t110, not thunderx3t100 in TargetParserTest.cpp
Fix the format issue in TargetParserTest.cpp
- Added the predicates as suggested
- brought back the TargetParserTest.cpp which was missed last time
Fri, May 8
Sure I will add Joel's suggestion and other fixes later.
I think I made all the changes mentioned in the feedbacks. Please take sometime to review the current version. We are eager to get the first thunderx3t110 checked in.
Removed the PA related instructions from the .md file as suggested.
Thu, May 7
I will put the "PAUnsupported" predicate later once this got passed.
I put every people's feedbacks into the code and upload them here.
May 6 2020
I can confirm your findings, basically as long as we comment out the new instructions, it will be OK to build.
I tried to set CompleteModel = 0 on line 25 in file llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
May 1 2020
fixed all the feedback suggestions. Thanks,
Apr 28 2020
Remove non-official target options. We now only support -mcpu=thunderx3t110
Apr 24 2020
Apr 23 2020
An other miss the format. fixed
Fix a format issue.
fix a format issus.
Fix a few format problems.
Resubmit as the previous one was rejected by test plan changes
Merged with the current code.
Apr 22 2020
Apr 15 2020
Fix the precheck errors.
The newly added two files were not accepted by the pre-merge check. Re worked on the diff file and uploaded it now.
Patch the function interface changes in other targets to avoid build failure for ARM, Hexagon, PowerPC, SystemZ and X86.
Apr 14 2020
Mar 31 2020
fix the warning.
minor format change
fix clang-format issue.
Mar 30 2020
Move the creation of the Tbl1 instruction's mask from LLVM generic code to AArch64 target specific code.
Mar 18 2020
Sanjay Patel :The title of this patch confused me. This is not adding a pass; it is extending existing passes.
WZ: Agree. It is not a new LLVM pass. The work is piggy backed on an existing pass. I will change the title.
On 05/03/2020 00:35, Wei Zhao wrote:
- Why not do this work in ISel?
In LLVM IR, we have shufflevector In LLVM DAG, we have vector_shuffle
In ISel, the normal process to translate LLVM IR shufflevector to TBLn instruction is to translate it first to DAG node vector_shuffle, and then in the DAG Legalize() to lower it to machine specific instructions like TBLn.
There is a very strict and deeply rooted convention or requirement on how to translate LLVM IR shufflevector -> DAG node vector_shuffle.
In the following example: %v3 = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> ; yields <8 x i8>
%v3 and %v1, %v2 have to be the same type.
If not, ISel won't translate it to DAG node vector_shuffle and later it won't be lowered into a TBLn instruction. Instead, the ISel(it has at most 9 steps in total) will lower it into a sequence of extract/insert instructions to form a new vector, as in the above example, %v3 will be generated by a sequence of extract/insert instructions.
Because ISel is coded like this, it is very hard to break this rule and put the handling of irregular (mismatched type) shufflevector in the ISel stage.
To my understanding, the type match requirement on shuffle vector can be dated back to the early days of LLVM when it was used to generate code for Motorola Altivec.
Because of all these, we decided to following the example of Ldn/Stn generation in InterleavedAccessPass(), just directly generate Tbl1 instruction from LLVM IR before entering ISel.
Mar 9 2020
Fix a minor comment.
Mar 4 2020
Fix clang-tidy warning and one clang-format error.
yet another missing format error.
This upload changed the clang-format problems.