[Disassember][NFCI] Use strong type for instruction decoder

[maksfb]

Summary

All LLVM backends use MCDisassembler as a base class for their
instruction decoders. Use "const MCDisassembler *" for the decoder
instead of "const void *". Remove unnecessary static casts.

[foad]

Remove unnecessary static casts.

Can you explain which ones are removed? In the AMDGPU backend it looks like they are all still required, to cast from MCDisassembler * to AMDGPUDisassembler *.

No objection to the patch btw.

[maksfb]

In D122245#3401920, @foad wrote:

Can you explain which ones are removed? In the AMDGPU backend it looks like they are all still required, to cast from MCDisassembler * to AMDGPUDisassembler *.

Right, I removed casts where no further code changes were required. E.g., if the pointer was used to call an AMDGPUDisassembler-specific function, we still need to cast. It's possible I've missed some cases. Please let me know.

[skan]

In D122245#3403187, @maksfb wrote:

In D122245#3401920, @foad wrote:

Can you explain which ones are removed? In the AMDGPU backend it looks like they are all still required, to cast from MCDisassembler * to AMDGPUDisassembler *.

Right, I removed casts where no further code changes were required. E.g., if the pointer was used to call an AMDGPUDisassembler-specific function, we still need to cast. It's possible I've missed some cases. Please let me know.

I think most of the removed casts are const void *->const MCDisassembler * b/c we use MCDisassembler as parameters explicitly in this patch , which seems reasonable to me. From the logs, I believe FixedLenDecoderEmitter.cpp defined the function prototype first, and then all the targets had to follow it.

[skan]

Added @grosbach as a reviewer, who defined the interfaces of decodeToMCInst and decodeInstruction in https://reviews.llvm.org/rGecaef49f59bb4e414f95d89b7c6b35eb9adad314 in 2012.
After ten years, I believe we don't need such generic interface now.

LGTM generally.

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

 
 #define DEBUG_TYPE "aarch64-disassembler"
 
 // Pull DecodeStatus and its enum values into the global namespace.
 using DecodeStatus = MCDisassembler::DecodeStatus;
 
 // Forward declare these because the autogenerated code will reference them.
 // Definitions are further down.
-static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
-                                              unsigned RegNo, uint64_t Address,
-                                              const void *Decoder);
-static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
-                                                 unsigned RegNo,
+static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder);
+static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t Address,
-                                                 const void *Decoder);
+                                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder);
-static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
-                                             uint64_t Address,
-                                             const void *Decoder);
+                                            const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
-static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst,
-                                                    unsigned RegNo,
-                                                    uint64_t Address,
-                                                    const void *Decoder);
-static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
-                                               unsigned RegNo, uint64_t Address,
-                                               const void *Decoder);
-static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst,
-                                                              unsigned RegNo,
-                                                              uint64_t Address,
-                                                              const void *Decoder);
+                                             const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                                const MCDisassembler *Decoder);
+static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
-static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
-                                               unsigned RegNo, uint64_t Address,
-                                               const void *Decoder);
+                                             const MCDisassembler *Decoder);
+static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
                                           uint64_t Address,
-                                          const void *Decoder);
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
                                           uint64_t Address,
-                                          const void *Decoder);
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 template <unsigned NumBitsForTile>
 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
-                                     uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst,
-                                                      unsigned RegMask,
-                                                      uint64_t Address,
-                                                      const void *Decoder);
+                                     const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
+                                  uint64_t Address,
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
-                                       uint64_t Address, const void *Decoder);
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder);
 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
-                                            uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
-                                            uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
-                                                   uint64_t Address,
-                                                   const void *Decoder);
+                                            const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
+                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
                                              uint64_t Address,
-                                             const void *Decoder);
-static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
-                                                  uint64_t Address,
-                                                  const void *Decoder);
+                                             const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
+                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Address,
-                                                const void *Decoder);
-static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
-                                                   uint64_t Address,
-                                                   const void *Decoder);
+                                                const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
+                               const MCDisassembler *Decoder);
 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Address,
-                                                const void *Decoder);
+                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Address,
-                                                const void *Decoder);
+                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Address,
-                                                const void *Decoder);
+                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
-                                         uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
-                                         uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
-                                              uint64_t Address,
-                                              const void *Decoder);
-static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
-                                                  uint64_t Address,
-                                                  const void *Decoder);
+                                         const MCDisassembler *Decoder);
+static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
+                                              const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
+                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder);
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
                                                uint64_t Addr,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder);
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
                                                uint64_t Addr,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder);
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
                                                uint64_t Addr,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
-                                        uint64_t Addr, const void *Decoder);
+                                        uint64_t Addr,
+                                        const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder);
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder);
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder);
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
-                                        uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
-                                                      unsigned RegNo,
-                                                      uint64_t Addr,
-                                                      const void *Decoder);
-static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
-                                                      unsigned RegNo,
-                                                      uint64_t Addr,
-                                                      const void *Decoder);
-static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn,
-                                                   uint64_t Address,
-                                                   const void *Decoder);
+                                        const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
+                               const MCDisassembler *Decoder);
 template <int Bits>
 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
-                               const void *Decoder);
+                               const MCDisassembler *Decoder);
 template <int ElementWidth>
-static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
-                                     uint64_t Addr, const void *Decoder);
+static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
+                                     const MCDisassembler *Decoder);
 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
-                                       uint64_t Addr, const void *Decoder);
+                                       uint64_t Addr,
+                                       const MCDisassembler *Decoder);
 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Addr,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Addr,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 
 static bool Check(DecodeStatus &Out, DecodeStatus In) {
   switch (In) {
     case MCDisassembler::Success:
       // Out stays the same.
       return true;
     case MCDisassembler::SoftFail:
       Out = In;
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
   TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
                                          createAArch64Disassembler);
   TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
                                        createAArch64ExternalSymbolizer);
 }
 
 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Addr,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
-static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                 uint64_t Addr,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
+                             const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return Fail;
   return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
 }
 
 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Addr,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Addr,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Addr,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Addr,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
-static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                   uint64_t Addr,
-                                                   const void *Decoder) {
+static DecodeStatus
+DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
+                               const MCDisassembler *Decoder) {
   if (RegNo > 30)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
           RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Addr,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
-static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst,
-                                                    unsigned RegNo,
-                                                    uint64_t Address,
-                                                    const void *Decoder) {
+static DecodeStatus
+DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                                const MCDisassembler *Decoder) {
   if (RegNo > 22)
     return Fail;
   if (RegNo & 1)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
           RegNo >> 1);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Addr,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
-static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst,
-                                                              unsigned RegNo,
-                                                              uint64_t Addr,
-                                                              const void *Decoder) {
+static DecodeStatus
+DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
+                                          const MCDisassembler *Decoder) {
   if (RegNo > 3)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
           .getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Addr,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Addr,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void* Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return Fail;
   return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return Fail;
   return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void* Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void* Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void* Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
-static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst,
-                                                      unsigned RegMask,
-                                                      uint64_t Address,
-                                                      const void *Decoder) {
+static DecodeStatus
+DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
+                                  const MCDisassembler *Decoder) {
   if (RegMask > 0xFF)
     return Fail;
   Inst.addOperand(MCOperand::createImm(RegMask));
   return Success;
 }
 
 static const SmallVector<SmallVector<unsigned, 16>, 5>
     MatrixZATileDecoderTable = {
         {AArch64::ZAB0},
         {AArch64::ZAH0, AArch64::ZAH1},
         {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
         {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3,
          AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
         {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3,
          AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7,
          AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11,
          AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}};
 
 template <unsigned NumBitsForTile>
 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
-                                     uint64_t Address, const void *Decoder) {
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   unsigned LastReg = (1 << NumBitsForTile) - 1;
   if (RegNo > LastReg)
     return Fail;
   Inst.addOperand(
       MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
   return Success;
 }
 
 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                           uint64_t Addr, const void *Decoder) {
+                                           uint64_t Addr,
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Addr,
-                                              const void* Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return Fail;
 
   // Just reuse the PPR decode table
   return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
 }
 
 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
-                                          uint64_t Addr, const void *Decoder) {
+                                          uint64_t Addr,
+                                          const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
-                                           uint64_t Addr, const void *Decoder) {
+                                           uint64_t Addr,
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Addr,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
-                                          uint64_t Addr, const void *Decoder) {
+                                          uint64_t Addr,
+                                          const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
-                                           uint64_t Addr, const void *Decoder) {
+                                           uint64_t Addr,
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Addr,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
                                                uint64_t Addr,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   // scale{5} is asserted as 1 in tblgen.
   Imm |= 0x20;
   Inst.addOperand(MCOperand::createImm(64 - Imm));
   return Success;
 }
 
 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
                                                uint64_t Addr,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(64 - Imm));
   return Success;
 }
 
 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
-                                       uint64_t Addr, const void *Decoder) {
+                                       uint64_t Addr,
+                                       const MCDisassembler *Decoder) {
   int64_t ImmVal = Imm;
-  const AArch64Disassembler *Dis =
-      static_cast<const AArch64Disassembler *>(Decoder);
 
   // Sign-extend 19-bit immediate.
   if (ImmVal & (1 << (19 - 1)))
     ImmVal |= ~((1LL << 19) - 1);
 
-  if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal *  4, Addr,
-                                     Inst.getOpcode() != AArch64::LDRXl, 0, 4))
+  if (!Decoder->tryAddingSymbolicOperand(
+          Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 4))
     Inst.addOperand(MCOperand::createImm(ImmVal));
   return Success;
 }
 
 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm((Imm  >> 1) & 1));
   Inst.addOperand(MCOperand::createImm(Imm & 1));
   return Success;
 }
 
 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(Imm));
 
   // Every system register in the encoding space is valid with the syntax
   // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
   return Success;
 }
 
 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(Imm));
 
   return Success;
 }
 
 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   // This decoder exists to add the dummy Lane operand to the MCInst, which must
   // be 1 in assembly but has no other real manifestation.
   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 
   if (IsToVec) {
     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);

 
 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
                                        unsigned Add) {
   Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
   return Success;
 }
 
 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder) {
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder) {
   return DecodeVecShiftRImm(Inst, Imm, 64);
 }
 
 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
                                                uint64_t Addr,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
 }
 
 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder) {
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder) {
   return DecodeVecShiftRImm(Inst, Imm, 32);
 }
 
 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
                                                uint64_t Addr,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
 }
 
 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder) {
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder) {
   return DecodeVecShiftRImm(Inst, Imm, 16);
 }
 
 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
                                                uint64_t Addr,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
 }
 
 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
-                                        uint64_t Addr, const void *Decoder) {
+                                        uint64_t Addr,
+                                        const MCDisassembler *Decoder) {
   return DecodeVecShiftRImm(Inst, Imm, 8);
 }
 
 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder) {
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder) {
   return DecodeVecShiftLImm(Inst, Imm, 64);
 }
 
 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder) {
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder) {
   return DecodeVecShiftLImm(Inst, Imm, 32);
 }
 
 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
-                                         uint64_t Addr, const void *Decoder) {
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder) {
   return DecodeVecShiftLImm(Inst, Imm, 16);
 }
 
 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
-                                        uint64_t Addr, const void *Decoder) {
+                                        uint64_t Addr,
+                                        const MCDisassembler *Decoder) {
   return DecodeVecShiftLImm(Inst, Imm, 8);
 }
 
-static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
-                                                   uint64_t Addr,
-                                                   const void *Decoder) {
+static DecodeStatus
+DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
+                               const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   unsigned Rm = fieldFromInstruction(insn, 16, 5);
   unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
   unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
   unsigned shift = (shiftHi << 6) | shiftLo;
   switch (Inst.getOpcode()) {
   default:
DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
   }
 
   Inst.addOperand(MCOperand::createImm(shift));
   return Success;
 }
 
 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
                                              uint64_t Addr,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned imm = fieldFromInstruction(insn, 5, 16);
   unsigned shift = fieldFromInstruction(insn, 21, 2);
   shift <<= 4;
   switch (Inst.getOpcode()) {
   default:
     return Fail;
   case AArch64::MOVZWi:
if (Inst.getOpcode() == AArch64::MOVKWi ||
       Inst.getOpcode() == AArch64::MOVKXi)
     Inst.addOperand(Inst.getOperand(0));
 
   Inst.addOperand(MCOperand::createImm(imm));
   Inst.addOperand(MCOperand::createImm(shift));
   return Success;
 }
 
-static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
-                                                  uint64_t Addr,
-                                                  const void *Decoder) {
+static DecodeStatus
+DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
+                              const MCDisassembler *Decoder) {
   unsigned Rt = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   unsigned offset = fieldFromInstruction(insn, 10, 12);
-  const AArch64Disassembler *Dis =
-      static_cast<const AArch64Disassembler *>(Decoder);
 
   switch (Inst.getOpcode()) {
   default:
     return Fail;
   case AArch64::PRFMui:
     // Rt is an immediate in prefetch.
     Inst.addOperand(MCOperand::createImm(Rt));
     break;
case AArch64::STRHui:
     break;
   case AArch64::LDRBui:
   case AArch64::STRBui:
     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
     break;
   }
 
   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
-  if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
+  if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
     Inst.addOperand(MCOperand::createImm(offset));
   return Success;
 }
 
 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Addr,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   unsigned Rt = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   int64_t offset = fieldFromInstruction(insn, 12, 9);
 
   // offset is a 9-bit signed immediate, so sign extend it to
   // fill the unsigned.
   if (offset & (1 << (9 - 1)))
     offset |= ~((1LL << 9) - 1);
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
 
   // Cannot write back to a transfer register (but xzr != sp).
   if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
     return SoftFail;
 
   return Success;
 }
 
-static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
-                                                   uint64_t Addr,
-                                                   const void *Decoder) {
+static DecodeStatus
+DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
+                               const MCDisassembler *Decoder) {
   unsigned Rt = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
   unsigned Rs = fieldFromInstruction(insn, 16, 5);
 
   unsigned Opcode = Inst.getOpcode();
   switch (Opcode) {
   default:
if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
       Rt == Rt2)
     return SoftFail;
 
   return Success;
 }
 
 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Addr,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   unsigned Rt = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
   int64_t offset = fieldFromInstruction(insn, 15, 7);
   bool IsLoad = fieldFromInstruction(insn, 22, 1);
 
   // offset is a 7-bit signed immediate, so sign extend it to
   // fill the unsigned.
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
   if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
     return SoftFail;
 
   return Success;
 }
 
 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Addr,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   unsigned Rt = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
                     fieldFromInstruction(insn, 12, 9);
   unsigned writeback = fieldFromInstruction(insn, 11, 1);
 
   switch (Inst.getOpcode()) {
   default:
if (writeback && Rt == Rn && Rn != 31) {
     return SoftFail;
   }
 
   return Success;
 }
 
 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Addr,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   unsigned Rm = fieldFromInstruction(insn, 16, 5);
   unsigned extend = fieldFromInstruction(insn, 10, 6);
 
   unsigned shift = extend & 0x7;
   if (shift > 4)
     return Fail;
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
   }
 
   Inst.addOperand(MCOperand::createImm(extend));
   return Success;
 }
 
 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Addr,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
   unsigned imm;
 
   if (Datasize) {
     if (Inst.getOpcode() == AArch64::ANDSXri)
       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
       return Fail;
   }
   Inst.addOperand(MCOperand::createImm(imm));
   return Success;
 }
 
 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
                                             uint64_t Addr,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned cmode = fieldFromInstruction(insn, 12, 4);
   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
   imm |= fieldFromInstruction(insn, 5, 5);
 
   if (Inst.getOpcode() == AArch64::MOVID)
     DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
   else
case AArch64::MVNIv4s_msl:
     break;
   }
 
   return Success;
 }
 
 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Addr,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned cmode = fieldFromInstruction(insn, 12, 4);
   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
   imm |= fieldFromInstruction(insn, 5, 5);
 
   // Tied operands added twice.
   DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
   DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
 
   Inst.addOperand(MCOperand::createImm(imm));
   Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
 
   return Success;
 }
 
 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
-                                         uint64_t Addr, const void *Decoder) {
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
   imm |= fieldFromInstruction(insn, 29, 2);
-  const AArch64Disassembler *Dis =
-      static_cast<const AArch64Disassembler *>(Decoder);
 
   // Sign-extend the 21-bit immediate.
   if (imm & (1 << (21 - 1)))
     imm |= ~((1LL << 21) - 1);
 
   DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
-  if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
+  if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
     Inst.addOperand(MCOperand::createImm(imm));
 
   return Success;
 }
 
 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
-                                         uint64_t Addr, const void *Decoder) {
+                                         uint64_t Addr,
+                                         const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   unsigned Imm = fieldFromInstruction(insn, 10, 14);
   unsigned S = fieldFromInstruction(insn, 29, 1);
   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
 
   unsigned ShifterVal = (Imm >> 12) & 3;
   unsigned ImmVal = Imm & 0xFFF;
-  const AArch64Disassembler *Dis =
-      static_cast<const AArch64Disassembler *>(Decoder);
 
   if (ShifterVal != 0 && ShifterVal != 1)
     return Fail;
 
   if (Datasize) {
     if (Rd == 31 && !S)
       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
     else
       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
   } else {
     if (Rd == 31 && !S)
       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
     else
       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
   }
 
-  if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
+  if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
     Inst.addOperand(MCOperand::createImm(ImmVal));
   Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
   return Success;
 }
 
 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
                                               uint64_t Addr,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   int64_t imm = fieldFromInstruction(insn, 0, 26);
-  const AArch64Disassembler *Dis =
-      static_cast<const AArch64Disassembler *>(Decoder);
 
   // Sign-extend the 26-bit immediate.
   if (imm & (1 << (26 - 1)))
     imm |= ~((1LL << 26) - 1);
 
-  if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
+  if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
     Inst.addOperand(MCOperand::createImm(imm));
 
   return Success;
 }
 
-static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
-                                                  uint64_t Addr,
-                                                  const void *Decoder) {
+static DecodeStatus
+DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
+                              const MCDisassembler *Decoder) {
   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
   uint64_t crm = fieldFromInstruction(insn, 8, 4);
   uint64_t pstate_field = (op1 << 3) | op2;
 
   switch (pstate_field) {
   case 0x01: // XAFlag
   case 0x02: // AXFlag
     return Fail;
   }
 
   if ((pstate_field == AArch64PState::PAN  ||
        pstate_field == AArch64PState::UAO  ||
        pstate_field == AArch64PState::SSBS) && crm > 1)
     return Fail;
 
   Inst.addOperand(MCOperand::createImm(pstate_field));
   Inst.addOperand(MCOperand::createImm(crm));
 
-  const AArch64Disassembler *Dis =
-      static_cast<const AArch64Disassembler *>(Decoder);
   auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
-  if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
+  if (PState &&
+      PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
     return Success;
   return Fail;
 }
 
 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
-                                        uint64_t Addr, const void *Decoder) {
+                                        uint64_t Addr,
+                                        const MCDisassembler *Decoder) {
   uint64_t Rt = fieldFromInstruction(insn, 0, 5);
   uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
   bit |= fieldFromInstruction(insn, 19, 5);
   int64_t dst = fieldFromInstruction(insn, 5, 14);
-  const AArch64Disassembler *Dis =
-      static_cast<const AArch64Disassembler *>(Decoder);
 
   // Sign-extend 14-bit immediate.
   if (dst & (1 << (14 - 1)))
     dst |= ~((1LL << 14) - 1);
 
   if (fieldFromInstruction(insn, 31, 1) == 0)
     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
   else
     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
   Inst.addOperand(MCOperand::createImm(bit));
-  if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
+  if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
     Inst.addOperand(MCOperand::createImm(dst));
 
   return Success;
 }
 
-static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
-                                                        unsigned RegClassID,
-                                                        unsigned RegNo,
-                                                        uint64_t Addr,
-                                                        const void *Decoder) {
+static DecodeStatus
+DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
+                                    unsigned RegNo, uint64_t Addr,
+                                    const MCDisassembler *Decoder) {
   // Register number must be even (see CASP instruction)
   if (RegNo & 0x1)
     return Fail;
 
   unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
   Inst.addOperand(MCOperand::createReg(Reg));
   return Success;
 }
 
-static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
-                                                      unsigned RegNo,
-                                                      uint64_t Addr,
-                                                      const void *Decoder) {
+static DecodeStatus
+DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
+                                  const MCDisassembler *Decoder) {
   return DecodeGPRSeqPairsClassRegisterClass(Inst,
                                              AArch64::WSeqPairsClassRegClassID,
                                              RegNo, Addr, Decoder);
 }
 
-static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
-                                                      unsigned RegNo,
-                                                      uint64_t Addr,
-                                                      const void *Decoder) {
+static DecodeStatus
+DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
+                                  const MCDisassembler *Decoder) {
   return DecodeGPRSeqPairsClassRegisterClass(Inst,
                                              AArch64::XSeqPairsClassRegClassID,
                                              RegNo, Addr, Decoder);
 }
 
-static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn,
-                                                   uint64_t Addr,
-                                                   const void *Decoder) {
+static DecodeStatus
+DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
+                               const MCDisassembler *Decoder) {
   unsigned Zdn = fieldFromInstruction(insn, 0, 5);
   unsigned imm = fieldFromInstruction(insn, 5, 13);
   if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
     return Fail;
 
   // The same (tied) operand is added twice to the instruction.
   DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
   if (Inst.getOpcode() != AArch64::DUPM_ZI)
     DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
   Inst.addOperand(MCOperand::createImm(imm));
   return Success;
 }
 
 template <int Bits>
 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
-                               const void *Decoder) {
+                               const MCDisassembler *Decoder) {
   if (Imm & ~((1LL << Bits) - 1))
       return Fail;
 
   // Imm is a signed immediate, so sign extend it.
   if (Imm & (1 << (Bits - 1)))
     Imm |= ~((1LL << Bits) - 1);
 
   Inst.addOperand(MCOperand::createImm(Imm));
   return Success;
 }
 
 // Decode 8-bit signed/unsigned immediate for a given element width.
 template <int ElementWidth>
-static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
-                                      uint64_t Addr, const void *Decoder) {
+static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
+                                     const MCDisassembler *Decoder) {
   unsigned Val = (uint8_t)Imm;
   unsigned Shift = (Imm & 0x100) ? 8 : 0;
   if (ElementWidth == 8 && Shift)
     return Fail;
   Inst.addOperand(MCOperand::createImm(Val));
   Inst.addOperand(MCOperand::createImm(Shift));
   return Success;
 }
 
 // Decode uimm4 ranged from 1-16.
 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
-                                       uint64_t Addr, const void *Decoder) {
+                                       uint64_t Addr,
+                                       const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(Imm + 1));
   return Success;
 }
 
 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
     Inst.addOperand(MCOperand::createImm(Imm));
     return Success;
   }
   return Fail;
 }
 
 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Addr,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned Rs = fieldFromInstruction(insn, 16, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 
   // None of the registers may alias: if they do, then the instruction is not
   // merely unpredictable but actually entirely unallocated.
   if (Rd == Rs || Rs == Rn || Rd == Rn)
     return MCDisassembler::Fail;
 
   // All three register operands are written back, so they all appear
   // twice in the operand list, once as outputs and once as inputs.
   if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
       !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
       !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
       !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
       !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
       !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder))
     return MCDisassembler::Fail;
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Addr,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned Rm = fieldFromInstruction(insn, 16, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 
   // None of the registers may alias: if they do, then the instruction is not
   // merely unpredictable but actually entirely unallocated.
   if (Rd == Rm || Rm == Rn || Rd == Rn)
     return MCDisassembler::Fail;

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

if (OpIdx != -1) {
     auto I = MI.begin();
     std::advance(I, OpIdx);
     MI.insert(I, Op);
   }
   return OpIdx;
 }
 
 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
-                                       uint64_t Addr, const void *Decoder) {
+                                       uint64_t Addr,
+                                       const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
 
   // Our branches take a simm16, but we need two extra bits to account for the
   // factor of 4.
   APInt SignedOffset(18, Imm * 4, true);
   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
 
   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
     return MCDisassembler::Success;
   return addOperand(Inst, MCOperand::createImm(Imm));
 }
 
-static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm,
-                                     uint64_t Addr, const void *Decoder) {
+static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr,
+                                     const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   int64_t Offset;
   if (DAsm->isVI()) {         // VI supports 20-bit unsigned offsets.
     Offset = Imm & 0xFFFFF;
   } else {                    // GFX9+ supports 21-bit signed offsets.
     Offset = SignExtend64<21>(Imm);
   }
   return addOperand(Inst, MCOperand::createImm(Offset));
 }
 
-static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
-                                  uint64_t Addr, const void *Decoder) {
+static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr,
+                                  const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeBoolReg(Val));
 }
 
-#define DECODE_OPERAND(StaticDecoderName, DecoderName) \
-static DecodeStatus StaticDecoderName(MCInst &Inst, \
-                                       unsigned Imm, \
-                                       uint64_t /*Addr*/, \
-                                       const void *Decoder) { \
-  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
-  return addOperand(Inst, DAsm->DecoderName(Imm)); \
+#define DECODE_OPERAND(StaticDecoderName, DecoderName)                         \
+  static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm,            \
+                                        uint64_t /*Addr*/,                     \
+                                        const MCDisassembler *Decoder) {       \
+    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
+    return addOperand(Inst, DAsm->DecoderName(Imm));                           \
   }
 
 #define DECODE_OPERAND_REG(RegClass) \
 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
 
 DECODE_OPERAND_REG(VGPR_32)
 DECODE_OPERAND_REG(VRegOrLds_32)
 DECODE_OPERAND_REG(VS_32)
 DECODE_OPERAND_REG(VS_64)

 DECODE_OPERAND_REG(AReg_64)
 DECODE_OPERAND_REG(AReg_128)
 DECODE_OPERAND_REG(AReg_256)
 DECODE_OPERAND_REG(AReg_512)
 DECODE_OPERAND_REG(AReg_1024)
 DECODE_OPERAND_REG(AV_32)
 DECODE_OPERAND_REG(AV_64)
 
-static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
-                                         unsigned Imm,
+static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm,
                                          uint64_t Addr,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
 }
 
-static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
-                                         unsigned Imm,
+static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
-                                         const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
 }
 
-static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst,
-                                           unsigned Imm,
+static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm));
 }
 
-static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
-                                        unsigned Imm,
+static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm,
                                         uint64_t Addr,
-                                        const void *Decoder) {
+                                        const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
 }
 
-static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
-                                        unsigned Imm,
+static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm,
                                         uint64_t Addr,
-                                        const void *Decoder) {
+                                        const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
 }
 
-static DecodeStatus decodeOperand_AReg_64(MCInst &Inst,
-                                          unsigned Imm,
+static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm,
                                           uint64_t Addr,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512));
 }
 
-static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
-                                           unsigned Imm,
+static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
 }
 
-static DecodeStatus decodeOperand_AReg_256(MCInst &Inst,
-                                           unsigned Imm,
+static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512));
 }
 
-static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
-                                           unsigned Imm,
+static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
 }
 
-static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
-                                            unsigned Imm,
+static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm,
                                             uint64_t Addr,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
 }
 
-static DecodeStatus decodeOperand_VReg_64(MCInst &Inst,
-                                          unsigned Imm,
+static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm,
                                           uint64_t Addr,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm));
 }
 
-static DecodeStatus decodeOperand_VReg_128(MCInst &Inst,
-                                           unsigned Imm,
+static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm));
 }
 
-static DecodeStatus decodeOperand_VReg_256(MCInst &Inst,
-                                           unsigned Imm,
+static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm));
 }
 
-static DecodeStatus decodeOperand_VReg_512(MCInst &Inst,
-                                           unsigned Imm,
+static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm));
 }
 
-static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst,
-                                            unsigned Imm,
+static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm,
                                             uint64_t Addr,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm));
 }
 
 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm,
-                                          uint64_t Addr, const void *Decoder) {
+                                          uint64_t Addr,
+                                          const MCDisassembler *Decoder) {
   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
   return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
 }
 
 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm,
-                                          uint64_t Addr, const void *Decoder) {
+                                          uint64_t Addr,
+                                          const MCDisassembler *Decoder) {
   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
   return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
 }
 
-static DecodeStatus decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm,
-                                                 uint64_t Addr,
-                                                 const void *Decoder) {
+static DecodeStatus
+decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr,
+                             const MCDisassembler *Decoder) {
   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
   return addOperand(
       Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true));
 }
 
-static DecodeStatus decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm,
-                                                 uint64_t Addr,
-                                                 const void *Decoder) {
+static DecodeStatus
+decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr,
+                             const MCDisassembler *Decoder) {
   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
   return addOperand(
       Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true));
 }
 
 static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
                           const MCRegisterInfo *MRI) {
   if (OpIdx < 0)
     return false;
 
   const MCOperand &Op = Inst.getOperand(OpIdx);
   if (!Op.isReg())
     return false;
 
   unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
   auto Reg = Sub ? Sub : Op.getReg();
   return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
 }
 
-static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst,
-                                             unsigned Imm,
+static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm,
                                              AMDGPUDisassembler::OpWidthTy Opw,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   if (!DAsm->isGFX90A()) {
     Imm &= 511;
   } else {
     // If atomic has both vdata and vdst their register classes are tied.
     // The bit is decoded along with the vdst, first operand. We need to
     // change register class to AGPR if vdst was AGPR.
     // If a DS instruction has both data0 and data1 their register classes
if (TSFlags & SIInstrFlags::DS) {
       if ((int)Inst.getNumOperands() == Data2Idx &&
           IsAGPROperand(Inst, DataIdx, MRI))
         Imm |= 512;
     }
   }
   return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
 }
 
-static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst,
-                                                 unsigned Imm,
-                                                 uint64_t Addr,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
+                             const MCDisassembler *Decoder) {
   return decodeOperand_AVLdSt_Any(Inst, Imm,
                                   AMDGPUDisassembler::OPW32, Decoder);
 }
 
-static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst,
-                                                 unsigned Imm,
-                                                 uint64_t Addr,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
+                             const MCDisassembler *Decoder) {
   return decodeOperand_AVLdSt_Any(Inst, Imm,
                                   AMDGPUDisassembler::OPW64, Decoder);
 }
 
-static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst,
-                                                 unsigned Imm,
-                                                 uint64_t Addr,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
+                             const MCDisassembler *Decoder) {
   return decodeOperand_AVLdSt_Any(Inst, Imm,
                                   AMDGPUDisassembler::OPW96, Decoder);
 }
 
-static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst,
-                                                  unsigned Imm,
-                                                  uint64_t Addr,
-                                                  const void *Decoder) {
+static DecodeStatus
+DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
+                              const MCDisassembler *Decoder) {
   return decodeOperand_AVLdSt_Any(Inst, Imm,
                                   AMDGPUDisassembler::OPW128, Decoder);
 }
 
-static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
-                                          unsigned Imm,
+static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm,
                                           uint64_t Addr,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
 }
 
 #define DECODE_SDWA(DecName) \
 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
 
 DECODE_SDWA(Src32)

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

 static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
                               uint64_t &Size, uint32_t &Insn) {
   Size = 2;
   Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
   return true;
 }
 
 template <unsigned B>
-static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
-                                        uint64_t Address = 0,
-                                        const void *Decoder = nullptr);
+static DecodeStatus
+DecodeSignedOperand(MCInst &Inst, unsigned InsnS, uint64_t Address = 0,
+                    const MCDisassembler *Decoder = nullptr);
 
 template <unsigned B>
-static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS,
-                                        uint64_t Address = 0,
-                                        const void *Decoder = nullptr);
+static DecodeStatus
+DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, uint64_t Address = 0,
+                      const MCDisassembler *Decoder = nullptr);
 
 template <unsigned B>
 static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t, const void *);
+static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t,
+                                 const MCDisassembler *);
 
 static DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t,
-                                            const void *);
+                                            const MCDisassembler *);
 
 static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t,
-                                            const void *);
+                                            const MCDisassembler *);
 
 static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t,
-                                             const void *);
+                                             const MCDisassembler *);
 
 static DecodeStatus DecodeSOPwithRS12(MCInst &, uint64_t, uint64_t,
-                                      const void *);
+                                      const MCDisassembler *);
 
 static DecodeStatus DecodeSOPwithRU6(MCInst &, uint64_t, uint64_t,
-                                     const void *);
+                                     const MCDisassembler *);
 
 static DecodeStatus DecodeCCRU6Instruction(MCInst &, uint64_t, uint64_t,
-                                           const void *);
+                                           const MCDisassembler *);
 
 static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t, uint64_t,
-                                              const void *);
+                                              const MCDisassembler *);
 
 static const uint16_t GPR32DecoderTable[] = {
     ARC::R0,  ARC::R1,    ARC::R2,  ARC::R3,   ARC::R4,  ARC::R5,  ARC::R6,
     ARC::R7,  ARC::R8,    ARC::R9,  ARC::R10,  ARC::R11, ARC::R12, ARC::R13,
     ARC::R14, ARC::R15,   ARC::R16, ARC::R17,  ARC::R18, ARC::R19, ARC::R20,
     ARC::R21, ARC::R22,   ARC::R23, ARC::R24,  ARC::R25, ARC::GP,  ARC::FP,
     ARC::SP,  ARC::ILINK, ARC::R30, ARC::BLINK};
 
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo >= 32) {
     LLVM_DEBUG(dbgs() << "Not a GPR32 register.");
     return MCDisassembler::Fail;
   }
 
   unsigned Reg = GPR32DecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo,
-                                               uint64_t Address,
-                                               const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   // Enumerates registers from ranges [r0-r3],[r12-r15].
   if (RegNo > 3)
     RegNo += 8; // 4 for r12, etc...
 
   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 #include "ARCGenDisassemblerTables.inc"
 
 static unsigned decodeCField(unsigned Insn) {
   return fieldFromInstruction(Insn, 6, 6);
 }
 
 static unsigned decodeBField(unsigned Insn) {
   return (fieldFromInstruction(Insn, 12, 3) << 3) |
          fieldFromInstruction(Insn, 24, 3);
 }
 
 static unsigned decodeAField(unsigned Insn) {
   return fieldFromInstruction(Insn, 0, 6);
 }
 
 static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Dec) {
+                                 const MCDisassembler *Dec) {
   // We have the 9-bit immediate in the low bits, 6-bit register in high bits.
   unsigned S9 = Insn & 0x1ff;
   unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
   DecodeGPR32RegisterClass(Inst, R, Address, Dec);
   Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9)));
   return MCDisassembler::Success;
 }
 
 static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address,
-                                  uint64_t Value, const void *Decoder) {
+                                  uint64_t Value,
+                                  const MCDisassembler *Decoder) {
   static const uint64_t AtLeast = 2;
-  // TODO: Try to force emitter to use MCDisassembler* instead of void*.
-  auto Disassembler = static_cast<const MCDisassembler *>(Decoder);
-  return (nullptr != Disassembler &&
-          Disassembler->tryAddingSymbolicOperand(Inst, Value, Address, true, 0,
-                                                 AtLeast));
+  return (nullptr != Decoder && Decoder->tryAddingSymbolicOperand(
+                                    Inst, Value, Address, true, 0, AtLeast));
 }
 
 static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address,
-                                     uint64_t Offset, const void *Decoder) {
+                                     uint64_t Offset,
+                                     const MCDisassembler *Decoder) {
   uint64_t NextAddress = Address + Offset;
 
   if (!DecodeSymbolicOperand(Inst, Address, NextAddress, Decoder))
     Inst.addOperand(MCOperand::createImm(Offset));
 }
 
 template <unsigned B>
 static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
 
   static_assert(B > 0, "field is empty");
   DecodeSymbolicOperandOff(Inst, Address, SignExtend32<B>(InsnS), Decoder);
   return MCDisassembler::Success;
 }
 
 template <unsigned B>
 static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
                                         uint64_t /*Address*/,
-                                        const void * /*Decoder*/) {
+                                        const MCDisassembler * /*Decoder*/) {
 
   static_assert(B > 0, "field is empty");
   Inst.addOperand(MCOperand::createImm(
       SignExtend32<B>(maskTrailingOnes<decltype(InsnS)>(B) & InsnS)));
   return MCDisassembler::Success;
 }
 
 template <unsigned B>
 static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS,
                                           uint64_t /*Address*/,
-                                          const void * /*Decoder*/) {
+                                          const MCDisassembler * /*Decoder*/) {
 
   static_assert(B > 0, "field is empty");
   const unsigned max = (1u << B) - 1;
   Inst.addOperand(
       MCOperand::createImm(InsnS < max ? static_cast<int>(InsnS) : -1));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   unsigned SrcC, DstB, LImm;
   DstB = decodeBField(Insn);
   if (DstB != 62) {
     LLVM_DEBUG(dbgs() << "Decoding StLImm found non-limm register.");
     return MCDisassembler::Fail;
   }
   SrcC = decodeCField(Insn);
   DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder);
   LImm = (Insn >> 32);
   Inst.addOperand(MCOperand::createImm(LImm));
   Inst.addOperand(MCOperand::createImm(0));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   unsigned DstA, SrcB, LImm;
   LLVM_DEBUG(dbgs() << "Decoding LdLImm:\n");
   SrcB = decodeBField(Insn);
   if (SrcB != 62) {
     LLVM_DEBUG(dbgs() << "Decoding LdLImm found non-limm register.");
     return MCDisassembler::Fail;
   }
   DstA = decodeAField(Insn);
   DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder);
   LImm = (Insn >> 32);
   Inst.addOperand(MCOperand::createImm(LImm));
   Inst.addOperand(MCOperand::createImm(0));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   unsigned DstA, SrcB;
   LLVM_DEBUG(dbgs() << "Decoding LdRLimm\n");
   DstA = decodeAField(Insn);
   DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder);
   SrcB = decodeBField(Insn);
   DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder);
   if (decodeCField(Insn) != 62) {
     LLVM_DEBUG(dbgs() << "Decoding LdRLimm found non-limm register.");
     return MCDisassembler::Fail;
   }
   Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32)));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   LLVM_DEBUG(dbgs() << "Decoding MOV_S h-register\n");
   using Field = decltype(Insn);
   Field H = fieldFromInstruction(Insn, 5, 3) |
             (fieldFromInstruction(Insn, 0, 2) << 3);
   Field G = fieldFromInstruction(Insn, 8, 3) |
             (fieldFromInstruction(Insn, 3, 2) << 3);
 
   auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum,
static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn,
   if (MCDisassembler::Success != DecodeRegisterOrImm(G, 0))
     return MCDisassembler::Fail;
 
   return DecodeRegisterOrImm(H, Insn >> 16u);
 }
 
 static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   unsigned DstB;
   LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n");
   DstB = decodeBField(Insn);
   DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
   using Field = decltype(Insn);
   Field U6Field = fieldFromInstruction(Insn, 6, 6);
   Inst.addOperand(MCOperand::createImm(U6Field));
   Field CCField = fieldFromInstruction(Insn, 0, 4);
   Inst.addOperand(MCOperand::createImm(CCField));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn,
-                                     uint64_t Address, const void *Decoder) {
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   unsigned DstB = decodeBField(Insn);
   DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
   using Field = decltype(Insn);
   Field U6 = fieldFromInstruction(Insn, 6, 6);
   Inst.addOperand(MCOperand::createImm(U6));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSOPwithRS12(MCInst &Inst, uint64_t Insn,
-                                      uint64_t Address, const void *Decoder) {
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   unsigned DstB = decodeBField(Insn);
   DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
   using Field = decltype(Insn);
   Field Lower = fieldFromInstruction(Insn, 6, 6);
   Field Upper = fieldFromInstruction(Insn, 0, 5);
   Field Sign = fieldFromInstruction(Insn, 5, 1) ? -1 : 1;
   Field Result = Sign * ((Upper << 6) + Lower);
   Inst.addOperand(MCOperand::createImm(Result));

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

case MCDisassembler::Fail:
       return false;
   }
   llvm_unreachable("Invalid DecodeStatus!");
 }
 
 // Forward declare these because the autogenerated code will reference them.
 // Definitions are further down.
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder);
 static DecodeStatus
 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
-static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
-                                               unsigned RegNo, uint64_t Address,
-                                               const void *Decoder);
-static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
-                                               unsigned RegNo, uint64_t Address,
-                                               const void *Decoder);
-static DecodeStatus DecodeGPRwithZRnospRegisterClass(
-    MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
+                                               const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder);
+static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                                 uint64_t Address,
+                                                 const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
-                                                unsigned RegNo,
-                                                uint64_t Address,
-                                                const void *Decoder);
+                                             const MCDisassembler *Decoder);
+static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
-                               unsigned RegNo, uint64_t Address,
-                               const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder);
 
 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder);
 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
-                                                  unsigned Insn,
-                                                  uint64_t Address,
-                                                  const void *Decoder);
+                                            const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
+static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
-                                         uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
-                                                  unsigned Insn,
-                                                  uint64_t Adddress,
-                                                  const void *Decoder);
+static DecodeStatus
+DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
+                                      const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
                                                  uint64_t Address,
-                                                 const void *Decoder);
+                                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
+static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
+static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val,
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder);
+static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder);
 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-template<int shift>
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
+template <int shift>
 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder);
 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder);
 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder);
+static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
+static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
+                               const MCDisassembler *Decoder);
+static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                const MCDisassembler *Decoder);
+static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
-                                         uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
-                                                       unsigned Val,
-                                                       uint64_t Address,
-                                                       const void *Decoder);
+                                         const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address,
+                                   const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
-                               uint64_t Address, const void *Decoder);
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void* Decoder);
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void* Decoder);
-static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void* Decoder);
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder);
+static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void* Decoder);
-static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder);
+static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
+                                   const MCDisassembler *Decoder);
+static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
+                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
                                            uint64_t Address,
-                                           const void *Decoder);
-static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
-template<int shift>
-static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                           const MCDisassembler *Decoder);
+static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder);
+static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
+                                 const MCDisassembler *Decoder);
+template <int shift>
+static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
-template<int shift>
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
+template <int shift>
 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
-template<int shift, int WriteBack>
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
+template <int shift, int WriteBack>
 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
-                               uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
-                                uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
-                                uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
-                                uint64_t Address, const void *Decoder);
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
+static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
+static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address,
+                             const MCDisassembler *Decoder);
+static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
+static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
+static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address,
+                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
+                              const MCDisassembler *Decoder);
 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
-                                            uint64_t Address, const void *Decoder);
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
-                                         uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 
 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
-                                         uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
                                           uint64_t Address,
-                                          const void *Decoder);
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                  const void *Decoder);
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
-                                         uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val,
-                                                     uint64_t Address,
-                                                     const void *Decoder);
-static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val,
-                                                     uint64_t Address,
-                                                     const void *Decoder);
-static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val,
-                                                     uint64_t Address,
-                                                     const void *Decoder);
-static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst,
-                                                       unsigned Val,
-                                                       uint64_t Address,
-                                                       const void *Decoder);
-template<bool Writeback>
+                                         const MCDisassembler *Decoder);
+static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
+                                        const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                   const MCDisassembler *Decoder);
+template <bool Writeback>
 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
                                           uint64_t Address,
-                                          const void *Decoder);
-template<int shift>
+                                          const MCDisassembler *Decoder);
+template <int shift>
 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder);
-template<int shift>
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
+template <int shift>
 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder);
-template<int shift>
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
+template <int shift>
 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder);
-template<unsigned MinLog, unsigned MaxLog>
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
+template <unsigned MinLog, unsigned MaxLog>
 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
                                           uint64_t Address,
-                                          const void *Decoder);
-template<unsigned start>
-static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
-                                                    uint64_t Address,
-                                                    const void *Decoder);
+                                          const MCDisassembler *Decoder);
+template <unsigned start>
+static DecodeStatus
+DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
                                          uint64_t Address,
-                                         const void *Decoder);
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
                                          uint64_t Address,
-                                         const void *Decoder);
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
-                                      uint64_t Address, const void *Decoder);
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder);
 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
-                                    uint64_t Address, const void *Decoder);
-template<bool scalar, OperandDecoder predicate_decoder>
-static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
+template <bool scalar, OperandDecoder predicate_decoder>
+static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
-                                                  uint64_t Address,
-                                                  const void *Decoder);
+                                   const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
+                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 
 #include "ARMGenDisassemblerTables.inc"
 
 static MCDisassembler *createARMDisassembler(const Target &T,
                                              const MCSubtargetInfo &STI,
                                              MCContext &Ctx) {
   return new ARMDisassembler(STI, Ctx);
 }

 /// that returns non-zero then the symbolic information it returns is used to
 /// create an MCExpr and that is added as an operand to the MCInst.  If
 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
 /// Value is done and if a symbol is found an MCExpr is created with that, else
 /// an MCExpr with Value is created.  This function returns true if it adds an
 /// operand to the MCInst and false otherwise.
 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
                                      bool isBranch, uint64_t InstSize,
-                                     MCInst &MI, const void *Decoder) {
-  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
+                                     MCInst &MI,
+                                     const MCDisassembler *Decoder) {
   // FIXME: Does it make sense for value to be negative?
-  return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
-                                       /* Offset */ 0, InstSize);
+  return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
+                                           isBranch, /* Offset */ 0, InstSize);
 }
 
 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
 /// referenced by a load instruction with the base register that is the Pc.
 /// These can often be values in a literal pool near the Address of the
 /// instruction.  The Address of the instruction and its immediate Value are
 /// used as a possible literal pool entry.  The SymbolLookUp call back will
 /// return the name of a symbol referenced by the literal pool's entry if
 /// the referenced address is that of a symbol.  Or it will return a pointer to
 /// a literal 'C' string if the referenced address of the literal pool's entry
 /// is an address into a section with 'C' string literals.
 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
   Dis->tryAddingPcLoadReferenceComment(Value, Address);
 }
 
 // Thumb1 instructions don't have explicit S bits.  Rather, they
 // implicitly set CPSR.  Since it's not represented in the encoding, the
 // auto-generated decoder won't inject the CPSR operand.  We need to fix
 // that as a post-pass.

 static const uint16_t CLRMGPRDecoderTable[] = {
   ARM::R0, ARM::R1, ARM::R2, ARM::R3,
   ARM::R4, ARM::R5, ARM::R6, ARM::R7,
   ARM::R8, ARM::R9, ARM::R10, ARM::R11,
   ARM::R12, 0, ARM::LR, ARM::APSR
 };
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
 
   unsigned Register = GPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
 
   unsigned Register = CLRMGPRDecoderTable[RegNo];
   if (Register == 0)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus
-DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
-                           uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (RegNo == 15)
     S = MCDisassembler::SoftFail;
 
   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
 
   return S;
 }
 
 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (RegNo == 13)
     S = MCDisassembler::SoftFail;
 
   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
 
   return S;
 }
 
 static DecodeStatus
-DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
-                               uint64_t Address, const void *Decoder) {
+DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (RegNo == 15)
   {
     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
     return MCDisassembler::Success;
   }
 
   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
   return S;
 }
 
 static DecodeStatus
-DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
-                             uint64_t Address, const void *Decoder) {
+DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (RegNo == 15)
   {
     Inst.addOperand(MCOperand::createReg(ARM::ZR));
     return MCDisassembler::Success;
   }
 
   if (RegNo == 13)
     Check(S, MCDisassembler::SoftFail);
 
   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
   return S;
 }
 
 static DecodeStatus
-DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo,
-                                 uint64_t Address, const void *Decoder) {
+DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   if (RegNo == 13)
     return MCDisassembler::Fail;
   Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
   return S;
 }
 
 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static const uint16_t GPRPairDecoderTable[] = {
   ARM::R0_R1, ARM::R2_R3,   ARM::R4_R5,  ARM::R6_R7,
   ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
 };
 
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   // According to the Arm ARM RegNo = 14 is undefined, but we return fail
   // rather than SoftFail as there is no GPRPair table entry for index 7.
   if (RegNo > 13)
     return MCDisassembler::Fail;
 
   if (RegNo & 1)
      S = MCDisassembler::SoftFail;
 
   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
   Inst.addOperand(MCOperand::createReg(RegisterPair));
   return S;
 }
 
-static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder) {
   if (RegNo > 13)
     return MCDisassembler::Fail;
 
   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
   Inst.addOperand(MCOperand::createReg(RegisterPair));
 
   if ((RegNo & 1) || RegNo > 10)
      return MCDisassembler::SoftFail;
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo != 13)
     return MCDisassembler::Fail;
 
   unsigned Register = GPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   unsigned Register = 0;
   switch (RegNo) {
     case 0:
       Register = ARM::R0;
       break;
     case 1:
       Register = ARM::R1;
       break;
default:
       return MCDisassembler::Fail;
     }
 
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   const FeatureBitset &featureBits =
     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
 
   if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
     S = MCDisassembler::SoftFail;
 
   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
   return S;
 }
 
 static const uint16_t SPRDecoderTable[] = {
      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
      ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
     ARM::S12, ARM::S13, ARM::S14, ARM::S15,
     ARM::S16, ARM::S17, ARM::S18, ARM::S19,
     ARM::S20, ARM::S21, ARM::S22, ARM::S23,
     ARM::S24, ARM::S25, ARM::S26, ARM::S27,
     ARM::S28, ARM::S29, ARM::S30, ARM::S31
 };
 
 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Register = SPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static const uint16_t DPRDecoderTable[] = {
      ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
      ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
      ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
     ARM::D12, ARM::D13, ARM::D14, ARM::D15,
     ARM::D16, ARM::D17, ARM::D18, ARM::D19,
     ARM::D20, ARM::D21, ARM::D22, ARM::D23,
     ARM::D24, ARM::D25, ARM::D26, ARM::D27,
     ARM::D28, ARM::D29, ARM::D30, ARM::D31
 };
 
 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   const FeatureBitset &featureBits =
     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
 
   bool hasD32 = featureBits[ARM::FeatureD32];
 
   if (RegNo > 31 || (!hasD32 && RegNo > 15))
     return MCDisassembler::Fail;
 
   unsigned Register = DPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
   return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static DecodeStatus
-DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
-                            uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static const uint16_t QPRDecoderTable[] = {
      ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
      ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
      ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
     ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
 };
 
 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 31 || (RegNo & 1) != 0)
     return MCDisassembler::Fail;
   RegNo >>= 1;
 
   unsigned Register = QPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static const uint16_t DPairDecoderTable[] = {
   ARM::Q0,  ARM::D1_D2,   ARM::Q1,  ARM::D3_D4,   ARM::Q2,  ARM::D5_D6,
   ARM::Q3,  ARM::D7_D8,   ARM::Q4,  ARM::D9_D10,  ARM::Q5,  ARM::D11_D12,
   ARM::Q6,  ARM::D13_D14, ARM::Q7,  ARM::D15_D16, ARM::Q8,  ARM::D17_D18,
   ARM::Q9,  ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
   ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
   ARM::Q15
 };
 
 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 30)
     return MCDisassembler::Fail;
 
   unsigned Register = DPairDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static const uint16_t DPairSpacedDecoderTable[] = {
   ARM::D0_D2,   ARM::D1_D3,   ARM::D2_D4,   ARM::D3_D5,
   ARM::D4_D6,   ARM::D5_D7,   ARM::D6_D8,   ARM::D7_D9,
   ARM::D8_D10,  ARM::D9_D11,  ARM::D10_D12, ARM::D11_D13,
   ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
   ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
   ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
   ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
   ARM::D28_D30, ARM::D29_D31
 };
 
-static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
-                                                   unsigned RegNo,
-                                                   uint64_t Address,
-                                                   const void *Decoder) {
+static DecodeStatus
+DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder) {
   if (RegNo > 29)
     return MCDisassembler::Fail;
 
   unsigned Register = DPairSpacedDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   if (Val == 0xF) return MCDisassembler::Fail;
   // AL predicate is not allowed on Thumb1 branches.
   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
     return MCDisassembler::Fail;
   if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
     Check(S, MCDisassembler::SoftFail);
   Inst.addOperand(MCOperand::createImm(Val));
   if (Val == ARMCC::AL) {
     Inst.addOperand(MCOperand::createReg(0));
   } else
     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
   return S;
 }
 
 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   if (Val)
     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
   else
     Inst.addOperand(MCOperand::createReg(0));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rm = fieldFromInstruction(Val, 0, 4);
   unsigned type = fieldFromInstruction(Val, 5, 2);
   unsigned imm = fieldFromInstruction(Val, 7, 5);
 
   // Register-immediate
   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
 
   unsigned Op = Shift | (imm << 3);
   Inst.addOperand(MCOperand::createImm(Op));
 
   return S;
 }
 
 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rm = fieldFromInstruction(Val, 0, 4);
   unsigned type = fieldFromInstruction(Val, 5, 2);
   unsigned Rs = fieldFromInstruction(Val, 8, 4);
 
   // Register-register
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
   }
 
   Inst.addOperand(MCOperand::createImm(Shift));
 
   return S;
 }
 
 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   bool NeedDisjointWriteback = false;
   unsigned WritebackReg = 0;
   bool CLRM = false;
   switch (Inst.getOpcode()) {
   default:
     break;
if (Val & (1 << i)) {
       }
     }
   }
 
   return S;
 }
 
 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Vd = fieldFromInstruction(Val, 8, 5);
   unsigned regs = fieldFromInstruction(Val, 0, 8);
 
   // In case of unpredictable encoding, tweak the operands.
   if (regs == 0 || (Vd + regs) > 32) {
     regs = Vd + regs > 32 ? 32 - Vd : regs;
     regs = std::max( 1u, regs);
     S = MCDisassembler::SoftFail;
   }
 
   if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
     return MCDisassembler::Fail;
   for (unsigned i = 0; i < (regs - 1); ++i) {
     if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
       return MCDisassembler::Fail;
   }
 
   return S;
 }
 
 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Vd = fieldFromInstruction(Val, 8, 5);
   unsigned regs = fieldFromInstruction(Val, 1, 7);
 
   // In case of unpredictable encoding, tweak the operands.
   if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
     regs = Vd + regs > 32 ? 32 - Vd : regs;
     regs = std::max( 1u, regs);
     regs = std::min(16u, regs);
     S = MCDisassembler::SoftFail;
   }
 
   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
       return MCDisassembler::Fail;
   for (unsigned i = 0; i < (regs - 1); ++i) {
     if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
       return MCDisassembler::Fail;
   }
 
   return S;
 }
 
 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
-                                      uint64_t Address, const void *Decoder) {
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
   // This operand encodes a mask of contiguous zeros between a specified MSB
   // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
   // the mask of all bits LSB-and-lower, and then xor them to create
   // the mask of that's all ones on [msb, lsb].  Finally we not it to
   // create the final mask.
   unsigned msb = fieldFromInstruction(Val, 5, 5);
   unsigned lsb = fieldFromInstruction(Val, 0, 5);
 
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
   if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
   uint32_t lsb_mask = (1U << lsb) - 1;
 
   Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
   return S;
 }
 
 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
   unsigned CRd = fieldFromInstruction(Insn, 12, 4);
   unsigned coproc = fieldFromInstruction(Insn, 8, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 8);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned U = fieldFromInstruction(Insn, 23, 1);
switch (Inst.getOpcode()) {
     default:
       break;
   }
 
   return S;
 }
 
 static DecodeStatus
-DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
-                              uint64_t Address, const void *Decoder) {
+DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+                              const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 12);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
   unsigned reg = fieldFromInstruction(Insn, 25, 1);
DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
-                                  uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 13, 4);
   unsigned Rm = fieldFromInstruction(Val,  0, 4);
   unsigned type = fieldFromInstruction(Val, 5, 2);
   unsigned imm = fieldFromInstruction(Val, 7, 5);
   unsigned U = fieldFromInstruction(Val, 12, 1);
 
else
     shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
   Inst.addOperand(MCOperand::createImm(shift));
 
   return S;
 }
 
 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
     return MCDisassembler::Fail;
 
   // The "csync" operand is not encoded into the "tsb" instruction (as this is
   // the only available operand), but LLVM expects the instruction to have one
   // operand, so we need to add the csync when decoding.
   Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus
-DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
-                           uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned type = fieldFromInstruction(Insn, 22, 1);
   unsigned imm = fieldFromInstruction(Insn, 8, 4);
   unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
 
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
-                                 uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned mode = fieldFromInstruction(Insn, 23, 2);
 
   switch (mode) {
     case 0:
       mode = ARM_AM::da;
static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
   Inst.addOperand(MCOperand::createImm(mode));
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
 
   if (pred == 0xF)
     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
 
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
   return S;
 }
 
-static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
-                                  unsigned Insn,
-                                  uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
   unsigned reglist = fieldFromInstruction(Insn, 0, 16);
 
   if (pred == 0xF) {
     // Ambiguous with RFE and SRS
DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
   if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 // Check for UNPREDICTABLE predicated ESB instruction
 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
-                                 uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
   unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
 
   DecodeStatus S = MCDisassembler::Success;
 
   Inst.addOperand(MCOperand::createImm(imm8));
 
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
   // so all predicates should be allowed.
   if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
     S = MCDisassembler::SoftFail;
 
   return S;
 }
 
 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
-                                 uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   unsigned imod = fieldFromInstruction(Insn, 18, 2);
   unsigned M = fieldFromInstruction(Insn, 17, 1);
   unsigned iflags = fieldFromInstruction(Insn, 6, 3);
   unsigned mode = fieldFromInstruction(Insn, 0, 5);
 
   DecodeStatus S = MCDisassembler::Success;
 
   // This decoder is called from multiple location that do not check
if (imod && M) {
     Inst.addOperand(MCOperand::createImm(mode));
     S = MCDisassembler::SoftFail;
   }
 
   return S;
 }
 
 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
-                                 uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   unsigned imod = fieldFromInstruction(Insn, 9, 2);
   unsigned M = fieldFromInstruction(Insn, 8, 1);
   unsigned iflags = fieldFromInstruction(Insn, 5, 3);
   unsigned mode = fieldFromInstruction(Insn, 0, 5);
 
   DecodeStatus S = MCDisassembler::Success;
 
   // imod == '01' --> UNPREDICTABLE
if (imod && M) {
     if(imm > 4) return MCDisassembler::Fail;
     Inst.setOpcode(ARM::t2HINT);
     Inst.addOperand(MCOperand::createImm(imm));
   }
 
   return S;
 }
 
-static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   unsigned imm = fieldFromInstruction(Insn, 0, 8);
 
   unsigned Opcode = ARM::t2HINT;
 
   if (imm == 0x0D) {
     Opcode = ARM::t2PACBTI;
   } else if (imm == 0x1D) {
     Opcode = ARM::t2PAC;
   } else if (imm == 0x2D) {
     Opcode = ARM::t2AUT;
   } else if (imm == 0x0F) {
     Opcode = ARM::t2BTI;
   }
 
   Inst.setOpcode(Opcode);
   if (Opcode == ARM::t2HINT) {
     Inst.addOperand(MCOperand::createImm(imm));
   }
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
-                                 uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 8, 4);
   unsigned imm = 0;
 
   imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
   imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
   imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
 
   if (Inst.getOpcode() == ARM::t2MOVTi16)
     if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
       return MCDisassembler::Fail;
   if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
     return MCDisassembler::Fail;
 
   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
     Inst.addOperand(MCOperand::createImm(imm));
 
   return S;
 }
 
 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
-                                 uint64_t Address, const void *Decoder) {
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
   unsigned imm = 0;
 
   imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
 
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
-                                 uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 16, 4);
   unsigned Rn = fieldFromInstruction(Insn, 0, 4);
   unsigned Rm = fieldFromInstruction(Insn, 8, 4);
   unsigned Ra = fieldFromInstruction(Insn, 12, 4);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
 
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
 
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Pred = fieldFromInstruction(Insn, 28, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
 
   if (Pred == 0xF)
     return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Imm = fieldFromInstruction(Insn, 9, 1);
 
   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
 
   if (!FeatureBits[ARM::HasV8_1aOps] ||
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
 
   Inst.setOpcode(ARM::SETPAN);
   Inst.addOperand(MCOperand::createImm(Imm));
 
   return S;
 }
 
 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
-                           uint64_t Address, const void *Decoder) {
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned add = fieldFromInstruction(Val, 12, 1);
   unsigned imm = fieldFromInstruction(Val, 0, 12);
   unsigned Rn = fieldFromInstruction(Val, 13, 4);
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
 
   if (!add) imm *= -1;
   if (imm == 0 && !add) imm = INT32_MIN;
   Inst.addOperand(MCOperand::createImm(imm));
   if (Rn == 15)
     tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
 
   return S;
 }
 
 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 9, 4);
   // U == 1 to add imm, 0 to subtract it.
   unsigned U = fieldFromInstruction(Val, 8, 1);
   unsigned imm = fieldFromInstruction(Val, 0, 8);
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
 
   if (U)
     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
   else
     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
 
   return S;
 }
 
 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
-                                   uint64_t Address, const void *Decoder) {
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 9, 4);
   // U == 1 to add imm, 0 to subtract it.
   unsigned U = fieldFromInstruction(Val, 8, 1);
   unsigned imm = fieldFromInstruction(Val, 0, 8);
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
 
   if (U)
     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
   else
     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
 
   return S;
 }
 
 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
 }
 
-static DecodeStatus
-DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
-                     uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus Status = MCDisassembler::Success;
 
   // Note the J1 and J2 values are from the encoded instruction.  So here
   // change them to I1 and I2 values via as documented:
   // I1 = NOT(J1 EOR S);
   // I2 = NOT(J2 EOR S);
   // and build the imm32 with one trailing zero as documented:
   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
   unsigned S = fieldFromInstruction(Insn, 26, 1);
   unsigned J1 = fieldFromInstruction(Insn, 13, 1);
   unsigned J2 = fieldFromInstruction(Insn, 11, 1);
   unsigned I1 = !(J1 ^ S);
   unsigned I2 = !(J2 ^ S);
   unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
   unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
   unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
   int imm32 = SignExtend32<25>(tmp << 1);
   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
                                 true, 4, Inst, Decoder))
     Inst.addOperand(MCOperand::createImm(imm32));
 
   return Status;
 }
 
-static DecodeStatus
-DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
-                           uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
 
   if (pred == 0xF) {
     Inst.setOpcode(ARM::BLXi);
     imm |= fieldFromInstruction(Insn, 24, 1) << 1;
static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
   if (Inst.getOpcode() != ARM::BL)
     if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
       return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rm = fieldFromInstruction(Val, 0, 4);
   unsigned align = fieldFromInstruction(Val, 4, 2);
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!align)
     Inst.addOperand(MCOperand::createImm(0));
   else
     Inst.addOperand(MCOperand::createImm(4 << align));
 
   return S;
 }
 
 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned wb = fieldFromInstruction(Insn, 16, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
   case ARM::VLD2q32wb_fixed:
     break;
   }
 
   return S;
 }
 
 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   unsigned type = fieldFromInstruction(Insn, 8, 4);
   unsigned align = fieldFromInstruction(Insn, 4, 2);
   if (type == 6 && (align & 2)) return MCDisassembler::Fail;
   if (type == 7 && (align & 2)) return MCDisassembler::Fail;
   if (type == 10 && align == 3) return MCDisassembler::Fail;
 
   unsigned load = fieldFromInstruction(Insn, 21, 1);
   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
 }
 
 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   unsigned size = fieldFromInstruction(Insn, 6, 2);
   if (size == 3) return MCDisassembler::Fail;
 
   unsigned type = fieldFromInstruction(Insn, 8, 4);
   unsigned align = fieldFromInstruction(Insn, 4, 2);
   if (type == 8 && align == 3) return MCDisassembler::Fail;
   if (type == 9 && align == 3) return MCDisassembler::Fail;
 
   unsigned load = fieldFromInstruction(Insn, 21, 1);
   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
 }
 
 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   unsigned size = fieldFromInstruction(Insn, 6, 2);
   if (size == 3) return MCDisassembler::Fail;
 
   unsigned align = fieldFromInstruction(Insn, 4, 2);
   if (align & 2) return MCDisassembler::Fail;
 
   unsigned load = fieldFromInstruction(Insn, 21, 1);
   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
 }
 
 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   unsigned size = fieldFromInstruction(Insn, 6, 2);
   if (size == 3) return MCDisassembler::Fail;
 
   unsigned load = fieldFromInstruction(Insn, 21, 1);
   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
 }
 
 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
-                                 uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned wb = fieldFromInstruction(Insn, 16, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
switch (Inst.getOpcode()) {
     default:
       break;
   }
 
   return S;
 }
 
 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned align = fieldFromInstruction(Insn, 4, 1);
   unsigned size = fieldFromInstruction(Insn, 6, 2);
static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
   if (Rm != 0xD && Rm != 0xF &&
       !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned align = fieldFromInstruction(Insn, 4, 1);
   unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
if (Rm != 0xD && Rm != 0xF) {
     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
       return MCDisassembler::Fail;
   }
 
   return S;
 }
 
 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
 
else if (Rm != 0xF) {
     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
       return MCDisassembler::Fail;
   }
 
   return S;
 }
 
 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned size = fieldFromInstruction(Insn, 6, 2);
   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
   else if (Rm != 0xF) {
     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
       return MCDisassembler::Fail;
   }
 
   return S;
 }
 
-static DecodeStatus
-DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
-                            uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned imm = fieldFromInstruction(Insn, 0, 4);
   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
   imm |= fieldFromInstruction(Insn, 24, 1) << 7;
   imm |= fieldFromInstruction(Insn, 8, 4) << 8;
case ARM::VBICiv4i32:
       break;
     default:
       break;
   }
 
   return S;
 }
 
-static DecodeStatus
-DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
-                           uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
                  fieldFromInstruction(Insn, 13, 3));
   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 4);
   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
   imm |= fieldFromInstruction(Insn, 28, 1) << 7;
static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
   Inst.addOperand(MCOperand::createImm(ARMVCC::None));
   Inst.addOperand(MCOperand::createReg(0));
   Inst.addOperand(MCOperand::createImm(0));
 
   return S;
 }
 
 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Qd = fieldFromInstruction(Insn, 13, 3);
   Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
 
   unsigned Qn = fieldFromInstruction(Insn, 17, 3);
   Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
     return MCDisassembler::Fail;
   unsigned Qm = fieldFromInstruction(Insn, 1, 3);
   Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
     Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
   Inst.addOperand(MCOperand::createImm(Qd));
 
   return S;
 }
 
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
   unsigned size = fieldFromInstruction(Insn, 18, 2);
 
   if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(8 << size));
 
   return S;
 }
 
 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(8 - Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(16 - Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(32 - Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(64 - Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
 
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
-                                     uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned dst = fieldFromInstruction(Insn, 8, 3);
   unsigned imm = fieldFromInstruction(Insn, 0, 8);
 
   if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
     return MCDisassembler::Fail;
 
   switch(Inst.getOpcode()) {
     default:
       return MCDisassembler::Fail;
     case ARM::tADR:
       break; // tADR does not explicitly represent the PC as an operand.
     case ARM::tADDrSPi:
       Inst.addOperand(MCOperand::createReg(ARM::SP));
       break;
   }
 
   Inst.addOperand(MCOperand::createImm(imm));
   return S;
 }
 
 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
                                 true, 2, Inst, Decoder))
     Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
                                 true, 4, Inst, Decoder))
     Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
                                 true, 2, Inst, Decoder))
     Inst.addOperand(MCOperand::createImm(Val << 1));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 0, 3);
   unsigned Rm = fieldFromInstruction(Val, 3, 3);
 
   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
-                                  uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 0, 3);
   unsigned imm = fieldFromInstruction(Val, 3, 5);
 
   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(imm));
 
   return S;
 }
 
 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
-                                  uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   unsigned imm = Val << 2;
 
   Inst.addOperand(MCOperand::createImm(imm));
   tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
-                                  uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createReg(ARM::SP));
   Inst.addOperand(MCOperand::createImm(Val));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
-                                  uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 6, 4);
   unsigned Rm = fieldFromInstruction(Val, 2, 4);
   unsigned imm = fieldFromInstruction(Val, 0, 2);
 
   // Thumb stores cannot use PC as dest register.
   switch (Inst.getOpcode()) {
static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(imm));
 
   return S;
 }
 
 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
-                              uint64_t Address, const void *Decoder) {
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
 
   const FeatureBitset &featureBits =
     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
 
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
   addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
   if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void* Decoder) {
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned U = fieldFromInstruction(Insn, 9, 1);
   unsigned imm = fieldFromInstruction(Insn, 0, 8);
   imm |= (U << 8);
   imm |= (Rn << 9);
static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
   }
 
   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
   return S;
 }
 
 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void* Decoder) {
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 12);
   imm |= (Rn << 13);
 
   const FeatureBitset &featureBits =
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
       return MCDisassembler::Fail;
   }
 
   if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
   return S;
 }
 
-static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void* Decoder) {
+static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 8);
   imm |= (Rn << 9);
 
   if (Rn == 15) {
static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
   return S;
 }
 
 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void* Decoder) {
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned U = fieldFromInstruction(Insn, 23, 1);
   int imm = fieldFromInstruction(Insn, 0, 12);
 
   const FeatureBitset &featureBits =
     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
if (!U) {
     else
       imm = -imm;
   }
   Inst.addOperand(MCOperand::createImm(imm));
 
   return S;
 }
 
-static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
-                           uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   if (Val == 0)
     Inst.addOperand(MCOperand::createImm(INT32_MIN));
   else {
     int imm = Val & 0xFF;
 
     if (!(Val & 0x100)) imm *= -1;
     Inst.addOperand(MCOperand::createImm(imm * 4));
   }
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
-                                   const void *Decoder) {
+                                   const MCDisassembler *Decoder) {
   if (Val == 0)
     Inst.addOperand(MCOperand::createImm(INT32_MIN));
   else {
     int imm = Val & 0x7F;
 
     if (!(Val & 0x80))
       imm *= -1;
     Inst.addOperand(MCOperand::createImm(imm * 4));
   }
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 9, 4);
   unsigned imm = fieldFromInstruction(Val, 0, 9);
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 8, 4);
   unsigned imm = fieldFromInstruction(Val, 0, 8);
 
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
-                                   uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 8, 4);
   unsigned imm = fieldFromInstruction(Val, 0, 8);
 
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(imm));
 
   return S;
 }
 
-static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
-                         uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   int imm = Val & 0xFF;
   if (Val == 0)
     imm = INT32_MIN;
   else if (!(Val & 0x100))
     imm *= -1;
   Inst.addOperand(MCOperand::createImm(imm));
 
   return MCDisassembler::Success;
 }
 
-template<int shift>
-static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
-                         uint64_t Address, const void *Decoder) {
+template <int shift>
+static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   int imm = Val & 0x7F;
   if (Val == 0)
     imm = INT32_MIN;
   else if (!(Val & 0x80))
     imm *= -1;
   if (imm != INT32_MIN)
     imm *= (1U << shift);
   Inst.addOperand(MCOperand::createImm(imm));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 9, 4);
   unsigned imm = fieldFromInstruction(Val, 0, 9);
 
   // Thumb stores cannot use PC as dest register.
   switch (Inst.getOpcode()) {
   case ARM::t2STRT:
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-template<int shift>
+template <int shift>
 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
-                                         uint64_t Address,
-                                         const void *Decoder) {
+                                        const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 8, 3);
   unsigned imm = fieldFromInstruction(Val, 0, 8);
 
   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-template<int shift, int WriteBack>
+template <int shift, int WriteBack>
 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 8, 4);
   unsigned imm = fieldFromInstruction(Val, 0, 8);
   if (WriteBack) {
     if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
       return MCDisassembler::Fail;
   } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned addr = fieldFromInstruction(Insn, 0, 8);
   addr |= fieldFromInstruction(Insn, 9, 1) << 8;
   addr |= Rn << 9;
   unsigned load = fieldFromInstruction(Insn, 20, 1);
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
 
   if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
-                                  uint64_t Address, const void *Decoder) {
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 13, 4);
   unsigned imm = fieldFromInstruction(Val, 0, 12);
 
   // Thumb stores cannot use PC as dest register.
   switch (Inst.getOpcode()) {
   case ARM::t2STRi12:
static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(imm));
 
   return S;
 }
 
 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
-                                uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   unsigned imm = fieldFromInstruction(Insn, 0, 7);
 
   Inst.addOperand(MCOperand::createReg(ARM::SP));
   Inst.addOperand(MCOperand::createReg(ARM::SP));
   Inst.addOperand(MCOperand::createImm(imm));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
-                                uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (Inst.getOpcode() == ARM::tADDrSP) {
     unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
     Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
 
     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
     return MCDisassembler::Fail;
     Inst.addOperand(MCOperand::createReg(ARM::SP));
     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
     return MCDisassembler::Fail;
   } else if (Inst.getOpcode() == ARM::tADDspr) {
     unsigned Rm = fieldFromInstruction(Insn, 3, 4);
 
     Inst.addOperand(MCOperand::createReg(ARM::SP));
     Inst.addOperand(MCOperand::createReg(ARM::SP));
     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   }
 
   return S;
 }
 
 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
-                           uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
   unsigned flags = fieldFromInstruction(Insn, 0, 3);
 
   Inst.addOperand(MCOperand::createImm(imod));
   Inst.addOperand(MCOperand::createImm(flags));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
-                             uint64_t Address, const void *Decoder) {
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned add = fieldFromInstruction(Insn, 4, 1);
 
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(add));
 
   return S;
 }
 
 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
-                             uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned Rn = fieldFromInstruction(Insn, 3, 4);
   unsigned Qm = fieldFromInstruction(Insn, 0, 3);
 
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-template<int shift>
+template <int shift>
 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
-                             uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned Qm = fieldFromInstruction(Insn, 8, 3);
   int imm = fieldFromInstruction(Insn, 0, 7);
 
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   if(!fieldFromInstruction(Insn, 7, 1)) {
     if (imm == 0)
       imm = INT32_MIN;                 // indicate -0
     else
       imm *= -1;
   }
   if (imm != INT32_MIN)
     imm *= (1U << shift);
   Inst.addOperand(MCOperand::createImm(imm));
 
   return S;
 }
 
 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
   // Note only one trailing zero not two.  Also the J1 and J2 values are from
   // the encoded instruction.  So here change to I1 and I2 values via:
   // I1 = NOT(J1 EOR S);
   // I2 = NOT(J2 EOR S);
   // and build the imm32 with two trailing zeros as documented:
   // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
   unsigned S = (Val >> 23) & 1;
   unsigned J1 = (Val >> 22) & 1;
   unsigned J2 = (Val >> 21) & 1;
   unsigned I1 = !(J1 ^ S);
   unsigned I2 = !(J2 ^ S);
   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
   int imm32 = SignExtend32<25>(tmp << 1);
 
   if (!tryAddingSymbolicOperand(Address,
                                 (Address & ~2u) + imm32 + 4,
                                 true, 4, Inst, Decoder))
     Inst.addOperand(MCOperand::createImm(imm32));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
-                              uint64_t Address, const void *Decoder) {
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   if (Val == 0xA || Val == 0xB)
     return MCDisassembler::Fail;
 
   const FeatureBitset &featureBits =
     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
 
   if (!isValidCoprocessorNumber(Val, featureBits))
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus
-DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
-                       uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   const FeatureBitset &FeatureBits =
     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
 
   if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   return S;
 }
 
-static DecodeStatus
-DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
-                           uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned pred = fieldFromInstruction(Insn, 22, 4);
   if (pred == 0xE || pred == 0xF) {
     unsigned opc = fieldFromInstruction(Insn, 4, 28);
     switch (opc) {
       default:
         return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 // Decode a shifted immediate operand.  These basically consist
 // of an 8-bit value, and a 4-bit directive that specifies either
 // a splat operation or a rotation.
-static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
-                          uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   unsigned ctrl = fieldFromInstruction(Val, 10, 2);
   if (ctrl == 0) {
     unsigned byte = fieldFromInstruction(Val, 8, 2);
     unsigned imm = fieldFromInstruction(Val, 0, 8);
     switch (byte) {
       case 0:
         Inst.addOperand(MCOperand::createImm(imm));
         break;
if (ctrl == 0) {
     unsigned rot = fieldFromInstruction(Val, 7, 5);
     unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
     Inst.addOperand(MCOperand::createImm(imm));
   }
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus
-DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
-                            uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder) {
   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
                                 true, 2, Inst, Decoder))
     Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   // Val is passed in as S:J1:J2:imm10:imm11
   // Note no trailing zero after imm11.  Also the J1 and J2 values are from
   // the encoded instruction.  So here change to I1 and I2 values via:
   // I1 = NOT(J1 EOR S);
   // I2 = NOT(J2 EOR S);
   // and build the imm32 with one trailing zero as documented:
   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
   unsigned S = (Val >> 23) & 1;
   unsigned J1 = (Val >> 22) & 1;
   unsigned J2 = (Val >> 21) & 1;
   unsigned I1 = !(J1 ^ S);
   unsigned I2 = !(J2 ^ S);
   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
   int imm32 = SignExtend32<25>(tmp << 1);
 
   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
                                 true, 4, Inst, Decoder))
     Inst.addOperand(MCOperand::createImm(imm32));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
-                                   uint64_t Address, const void *Decoder) {
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   if (Val & ~0xf)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder) {
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder) {
   if (Val & ~0xf)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
-                          uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   const FeatureBitset &FeatureBits =
     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
 
   if (FeatureBits[ARM::FeatureMClass]) {
     unsigned ValLow = Val & 0xff;
 
     // Validate the SYSm value first.
if (FeatureBits[ARM::FeatureMClass]) {
     if (Val == 0)
       return MCDisassembler::Fail;
   }
   Inst.addOperand(MCOperand::createImm(Val));
   return S;
 }
 
 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   unsigned R = fieldFromInstruction(Val, 5, 1);
   unsigned SysM = fieldFromInstruction(Val, 0, 5);
 
   // The table of encodings for these banked registers comes from B9.2.3 of the
   // ARM ARM. There are patterns, but nothing regular enough to make this logic
   // neater. So by fiat, these values are UNPREDICTABLE:
   if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
 
   if (Rn == 0xF)
     S = MCDisassembler::SoftFail;
 
   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
 
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
     return MCDisassembler::Fail;
 
   if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
     S = MCDisassembler::SoftFail;
 
   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
-                            uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 12);
   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
 
   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
-                            uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 12);
   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
-                            uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 12);
   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
 
   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
-                            uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned imm = fieldFromInstruction(Insn, 0, 12);
   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
 
   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
-                         uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned size = fieldFromInstruction(Insn, 10, 2);
 
static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
 
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(index));
 
   return S;
 }
 
-static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
-                         uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned size = fieldFromInstruction(Insn, 10, 2);
 
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
 
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(index));
 
   return S;
 }
 
-static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
-                         uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned size = fieldFromInstruction(Insn, 10, 2);
 
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(index));
 
   return S;
 }
 
-static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
-                         uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned size = fieldFromInstruction(Insn, 10, 2);
 
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(index));
 
   return S;
 }
 
-static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
-                         uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned size = fieldFromInstruction(Insn, 10, 2);
 
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(index));
 
   return S;
 }
 
-static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
-                         uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned size = fieldFromInstruction(Insn, 10, 2);
 
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(index));
 
   return S;
 }
 
-static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
-                         uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned size = fieldFromInstruction(Insn, 10, 2);
 
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(index));
 
   return S;
 }
 
-static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
-                         uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned size = fieldFromInstruction(Insn, 10, 2);
 
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(index));
 
   return S;
 }
 
-static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
 
   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
     S = MCDisassembler::SoftFail;
 
   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
 
   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
     S = MCDisassembler::SoftFail;
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
-                             uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned pred = fieldFromInstruction(Insn, 4, 4);
   unsigned mask = fieldFromInstruction(Insn, 0, 4);
 
   if (pred == 0xF) {
     pred = 0xE;
     S = MCDisassembler::SoftFail;
   }
if (pred & 1) {
     mask ^= BitsAboveLowBit;
   }
 
   Inst.addOperand(MCOperand::createImm(pred));
   Inst.addOperand(MCOperand::createImm(mask));
   return S;
 }
 
-static DecodeStatus
-DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
-                           uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned addr = fieldFromInstruction(Insn, 0, 8);
   unsigned W = fieldFromInstruction(Insn, 21, 1);
   unsigned U = fieldFromInstruction(Insn, 23, 1);
if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   // addr
   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-static DecodeStatus
-DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
-                           uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned addr = fieldFromInstruction(Insn, 0, 8);
   unsigned W = fieldFromInstruction(Insn, 21, 1);
   unsigned U = fieldFromInstruction(Insn, 23, 1);
if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
     return MCDisassembler::Fail;
   // addr
   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
-                                uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address,
+                                const MCDisassembler *Decoder) {
   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
   if (sign1 != sign2) return MCDisassembler::Fail;
   const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
   assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
   DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
 
   unsigned Val = fieldFromInstruction(Insn, 0, 8);
if (!Val) {
       Val = -Val;
   }
   Inst.addOperand(MCOperand::createImm(Val));
   return S;
 }
 
 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   // Shift of "asr #32" is not allowed in Thumb2 mode.
   if (Val == 0x20) S = MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Val));
   return S;
 }
 
-static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
+                               const MCDisassembler *Decoder) {
   unsigned Rt   = fieldFromInstruction(Insn, 12, 4);
   unsigned Rt2  = fieldFromInstruction(Insn, 0,  4);
   unsigned Rn   = fieldFromInstruction(Insn, 16, 4);
   unsigned pred = fieldFromInstruction(Insn, 28, 4);
 
   if (pred == 0xF)
     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
 
static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                const MCDisassembler *Decoder) {
   const FeatureBitset &featureBits =
       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
 
   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(64 - imm));
 
   return S;
 }
 
-static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
-                                uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                const MCDisassembler *Decoder) {
   const FeatureBitset &featureBits =
       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
 
   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(64 - imm));
 
   return S;
 }
 
-static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
-                                                       unsigned Insn,
-                                                       uint64_t Address,
-                                                       const void *Decoder) {
+static DecodeStatus
+DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn,
+                                   const MCDisassembler *Decoder) {
   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
   unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
   Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
   unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
   unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn,
   // The lane index does not have any bits in the encoding, because it can only
   // be 0.
   Inst.addOperand(MCOperand::createImm(0));
   Inst.addOperand(MCOperand::createImm(rotate));
 
   return S;
 }
 
-static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
+                              const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 16, 4);
   unsigned Rt = fieldFromInstruction(Val, 12, 4);
   unsigned Rm = fieldFromInstruction(Val, 0, 4);
   Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
   unsigned Cond = fieldFromInstruction(Val, 28, 4);
 
if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
-                                            uint64_t Address, const void *Decoder) {
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned CRm = fieldFromInstruction(Val, 0, 4);
   unsigned opc1 = fieldFromInstruction(Val, 4, 4);
   unsigned cop = fieldFromInstruction(Val, 8, 4);
   unsigned Rt = fieldFromInstruction(Val, 12, 4);
   unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
 
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
   }
   Inst.addOperand(MCOperand::createImm(CRm));
 
   return S;
 }
 
 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   const FeatureBitset &featureBits =
       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
   DecodeStatus S = MCDisassembler::Success;
 
   // Add explicit operand for the destination sysreg, for cases where
   // we have to model it for code generation purposes.
   switch (Inst.getOpcode()) {
   case ARM::VMSR_FPSCR_NZCVQC:
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
   }
 
   return S;
 }
 
 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   if (Val == 0 && !zeroPermitted)
     S = MCDisassembler::Fail;
 
   uint64_t DecVal;
   if (isSigned)
     DecVal = SignExtend32<size + 1>(Val << 1);
   else
     DecVal = (Val << 1);
 
   if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
                                 Decoder))
     Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
   return S;
 }
 
 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
 
   uint64_t LocImm = Inst.getOperand(0).getImm();
   Val = LocImm + (2 << Val);
   if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
                                 Decoder))
     Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   if (Val >= ARMCC::AL)  // also exclude the non-condition NV
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (Inst.getOpcode() == ARM::MVE_LCTP)
     return S;
 
   unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
                  fieldFromInstruction(Insn, 1, 10) << 1;
   switch (Inst.getOpcode()) {
case ARM::MVE_DLSTP_64:
     }
     break;
   }
   return S;
 }
 
 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (Val == 0)
     Val = 32;
 
   Inst.addOperand(MCOperand::createImm(Val));
 
   return S;
 }
 
 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   if ((RegNo) + 1 > 11)
     return MCDisassembler::Fail;
 
   unsigned Register = GPRDecoderTable[(RegNo) + 1];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                                uint64_t Address,
+                                                const MCDisassembler *Decoder) {
   if ((RegNo) > 14)
     return MCDisassembler::Fail;
 
   unsigned Register = GPRDecoderTable[(RegNo)];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus
 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   if (RegNo == 15) {
     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
     return MCDisassembler::Success;
   }
 
   unsigned Register = GPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
 
   if (RegNo == 13)
     return MCDisassembler::SoftFail;
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   Inst.addOperand(MCOperand::createImm(ARMCC::AL));
   Inst.addOperand(MCOperand::createReg(0));
   if (Inst.getOpcode() == ARM::VSCCLRMD) {
     unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) |
                        (fieldFromInstruction(Insn, 12, 4) << 8) |
                        (fieldFromInstruction(Insn, 22, 1) << 12);
if (Inst.getOpcode() == ARM::VSCCLRMD) {
     }
   }
   Inst.addOperand(MCOperand::createReg(ARM::VPR));
 
   return S;
 }
 
 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                              const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
 
   unsigned Register = QPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static const uint16_t QQPRDecoderTable[] = {
      ARM::Q0_Q1,  ARM::Q1_Q2,  ARM::Q2_Q3,  ARM::Q3_Q4,
      ARM::Q4_Q5,  ARM::Q5_Q6,  ARM::Q6_Q7
 };
 
 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 6)
     return MCDisassembler::Fail;
 
   unsigned Register = QQPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static const uint16_t QQQQPRDecoderTable[] = {
      ARM::Q0_Q1_Q2_Q3,  ARM::Q1_Q2_Q3_Q4,  ARM::Q2_Q3_Q4_Q5,
      ARM::Q3_Q4_Q5_Q6,  ARM::Q4_Q5_Q6_Q7
 };
 
 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 4)
     return MCDisassembler::Fail;
 
   unsigned Register = QQQQPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   // Parse VPT mask and encode it in the MCInst as an immediate with the same
   // format as the it_mask.  That is, from the second 'e|t' encode 'e' as 1 and
   // 't' as 0 and finish with a 1.
   unsigned Imm = 0;
   // We always start with a 't'.
   unsigned CurBit = 0;
static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
   }
 
   Inst.addOperand(MCOperand::createImm(Imm));
 
   return S;
 }
 
 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   // The vpred_r operand type includes an MQPR register field derived
   // from the encoding. But we don't actually want to add an operand
   // to the MCInst at this stage, because AddThumbPredicate will do it
   // later, and will infer the register number from the TIED_TO
   // constraint. So this is a deliberately empty decoder method that
   // will inhibit the auto-generated disassembly code from adding an
   // operand at all.
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst,
-                                                      unsigned Val,
-                                                      uint64_t Address,
-                                                      const void *Decoder) {
+static DecodeStatus
+DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst,
-                                                      unsigned Val,
-                                                      uint64_t Address,
-                                                      const void *Decoder) {
+static DecodeStatus
+DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   unsigned Code;
   switch (Val & 0x3) {
   case 0:
     Code = ARMCC::GE;
     break;
   case 1:
     Code = ARMCC::LT;
     break;
   case 2:
     Code = ARMCC::GT;
     break;
   case 3:
     Code = ARMCC::LE;
     break;
   }
   Inst.addOperand(MCOperand::createImm(Code));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst,
-                                                      unsigned Val,
-                                                      uint64_t Address,
-                                                      const void *Decoder) {
+static DecodeStatus
+DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val,
-                                                     uint64_t Address,
-                                                     const void *Decoder) {
+static DecodeStatus
+DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   unsigned Code;
   switch (Val) {
   default:
     return MCDisassembler::Fail;
   case 0:
     Code = ARMCC::EQ;
     break;
   case 1:
case 7:
     break;
   }
 
   Inst.addOperand(MCOperand::createImm(Code));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
-                                         uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned DecodedVal = 64 - Val;
 
   switch (Inst.getOpcode()) {
   case ARM::MVE_VCVTf16s16_fix:
   case ARM::MVE_VCVTs16f16_fix:
   case ARM::MVE_VCVTf16u16_fix:
static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
   case ARM::VLDR_P0_pre:
   case ARM::VLDR_P0_post:
     return ARM::P0;
   default:
     return 0;
   }
 }
 
-template<bool Writeback>
+template <bool Writeback>
 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   switch (Inst.getOpcode()) {
   case ARM::VSTR_FPSCR_pre:
   case ARM::VSTR_FPSCR_NZCVQC_pre:
   case ARM::VLDR_FPSCR_pre:
   case ARM::VLDR_FPSCR_NZCVQC_pre:
   case ARM::VSTR_FPSCR_off:
   case ARM::VSTR_FPSCR_NZCVQC_off:
   case ARM::VLDR_FPSCR_off:
if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(ARMCC::AL));
   Inst.addOperand(MCOperand::createReg(0));
 
   return S;
 }
 
-static inline DecodeStatus DecodeMVE_MEM_pre(
-  MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder,
-  unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
+static inline DecodeStatus
+DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address,
+                  const MCDisassembler *Decoder, unsigned Rn,
+                  OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Qd = fieldFromInstruction(Val, 13, 3);
   unsigned addr = fieldFromInstruction(Val, 0, 7) |
                   (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
 
   if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 template <int shift>
 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
                            fieldFromInstruction(Val, 16, 3),
                            DecodetGPRRegisterClass,
                            DecodeTAddrModeImm7<shift>);
 }
 
 template <int shift>
 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
                            fieldFromInstruction(Val, 16, 4),
                            DecoderGPRRegisterClass,
                            DecodeT2AddrModeImm7<shift,1>);
 }
 
 template <int shift>
 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
                            fieldFromInstruction(Val, 17, 3),
                            DecodeMQPRRegisterClass,
                            DecodeMveAddrModeQ<shift>);
 }
 
-template<unsigned MinLog, unsigned MaxLog>
+template <unsigned MinLog, unsigned MaxLog>
 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (Val < MinLog || Val > MaxLog)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(1LL << Val));
   return S;
 }
 
-template<unsigned start>
-static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
-                                                    uint64_t Address,
-                                                    const void *Decoder) {
+template <unsigned start>
+static DecodeStatus
+DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+                                const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   Inst.addOperand(MCOperand::createImm(start + Val));
 
   return S;
 }
 
 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
-                                         uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
                  fieldFromInstruction(Insn, 13, 3));
   unsigned index = fieldFromInstruction(Insn, 4, 1);
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
-                                         uint64_t Address, const void *Decoder) {
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
                  fieldFromInstruction(Insn, 13, 3));
   unsigned index = fieldFromInstruction(Insn, 4, 1);
 
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-static DecodeStatus DecodeMVEOverlappingLongShift(
-  MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
+                              const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
   unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
   unsigned Rm = fieldFromInstruction(Insn, 12, 4);
 
   if (RdaHi == 14) {
     // This value of RdaHi (really indicating pc, because RdaHi has to
if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
     unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
     // Saturate, the bit position for saturation
     Inst.addOperand(MCOperand::createImm(Saturate));
   }
 
   return S;
 }
 
-static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                      const void *Decoder) {
+static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
                  fieldFromInstruction(Insn, 13, 3));
   unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
                  fieldFromInstruction(Insn, 1, 3));
   unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
 
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
-template<bool scalar, OperandDecoder predicate_decoder>
+template <bool scalar, OperandDecoder predicate_decoder>
 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   Inst.addOperand(MCOperand::createReg(ARM::VPR));
   unsigned Qn = fieldFromInstruction(Insn, 17, 3);
   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
     return MCDisassembler::Fail;
 
   unsigned fc;
 
static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
   Inst.addOperand(MCOperand::createImm(ARMVCC::None));
   Inst.addOperand(MCOperand::createReg(0));
   Inst.addOperand(MCOperand::createImm(0));
 
   return S;
 }
 
 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   Inst.addOperand(MCOperand::createReg(ARM::VPR));
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   return S;
 }
 
-static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                   const void *Decoder) {
+static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   Inst.addOperand(MCOperand::createReg(ARM::VPR));
   Inst.addOperand(MCOperand::createReg(ARM::VPR));
   return S;
 }
 
 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
   const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
                          fieldFromInstruction(Insn, 12, 3) << 8 |
                          fieldFromInstruction(Insn, 0, 8);
   const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);

llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp

static const uint16_t GPRDecoderTable[] = {
     AVR::R7,  AVR::R8,  AVR::R9,  AVR::R10, AVR::R11, AVR::R12, AVR::R13,
     AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
     AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27,
     AVR::R28, AVR::R29, AVR::R30, AVR::R31,
 };
 
 static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Register = GPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
 
   unsigned Register = GPRDecoderTable[RegNo + 16];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   // Note: this function must be defined but does not seem to be called.
   assert(false && "unimplemented: PTRREGS register class");
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 
 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 
 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 
 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
-                                     uint64_t Address, const void *Decoder);
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder);
 
 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
-                              const void *Decoder);
+                              const MCDisassembler *Decoder);
 
 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                const void *Decoder);
+                                const MCDisassembler *Decoder);
 
 static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 
 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 
 static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                const void *Decoder);
+                                const MCDisassembler *Decoder);
 
 static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 
 #include "AVRGenDisassemblerTables.inc"
 
 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   unsigned addr = 0;
   addr |= fieldFromInstruction(Insn, 0, 4);
   addr |= fieldFromInstruction(Insn, 9, 2) << 4;
   unsigned reg = fieldFromInstruction(Insn, 4, 5);
   Inst.addOperand(MCOperand::createImm(addr));
   if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   unsigned addr = 0;
   addr |= fieldFromInstruction(Insn, 0, 4);
   addr |= fieldFromInstruction(Insn, 9, 2) << 4;
   unsigned reg = fieldFromInstruction(Insn, 4, 5);
   if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(addr));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   unsigned addr = fieldFromInstruction(Insn, 3, 5);
   unsigned b = fieldFromInstruction(Insn, 0, 3);
   Inst.addOperand(MCOperand::createImm(addr));
   Inst.addOperand(MCOperand::createImm(b));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
-                                     uint64_t Address, const void *Decoder) {
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   // Call targets need to be shifted left by one so this needs a custom
   // decoder.
   Inst.addOperand(MCOperand::createImm(Field << 1));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
-                              const void *Decoder) {
+                              const MCDisassembler *Decoder) {
   unsigned d = fieldFromInstruction(Insn, 4, 5);
   if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                const void *Decoder) {
+                                const MCDisassembler *Decoder) {
   if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(AVR::R31R30));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   unsigned d = fieldFromInstruction(Insn, 4, 3) + 16;
   unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;
   if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   unsigned r = fieldFromInstruction(Insn, 4, 4) * 2;
   unsigned d = fieldFromInstruction(Insn, 0, 4) * 2;
   if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                const void *Decoder) {
+                                const MCDisassembler *Decoder) {
   unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24; // starts at r24:r25
   unsigned k = 0;
   k |= fieldFromInstruction(Insn, 0, 4);
   k |= fieldFromInstruction(Insn, 6, 2) << 4;
   if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(k));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16;
   unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16;
   if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
   if (DecodeGPR8RegisterClass(Inst, rr, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
if (Result != MCDisassembler::Fail) {
       return Result;
     }
 
     return MCDisassembler::Fail;
   }
 }
 
 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
-                                   const void *Decoder);
+                                   const MCDisassembler *Decoder);

llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp

 }
 
 static const unsigned GPRDecoderTable[] = {
     BPF::R0,  BPF::R1,  BPF::R2,  BPF::R3,  BPF::R4,  BPF::R5,
     BPF::R6,  BPF::R7,  BPF::R8,  BPF::R9,  BPF::R10, BPF::R11};
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t /*Address*/,
-                                           const void * /*Decoder*/) {
+                                           const MCDisassembler * /*Decoder*/) {
   if (RegNo > 11)
     return MCDisassembler::Fail;
 
   unsigned Reg = GPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static const unsigned GPR32DecoderTable[] = {
     BPF::W0,  BPF::W1,  BPF::W2,  BPF::W3,  BPF::W4,  BPF::W5,
     BPF::W6,  BPF::W7,  BPF::W8,  BPF::W9,  BPF::W10, BPF::W11};
 
-static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
-                                             uint64_t /*Address*/,
-                                             const void * /*Decoder*/) {
+static DecodeStatus
+DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
+                         const MCDisassembler * /*Decoder*/) {
   if (RegNo > 11)
     return MCDisassembler::Fail;
 
   unsigned Reg = GPR32DecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   unsigned Register = (Insn >> 16) & 0xf;
   if (Register > 11)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
   unsigned Offset = (Insn & 0xffff);
   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
 
case BPF::LD_IND_W: {
     break;
   }
   }
 
   return Result;
 }
 
 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
-                                   const void *Decoder);
+                                   const MCDisassembler *Decoder);

llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp

static const uint16_t FPR128DecoderTable[] = {
     CSKY::F10_128, CSKY::F11_128, CSKY::F12_128, CSKY::F13_128, CSKY::F14_128,
     CSKY::F15_128, CSKY::F16_128, CSKY::F17_128, CSKY::F18_128, CSKY::F19_128,
     CSKY::F20_128, CSKY::F21_128, CSKY::F22_128, CSKY::F23_128, CSKY::F24_128,
     CSKY::F25_128, CSKY::F26_128, CSKY::F27_128, CSKY::F28_128, CSKY::F29_128,
     CSKY::F30_128, CSKY::F31_128};
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodesFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo >= 16)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodesFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo >= 16)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodesFPR64_VRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   if (RegNo >= 16)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodesFPR128RegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo >= 16)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR128DecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodesGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo >= 16)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo >= 8)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo != 14)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   const FeatureBitset &FeatureBits =
-      static_cast<const MCDisassembler *>(Decoder)
-          ->getSubtargetInfo()
-          .getFeatureBits();
+      Decoder->getSubtargetInfo().getFeatureBits();
   bool hasHighReg = FeatureBits[CSKY::FeatureHighreg];
 
   if (RegNo >= 32 || (!hasHighReg && RegNo >= 16))
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(GPRPairDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 template <unsigned N, unsigned S>
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
-                                      int64_t Address, const void *Decoder) {
+                                      int64_t Address,
+                                      const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   Inst.addOperand(MCOperand::createImm(Imm << S));
   return MCDisassembler::Success;
 }
 
 template <unsigned N>
 static DecodeStatus decodeOImmOperand(MCInst &Inst, uint64_t Imm,
-                                      int64_t Address, const void *Decoder) {
+                                      int64_t Address,
+                                      const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   Inst.addOperand(MCOperand::createImm(Imm + 1));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address,
-                                    const void *Decoder) {
+                                    const MCDisassembler *Decoder) {
   assert(isUInt<8>(Imm) && "Invalid immediate");
   if ((Imm >> 7) & 0x1) {
     Inst.addOperand(MCOperand::createImm((Imm & 0x7F) << 2));
   } else {
     uint64_t V = ((Imm ^ 0xFFFFFFFF) & 0xFF);
     Inst.addOperand(MCOperand::createImm(V << 2));
   }
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeJMPIXImmOperand(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   assert(isUInt<2>(Imm) && "Invalid immediate");
 
   if (Imm == 0)
     Inst.addOperand(MCOperand::createImm(16));
   else if (Imm == 1)
     Inst.addOperand(MCOperand::createImm(24));
   else if (Imm == 2)
     Inst.addOperand(MCOperand::createImm(32));
   else if (Imm == 3)
     Inst.addOperand(MCOperand::createImm(40));
   else
     return MCDisassembler::Fail;
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeRegSeqOperand(MCInst &Inst, uint64_t Imm,
-                                        int64_t Address, const void *Decoder) {
+                                        int64_t Address,
+                                        const MCDisassembler *Decoder) {
   assert(isUInt<10>(Imm) && "Invalid immediate");
 
   auto Imm5 = Imm & 0x1f;
   auto Ry = (Imm >> 5) & 0x1f;
 
   if (DecodeGPRRegisterClass(Inst, Ry, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Ry + Imm5]));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeRegSeqOperandF1(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   assert(isUInt<10>(Imm) && "Invalid immediate");
 
   auto Imm5 = Imm & 0x1f;
   auto Ry = (Imm >> 5) & 0x1f;
 
   if (DecodesFPR32RegisterClass(Inst, Ry, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[Ry + Imm5]));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeRegSeqOperandD1(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   assert(isUInt<10>(Imm) && "Invalid immediate");
 
   auto Imm5 = Imm & 0x1f;
   auto Ry = (Imm >> 5) & 0x1f;
 
   if (DecodesFPR64RegisterClass(Inst, Ry, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[Ry + Imm5]));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeRegSeqOperandF2(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   assert(isUInt<10>(Imm) && "Invalid immediate");
 
   auto Imm5 = Imm & 0x1f;
   auto Ry = (Imm >> 5) & 0x1f;
 
   if (DecodeFPR32RegisterClass(Inst, Ry, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[Ry + Imm5]));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeRegSeqOperandD2(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   assert(isUInt<10>(Imm) && "Invalid immediate");
 
   auto Imm5 = Imm & 0x1f;
   auto Ry = (Imm >> 5) & 0x1f;
 
   if (DecodeFPR64RegisterClass(Inst, Ry, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[Ry + Imm5]));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeImmShiftOpValue(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(Log2(Imm)));
   return MCDisassembler::Success;
 }
 
 template <unsigned N, unsigned S>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
-                                      int64_t Address, const void *Decoder) {
+                                      int64_t Address,
+                                      const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   // Sign-extend the number in the bottom N bits of Imm
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) << S));
   return MCDisassembler::Success;
 }
 
 #include "CSKYGenDisassemblerTables.inc"
 
DecodeStatus CSKYDisassembler::handleCROperand(MCInst &MI) const {
   case CSKY::INS32:
     MI.getOperand(3).setImm(MI.getOperand(3).getImm() +
                             MI.getOperand(4).getImm());
     return MCDisassembler::Success;
   }
 }
 
 static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address,
-                                   const void *DisAsm,
+                                   const MCDisassembler *DisAsm,
                                    const MCSubtargetInfo &STI) {
   LLVM_DEBUG(dbgs() << "Trying CSKY 32-bit fpuv3 table :\n");
   if (!STI.getFeatureBits()[CSKY::FeatureFPUV3_HF] &&
       !STI.getFeatureBits()[CSKY::FeatureFPUV3_SF] &&
       !STI.getFeatureBits()[CSKY::FeatureFPUV3_DF])
     return false;
 
   DecodeStatus Result =

llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

bool Success =
       Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
           Bits);
   assert(Success);
   (void)Success;
   uint64_t Upper26 = static_cast<uint64_t>(Bits);
   uint64_t Operand = Upper26 | Lower6;
   return Operand;
 }
-static HexagonDisassembler const &disassembler(void const *Decoder) {
+static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
   return *static_cast<HexagonDisassembler const *>(Decoder);
 }
 template <size_t T>
-static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
+static void signedDecoder(MCInst &MI, unsigned tmp,
+                          const MCDisassembler *Decoder) {
   HexagonDisassembler const &Disassembler = disassembler(Decoder);
   int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
   int64_t Extended = SignExtend64<32>(FullValue);
   HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
 }
 }
 
 // Forward declare these because the auto-generated code will reference them.
 // Definitions are further down.
 
 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
-static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
-                                                      unsigned RegNo,
-                                                      uint64_t Address,
-                                                      const void *Decoder);
-static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
-                                                   uint64_t Address,
-                                                   const void *Decoder);
+                                               const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+                                  const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
-static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                  uint64_t Address,
-                                                  const void *Decoder);
+                                             const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                              const MCDisassembler *Decoder);
 static DecodeStatus
 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                         uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
-static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst,
-                                              unsigned RegNo,
+                                             const MCDisassembler *Decoder);
+static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                 uint64_t Address,
-                                                const void *Decoder);
+                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t Address,
-                                                 const void *Decoder);
+                                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t Address,
-                                                 const void *Decoder);
-static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
-                                                   uint64_t Address,
-                                                   const void *Decoder);
+                                                 const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t Address,
-                                                 const void *Decoder);
-
+                                                 const MCDisassembler *Decoder);
 
 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
-                                       uint64_t Address, const void *Decoder);
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder);
 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
-                                    uint64_t /*Address*/, const void *Decoder);
+                                    uint64_t /*Address*/,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
-                                    const void *Decoder);
+                                    const MCDisassembler *Decoder);
 #include "HexagonDepDecoders.inc"
 #include "HexagonGenDisassemblerTables.inc"
 
 static MCDisassembler *createHexagonDisassembler(const Target &T,
                                                  const MCSubtargetInfo &STI,
                                                  MCContext &Ctx) {
   return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
 }
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
   if (RegNo < Table.size()) {
     Inst.addOperand(MCOperand::createReg(Table[RegNo]));
     return MCDisassembler::Success;
   }
 
   return MCDisassembler::Fail;
 }
 
-static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
-                                                   uint64_t Address,
-                                                   const void *Decoder) {
+static DecodeStatus
+DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder) {
   return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   static const MCPhysReg IntRegDecoderTable[] = {
       Hexagon::R0,  Hexagon::R1,  Hexagon::R2,  Hexagon::R3,  Hexagon::R4,
       Hexagon::R5,  Hexagon::R6,  Hexagon::R7,  Hexagon::R8,  Hexagon::R9,
       Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
       Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
       Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
       Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
       Hexagon::R30, Hexagon::R31};
 
   return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
 }
 
-static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
-                                                      unsigned RegNo,
-                                                      uint64_t Address,
-                                                      const void *Decoder) {
+static DecodeStatus
+DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+                                  const MCDisassembler *Decoder) {
   static const MCPhysReg GeneralSubRegDecoderTable[] = {
       Hexagon::R0,  Hexagon::R1,  Hexagon::R2,  Hexagon::R3,
       Hexagon::R4,  Hexagon::R5,  Hexagon::R6,  Hexagon::R7,
       Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
       Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
   };
 
   return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
 }
 
 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t /*Address*/,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   static const MCPhysReg HvxVRDecoderTable[] = {
       Hexagon::V0,  Hexagon::V1,  Hexagon::V2,  Hexagon::V3,  Hexagon::V4,
       Hexagon::V5,  Hexagon::V6,  Hexagon::V7,  Hexagon::V8,  Hexagon::V9,
       Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
       Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
       Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
       Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
       Hexagon::V30, Hexagon::V31};
 
   return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
 }
 
-static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                  uint64_t /*Address*/,
-                                                  const void *Decoder) {
+static DecodeStatus
+DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+                              const MCDisassembler *Decoder) {
   static const MCPhysReg DoubleRegDecoderTable[] = {
       Hexagon::D0,  Hexagon::D1,  Hexagon::D2,  Hexagon::D3,
       Hexagon::D4,  Hexagon::D5,  Hexagon::D6,  Hexagon::D7,
       Hexagon::D8,  Hexagon::D9,  Hexagon::D10, Hexagon::D11,
       Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
 
   return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
 }
 
-static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(
-    MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) {
+static DecodeStatus
+DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
+                                         uint64_t /*Address*/,
+                                         const MCDisassembler *Decoder) {
   static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
       Hexagon::D0, Hexagon::D1, Hexagon::D2,  Hexagon::D3,
       Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
 
   return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
 }
 
 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t /*Address*/,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   static const MCPhysReg HvxWRDecoderTable[] = {
       Hexagon::W0,   Hexagon::WR0,  Hexagon::W1,   Hexagon::WR1,  Hexagon::W2,
       Hexagon::WR2,  Hexagon::W3,   Hexagon::WR3,  Hexagon::W4,   Hexagon::WR4,
       Hexagon::W5,   Hexagon::WR5,  Hexagon::W6,   Hexagon::WR6,  Hexagon::W7,
       Hexagon::WR7,  Hexagon::W8,   Hexagon::WR8,  Hexagon::W9,   Hexagon::WR9,
       Hexagon::W10,  Hexagon::WR10, Hexagon::W11,  Hexagon::WR11, Hexagon::W12,
       Hexagon::WR12, Hexagon::W13,  Hexagon::WR13, Hexagon::W14,  Hexagon::WR14,
       Hexagon::W15,  Hexagon::WR15,
   };
 
   return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
 }
 
-LLVM_ATTRIBUTE_UNUSED  // Suppress warning temporarily.
-static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst,
-                                              unsigned RegNo,
-                                              uint64_t /*Address*/,
-                                              const void *Decoder) {
+LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
+    static DecodeStatus
+    DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
+                              const MCDisassembler *Decoder) {
   static const MCPhysReg HvxVQRDecoderTable[] = {
       Hexagon::VQ0,  Hexagon::VQ1,  Hexagon::VQ2,  Hexagon::VQ3,
       Hexagon::VQ4,  Hexagon::VQ5,  Hexagon::VQ6,  Hexagon::VQ7};
 
   return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
 }
 
 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                 uint64_t /*Address*/,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
                                                   Hexagon::P2, Hexagon::P3};
 
   return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
 }
 
 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t /*Address*/,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
                                                 Hexagon::Q2, Hexagon::Q3};
 
   return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
 }
 
 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t /*Address*/,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   using namespace Hexagon;
 
   static const MCPhysReg CtrlRegDecoderTable[] = {
     /*  0 */  SA0,        LC0,        SA1,        LC1,
     /*  4 */  P3_0,       C5,         M0,         M1,
     /*  8 */  USR,        PC,         UGP,        GP,
     /* 12 */  CS0,        CS1,        UPCYCLELO,  UPCYCLEHI,
     /* 16 */  FRAMELIMIT, FRAMEKEY,   PKTCOUNTLO, PKTCOUNTHI,
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
   if (CtrlRegDecoderTable[RegNo] == NoRegister)
     return MCDisassembler::Fail;
 
   unsigned Register = CtrlRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
-                                                 uint64_t /*Address*/,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
+                             const MCDisassembler *Decoder) {
   using namespace Hexagon;
 
   static const MCPhysReg CtrlReg64DecoderTable[] = {
     /*  0 */  C1_0,       0,          C3_2,       0,
     /*  4 */  C5_4,       0,          C7_6,       0,
     /*  8 */  C9_8,       0,          C11_10,     0,
     /* 12 */  CS,         0,          UPCYCLE,    0,
     /* 16 */  C17_16,     0,          PKTCOUNT,   0,
DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
 
   unsigned Register = CtrlReg64DecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t /*Address*/,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   unsigned Register = 0;
   switch (RegNo) {
   case 0:
     Register = Hexagon::M0;
     break;
   case 1:
     Register = Hexagon::M1;
     break;
   default:
     return MCDisassembler::Fail;
   }
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
                                        uint64_t /*Address*/,
-                                       const void *Decoder) {
+                                       const MCDisassembler *Decoder) {
   HexagonDisassembler const &Disassembler = disassembler(Decoder);
   int64_t FullValue = fullValue(Disassembler, MI, tmp);
   assert(FullValue >= 0 && "Negative in unsigned decoder");
   HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
   return MCDisassembler::Success;
 }
 
 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
-                                    uint64_t /*Address*/, const void *Decoder) {
+                                    uint64_t /*Address*/,
+                                    const MCDisassembler *Decoder) {
   HexagonDisassembler const &Disassembler = disassembler(Decoder);
   unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
   tmp = SignExtend64(tmp, Bits);
   signedDecoder<32>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
 
 // custom decoder for various jump/call immediates
 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
-                                    const void *Decoder) {
+                                    const MCDisassembler *Decoder) {
   HexagonDisassembler const &Disassembler = disassembler(Decoder);
   unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
   // r13_2 is not extendable, so if there are no extent bits, it's r13_2
   if (Bits == 0)
     Bits = 15;
   uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
   uint32_t Extended = FullValue + Address;
   if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4))
static const uint16_t SysRegDecoderTable[] = {
     Hexagon::S69,        Hexagon::S70,       Hexagon::S71,
     Hexagon::S72,        Hexagon::S73,       Hexagon::S74,
     Hexagon::S75,        Hexagon::S76,       Hexagon::S77,
     Hexagon::S78,        Hexagon::S79,       Hexagon::S80,
 };
 
 static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t /*Address*/,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0]))
     return MCDisassembler::Fail;
 
   if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
     return MCDisassembler::Fail;
 
   unsigned Register = SysRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static const uint16_t SysReg64DecoderTable[] = {
     Hexagon::SGP1_0, Hexagon::S3_2,   Hexagon::S5_4,   Hexagon::S7_6,
     Hexagon::S9_8,   Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
     Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
     Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
     Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
     Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
     Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
     Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
     Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
     Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
 };
 
-static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
-                                                 uint64_t /*Address*/,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
+                             const MCDisassembler *Decoder) {
   RegNo = RegNo >> 1;
   if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0]))
     return MCDisassembler::Fail;
 
   if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
     return MCDisassembler::Fail;
 
   unsigned Register = SysReg64DecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                                 uint64_t /*Address*/,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
+                             const MCDisassembler *Decoder) {
   using namespace Hexagon;
 
   static const MCPhysReg GuestRegDecoderTable[] = {
     /*  0 */ GELR,      GSR,        GOSP,       G3,
     /*  4 */ G4,        G5,         G6,         G7,
     /*  8 */ G8,        G9,         G10,        G11,
     /* 12 */ G12,       G13,        G14,        G15,
     /* 16 */ GPMUCNT4,  GPMUCNT5,   GPMUCNT6,   GPMUCNT7,
     /* 20 */ G20,       G21,        G22,        G23,
     /* 24 */ GPCYCLELO, GPCYCLEHI,  GPMUCNT0,   GPMUCNT1,
     /* 28 */ GPMUCNT2,  GPMUCNT3,   G30,        G31
   };
 
   if (RegNo >= array_lengthof(GuestRegDecoderTable))
     return MCDisassembler::Fail;
   if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
     return MCDisassembler::Fail;
 
   unsigned Register = GuestRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
-                                                   uint64_t /*Address*/,
-                                                   const void *Decoder) {
+static DecodeStatus
+DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
+                               const MCDisassembler *Decoder) {
   using namespace Hexagon;
 
   static const MCPhysReg GuestReg64DecoderTable[] = {
     /*  0 */ G1_0,      0,          G3_2,       0,
     /*  4 */ G5_4,      0,          G7_6,       0,
     /*  8 */ G9_8,      0,          G11_10,     0,
     /* 12 */ G13_12,    0,          G15_14,     0,
     /* 16 */ G17_16,    0,          G19_18,     0,

llvm/lib/Target/Hexagon/HexagonDepDecoders.inc

 //===----------------------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 // Automatically generated file, do not edit!
 //===----------------------------------------------------------------------===//
 
 
 #if defined(__clang__)
 #pragma clang diagnostic push
 #pragma clang diagnostic ignored "-Wunused-function"
 #endif
 
-static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const MCDisassembler *Decoder) {
   signedDecoder<6>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                    const MCDisassembler *Decoder) {
   signedDecoder<12>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                    const MCDisassembler *Decoder) {
   signedDecoder<13>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                    const MCDisassembler *Decoder) {
   signedDecoder<14>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const MCDisassembler *Decoder) {
   signedDecoder<3>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const MCDisassembler *Decoder) {
   signedDecoder<4>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const MCDisassembler *Decoder) {
   signedDecoder<5>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const MCDisassembler *Decoder) {
   signedDecoder<6>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const MCDisassembler *Decoder) {
   signedDecoder<7>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const MCDisassembler *Decoder) {
   signedDecoder<9>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
-static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp,
-    uint64_t, const void *Decoder) {
+static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
+                                   const MCDisassembler *Decoder) {
   signedDecoder<8>(MI, tmp, Decoder);
   return MCDisassembler::Success;
 }
 
 #if defined(__clang__)
 #pragma clang diagnostic pop
 #endif
 

llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp

 
 LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
     : MCDisassembler(STI, Ctx) {}
 
 // Forward declare because the autogenerated code will reference this.
 // Definition is further down.
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 
 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 
 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 
 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 
 static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 
 #include "LanaiGenDisassemblerTables.inc"
 
 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t &Size,
                                       uint32_t &Insn) {
   // We want to read exactly 4 bytes of data.
   if (Bytes.size() < 4) {
     Size = 0;
static const unsigned GPRDecoderTable[] = {
     Lanai::R6,  Lanai::R7,  Lanai::RV,  Lanai::R9,  Lanai::RR1, Lanai::RR2,
     Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
     Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
     Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
     Lanai::R30, Lanai::R31};
 
 DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                     uint64_t /*Address*/,
-                                    const void * /*Decoder*/) {
+                                    const MCDisassembler * /*Decoder*/) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = GPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   // RI memory values encoded using 23 bits:
   //   5 bit register, 16 bit constant
   unsigned Register = (Insn >> 18) & 0x1f;
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
   unsigned Offset = (Insn & 0xffff);
   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   // RR memory values encoded using 20 bits:
   //   5 bit register, 5 bit register, 2 bit PQ, 3 bit ALU operator, 5 bit JJJJJ
   unsigned Register = (Insn >> 15) & 0x1f;
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
   Register = (Insn >> 10) & 0x1f;
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   // RI memory values encoded using 17 bits:
   //   5 bit register, 10 bit constant
   unsigned Register = (Insn >> 12) & 0x1f;
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
   unsigned Offset = (Insn & 0x3ff);
   Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset)));
 
   return MCDisassembler::Success;
 }
 
 static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch,
                                      uint64_t Address, uint64_t Offset,
                                      uint64_t Width, MCInst &MI,
-                                     const void *Decoder) {
-  const MCDisassembler *Dis = static_cast<const MCDisassembler *>(Decoder);
-  return Dis->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset,
+                                     const MCDisassembler *Decoder) {
+  return Decoder->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset,
                                            Width);
 }
 
 static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   if (!tryAddingSymbolicOperand(Insn + Address, false, Address, 2, 23, MI,
                                 Decoder))
     MI.addOperand(MCOperand::createImm(Insn));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   unsigned Offset = (Insn & 0xffff);
   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (Val >= LPCC::UNKNOWN)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }

llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchDisassembler() {
   TargetRegistry::RegisterMCDisassembler(getTheLoongArch32Target(),
                                          createLoongArchDisassembler);
   TargetRegistry::RegisterMCDisassembler(getTheLoongArch64Target(),
                                          createLoongArchDisassembler);
 }
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo));
   return MCDisassembler::Success;
 }
 
 template <unsigned N, int P = 0>
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
-                                      int64_t Address, const void *Decoder) {
+                                      int64_t Address,
+                                      const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   Inst.addOperand(MCOperand::createImm(Imm + P));
   return MCDisassembler::Success;
 }
 
 template <unsigned N, unsigned S = 0>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
-                                      int64_t Address, const void *Decoder) {
+                                      int64_t Address,
+                                      const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   // Sign-extend the number in the bottom <N> bits of Imm, then shift left <S>
   // bits.
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) << S));
   return MCDisassembler::Success;
 }
 
 #include "LoongArchGenDisassemblerTables.inc"

llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp

static const unsigned GR8DecoderTable[] = {
   MSP430::PCB,  MSP430::SPB,  MSP430::SRB,  MSP430::CGB,
   MSP430::R4B,  MSP430::R5B,  MSP430::R6B,  MSP430::R7B,
   MSP430::R8B,  MSP430::R9B,  MSP430::R10B, MSP430::R11B,
   MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B
 };
 
 static DecodeStatus DecodeGR8RegisterClass(MCInst &MI, uint64_t RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
 
   unsigned Reg = GR8DecoderTable[RegNo];
   MI.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static const unsigned GR16DecoderTable[] = {
   MSP430::PC,  MSP430::SP,  MSP430::SR,  MSP430::CG,
   MSP430::R4,  MSP430::R5,  MSP430::R6,  MSP430::R7,
   MSP430::R8,  MSP430::R9,  MSP430::R10, MSP430::R11,
   MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
 };
 
 static DecodeStatus DecodeGR16RegisterClass(MCInst &MI, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
 
   unsigned Reg = GR16DecoderTable[RegNo];
   MI.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address,
-                                const void *Decoder);
+                                const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits,
                                      uint64_t Address,
-                                     const void *Decoder);
+                                     const MCDisassembler *Decoder);
 
 #include "MSP430GenDisassemblerTables.inc"
 
 static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address,
-                                const void *Decoder) {
+                                const MCDisassembler *Decoder) {
   int64_t Imm;
   switch (Bits) {
   default:
     llvm_unreachable("Invalid immediate value");
   case 0x22: Imm =  4; break;
   case 0x32: Imm =  8; break;
   case 0x03: Imm =  0; break;
   case 0x13: Imm =  1; break;
   case 0x23: Imm =  2; break;
   case 0x33: Imm = -1; break;
   }
   MI.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits,
                                      uint64_t Address,
-                                     const void *Decoder) {
+                                     const MCDisassembler *Decoder) {
   unsigned Reg = Bits & 15;
   unsigned Imm = Bits >> 4;
 
   if (DecodeGR16RegisterClass(MI, Reg, Address, Decoder) !=
       MCDisassembler::Success)
     return MCDisassembler::Fail;
   
   MI.addOperand(MCOperand::createImm((int16_t)Imm));

llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
                               raw_ostream &CStream) const override;
 };
 
 } // end anonymous namespace
 
 // Forward declare these because the autogenerated code will reference them.
 // Definitions are further down.
-static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
-                                                 unsigned RegNo,
+static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t Address,
-                                                 const void *Decoder);
+                                                 const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
-                                                   unsigned RegNo,
-                                                   uint64_t Address,
-                                                   const void *Decoder);
+static DecodeStatus
+DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
-                                                    unsigned RegNo,
-                                                    uint64_t Address,
-                                                    const void *Decoder);
+static DecodeStatus
+DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                                const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 
-static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
-                                           unsigned Insn,
+static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
-                                            unsigned RegNo,
+static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
-                                           unsigned RegNo,
+static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
-                                           unsigned RegNo,
+static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
-                                              unsigned Insn,
+static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
-                                              unsigned RegNo,
+static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
-                                                unsigned RegNo,
+static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
                                                 uint64_t Address,
-                                                const void *Decoder);
+                                                const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
-                                            unsigned RegNo,
+static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
-                                            unsigned RegNo,
+static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeBranchTarget(MCInst &Inst,
-                                       unsigned Offset,
+static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
                                        uint64_t Address,
-                                       const void *Decoder);
+                                       const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
-                                              unsigned Offset,
+static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeJumpTarget(MCInst &Inst,
-                                     unsigned Insn,
+static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
                                      uint64_t Address,
-                                     const void *Decoder);
+                                     const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
-                                         unsigned Offset,
+static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
                                          uint64_t Address,
-                                         const void *Decoder);
+                                         const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
-                                           unsigned Offset,
+static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
-                                         unsigned Offset,
+static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
                                          uint64_t Address,
-                                         const void *Decoder);
+                                         const MCDisassembler *Decoder);
 
 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 // shifted left by 1 bit.
-static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
-                                          unsigned Offset,
+static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
                                           uint64_t Address,
-                                          const void *Decoder);
+                                          const MCDisassembler *Decoder);
 
 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 // shifted left by 1 bit.
-static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
-                                           unsigned Offset,
+static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 // shifted left by 1 bit.
-static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
-                                         unsigned Offset,
+static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
                                          uint64_t Address,
-                                         const void *Decoder);
+                                         const MCDisassembler *Decoder);
 
 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
 // shifted left by 1 bit.
-static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
-                                           unsigned Offset,
+static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 // shifted left by 1 bit.
-static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
-                                       unsigned Insn,
+static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
                                        uint64_t Address,
-                                       const void *Decoder);
+                                       const MCDisassembler *Decoder);
 
 // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target,
 // which is shifted left by 2 bit.
-static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
-                                        unsigned Insn,
+static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
                                         uint64_t Address,
-                                        const void *Decoder);
+                                        const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMem(MCInst &Inst,
-                              unsigned Insn,
-                              uint64_t Address,
-                              const void *Decoder);
+static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
+                              const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMemEVA(MCInst &Inst,
-                                 unsigned Insn,
-                                 uint64_t Address,
-                                 const void *Decoder);
+static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeLoadByte15(MCInst &Inst,
-                                     unsigned Insn,
+static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
                                      uint64_t Address,
-                                     const void *Decoder);
+                                     const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                  const void *Decoder);
+                                  const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
-                                             unsigned Insn,
+static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
-                                    unsigned Insn,
+static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
                                     uint64_t Address,
-                                    const void *Decoder);
+                                    const MCDisassembler *Decoder);
 
-static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
-                                    unsigned Insn,
+static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
                                     uint64_t Address,
-                                    const void *Decoder);
+                                    const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeSyncI(MCInst &Inst,
-                                unsigned Insn,
-                                uint64_t Address,
-                                const void *Decoder);
+static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
-                                   unsigned Insn,
+static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
                                    uint64_t Address,
-                                   const void *Decoder);
+                                   const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeSynciR6(MCInst &Inst,
-                                  unsigned Insn,
-                                  uint64_t Address,
-                                  const void *Decoder);
+static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder);
-
-static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
-                                    unsigned Insn,
                                     uint64_t Address,
-                                    const void *Decoder);
+                                    const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
-                                          unsigned Insn,
-                                          uint64_t Address,
-                                          const void *Decoder);
+static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
+                                    const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
-                                          unsigned Insn,
+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
                                           uint64_t Address,
-                                          const void *Decoder);
+                                          const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
-                                               unsigned Insn,
-                                               uint64_t Address,
-                                               const void *Decoder);
+static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
+                                          const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
-                                    unsigned Insn,
+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
                                                uint64_t Address,
-                                    const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
-                                     unsigned Insn,
-                                     uint64_t Address,
-                                     const void *Decoder);
+static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
+                                    const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
-                                     unsigned Insn,
+static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
                                      uint64_t Address,
-                                     const void *Decoder);
+                                     const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
                                      uint64_t Address,
-                               const void *Decoder);
+                                     const MCDisassembler *Decoder);
+
+static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
+                               const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
                                    uint64_t Address,
-                                   const void *Decoder);
+                                   const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                const void *Decoder);
+                                const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                const void *Decoder);
+                                const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
-                                     uint64_t Address, const void *Decoder);
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
                                        uint64_t Address,
-                                       const void *Decoder);
+                                       const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
-                                       unsigned Insn,
+static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
                                        uint64_t Address,
-                                       const void *Decoder);
+                                       const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
-                                       unsigned Value,
+static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
                                        uint64_t Address,
-                                       const void *Decoder);
+                                       const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeLi16Imm(MCInst &Inst,
-                                  unsigned Value,
+static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
                                   uint64_t Address,
-                                  const void *Decoder);
+                                  const MCDisassembler *Decoder);
 
-static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
-                                              unsigned Value,
+static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 
 template <unsigned Bits, int Offset, int Scale>
 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
                                                  uint64_t Address,
-                                                 const void *Decoder);
+                                                 const MCDisassembler *Decoder);
 
 template <unsigned Bits, int Offset>
 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
                                                        Decoder);
 }
 
 template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
                                                  uint64_t Address,
-                                                 const void *Decoder);
+                                                 const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeInsSize(MCInst &Inst,
-                                  unsigned Insn,
-                                  uint64_t Address,
-                                  const void *Decoder);
+static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
-                                     uint64_t Address, const void *Decoder);
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
-                                     uint64_t Address, const void *Decoder);
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
-                                     uint64_t Address, const void *Decoder);
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder);
 
 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 /// handle.
 template <typename InsnType>
 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
-                                   const void *Decoder);
+                                   const MCDisassembler *Decoder);
 
 template <typename InsnType>
 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
-                                       uint64_t Address, const void *Decoder);
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder);
 
 template <typename InsnType>
 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
-                                   const void *Decoder);
+                                   const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
-                      const void *Decoder);
+static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
-                           const void *Decoder);
+static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
-                       const void *Decoder);
+static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
-                           const void *Decoder);
+static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
-                           const void *Decoder);
+static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
-                           const void *Decoder);
+static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
-                       const void *Decoder);
+static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
-                       const void *Decoder);
+static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
-                      const void *Decoder);
+static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
-                       const void *Decoder);
+static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
-                          const void *Decoder);
+static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder);
 
 template <typename InsnType>
-static DecodeStatus
-DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
-                          const void *Decoder);
+static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder);
 
 template <typename InsnType>
 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
-                               const void *Decoder);
+                               const MCDisassembler *Decoder);
 
 template <typename InsnType>
 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
-                               const void *Decoder);
+                               const MCDisassembler *Decoder);
 
 template <typename InsnType>
 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
-                              const void *Decoder);
+                              const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
                                          uint64_t Address,
-                                         const void *Decoder);
+                                         const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
                                        uint64_t Address,
-                                       const void *Decoder);
+                                       const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 
 static MCDisassembler *createMipsDisassembler(
                        const Target &T,
                        const MCSubtargetInfo &STI,
                        MCContext &Ctx) {
   return new MipsDisassembler(STI, Ctx, true);
 }
 
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler() {
   TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),
                                          createMipsDisassembler);
   TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),
                                          createMipselDisassembler);
 }
 
 #include "MipsGenDisassemblerTables.inc"
 
-static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
-  const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
-  const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
+static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
+  const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
-                                   const void *Decoder) {
-  using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
+                                   const MCDisassembler *Decoder) {
+  using DecodeFN =
+      DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *);
 
   // The size of the n field depends on the element size
   // The register class also depends on this.
   InsnType tmp = fieldFromInstruction(insn, 17, 5);
   unsigned NSize = 0;
   DecodeFN RegDecoder = nullptr;
   if ((tmp & 0x18) == 0x00) { // INSVE_B
     NSize = 4;
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
   // $n2
   MI.addOperand(MCOperand::createImm(0));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   InsnType Rs = fieldFromInstruction(insn, 16, 5);
   InsnType Imm = fieldFromInstruction(insn, 0, 16);
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
                                        Rs)));
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
                                        Rs)));
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
-                               const void *Decoder) {
+                                   const MCDisassembler *Decoder) {
   InsnType Rs = fieldFromInstruction(insn, 21, 5);
   InsnType Imm = fieldFromInstruction(insn, 0, 16);
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
                                        Rs)));
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
                                        Rs)));
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
   // (otherwise we would have matched the ADDI instruction from the earlier
   // ISA's instead).
   //
   // We have:
   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
   //      BOVC if rs >= rt
   //      BEQZALC if rs == 0 && rt != 0
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   InsnType Rt = fieldFromInstruction(insn, 21, 5);
   InsnType Rs = fieldFromInstruction(insn, 16, 5);
   int64_t Imm = 0;
 
   if (Rs >= Rt) {
     MI.setOpcode(Mips::BOVC_MMR6);
     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                        Rt)));
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
   // (otherwise we would have matched the ADDI instruction from the earlier
   // ISA's instead).
   //
   // We have:
   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
   //      BNVC if rs >= rt
   //      BNEZALC if rs == 0 && rt != 0
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   InsnType Rt = fieldFromInstruction(insn, 21, 5);
   InsnType Rs = fieldFromInstruction(insn, 16, 5);
   int64_t Imm = 0;
 
   if (Rs >= Rt) {
     MI.setOpcode(Mips::BNVC_MMR6);
     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                        Rt)));
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   // We have:
   //    0b110101 ttttt sssss iiiiiiiiiiiiiiii
   //      Invalid if rt == 0
   //      BGTZC_MMR6   if rs == 0  && rt != 0
   //      BLTZC_MMR6   if rs == rt && rt != 0
   //      BLTC_MMR6    if rs != rt && rs != 0  && rt != 0
 
   InsnType Rt = fieldFromInstruction(insn, 21, 5);
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   // We have:
   //    0b111101 ttttt sssss iiiiiiiiiiiiiiii
   //      Invalid if rt == 0
   //      BLEZC_MMR6   if rs == 0  && rt != 0
   //      BGEZC_MMR6   if rs == rt && rt != 0
   //      BGEC_MMR6    if rs != rt && rs != 0  && rt != 0
 
   InsnType Rt = fieldFromInstruction(insn, 21, 5);
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
   // (otherwise we would have matched the BLEZL instruction from the earlier
   // ISA's instead).
   //
   // We have:
   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
   //      Invalid if rs == 0
   //      BLEZC   if rs == 0  && rt != 0
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
   // (otherwise we would have matched the BGTZL instruction from the earlier
   // ISA's instead).
   //
   // We have:
   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
   //      Invalid if rs == 0
   //      BGTZC   if rs == 0  && rt != 0
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
   // (otherwise we would have matched the BGTZ instruction from the earlier
   // ISA's instead).
   //
   // We have:
   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
   //      BGTZ    if rt == 0
   //      BGTZALC if rs == 0 && rt != 0
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
-                                           uint64_t Address,
-                                           const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
   // (otherwise we would have matched the BLEZL instruction from the earlier
   // ISA's instead).
   //
   // We have:
   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
   //      Invalid   if rs == 0
   //      BLEZALC   if rs == 0  && rt != 0
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 
   return MCDisassembler::Success;
 }
 
 // Override the generated disassembler to produce DEXT all the time. This is
 // for feature / behaviour parity with  binutils.
 template <typename InsnType>
 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
-                               const void *Decoder) {
+                               const MCDisassembler *Decoder) {
   unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
   unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
   unsigned Size = 0;
   unsigned Pos = 0;
 
   switch (MI.getOpcode()) {
     case Mips::DEXT:
       Pos = Lsb;
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
 
   return MCDisassembler::Success;
 }
 
 // Override the generated disassembler to produce DINS all the time. This is
 // for feature / behaviour parity with binutils.
 template <typename InsnType>
 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
-                               const void *Decoder) {
+                               const MCDisassembler *Decoder) {
   unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
   unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
   unsigned Size = 0;
   unsigned Pos = 0;
 
   switch (MI.getOpcode()) {
     case Mips::DINS:
       Pos = Lsb;
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
   MI.addOperand(MCOperand::createImm(Size));
 
   return MCDisassembler::Success;
 }
 
 // Auto-generated decoder wouldn't add the third operand for CRC32*.
 template <typename InsnType>
 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
-                              const void *Decoder) {
+                              const MCDisassembler *Decoder) {
   InsnType Rs = fieldFromInstruction(Insn, 21, 5);
   InsnType Rt = fieldFromInstruction(Insn, 16, 5);
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                      Rt)));
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                      Rs)));
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                      Rt)));
DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
   Result =
       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
   if (Result != MCDisassembler::Fail)
     return Result;
 
   return MCDisassembler::Fail;
 }
 
-static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
-                                                 unsigned RegNo,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   return MCDisassembler::Fail;
 }
 
-static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
-                                                   unsigned RegNo,
-                                                   uint64_t Address,
-                                                   const void *Decoder) {
+static DecodeStatus
+DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
-                                                    unsigned RegNo,
-                                                    uint64_t Address,
-                                                    const void *Decoder) {
+static DecodeStatus
+DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                                const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
   unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
-                                           unsigned RegNo,
+static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 
   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
-                                            unsigned RegNo,
+static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
-                                           unsigned RegNo,
+static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
-                                           unsigned RegNo,
+static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMem(MCInst &Inst,
-                              unsigned Insn,
-                              uint64_t Address,
-                              const void *Decoder) {
+static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
+                              const MCDisassembler *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   if (Inst.getOpcode() == Mips::SC ||
       Inst.getOpcode() == Mips::SCD)
     Inst.addOperand(MCOperand::createReg(Reg));
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMemEVA(MCInst &Inst,
-                                 unsigned Insn,
-                                 uint64_t Address,
-                                 const void *Decoder) {
+static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   int Offset = SignExtend32<9>(Insn >> 7);
   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
    if (Inst.getOpcode() == Mips::SCE)
      Inst.addOperand(MCOperand::createReg(Reg));
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeLoadByte15(MCInst &Inst,
-                                     unsigned Insn,
+static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
                                      uint64_t Address,
-                                     const void *Decoder) {
+                                     const MCDisassembler *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeCacheOp(MCInst &Inst,
-                              unsigned Insn,
-                              uint64_t Address,
-                              const void *Decoder) {
+static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
   Inst.addOperand(MCOperand::createImm(Hint));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
-                                    unsigned Insn,
+static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
                                     uint64_t Address,
-                                    const void *Decoder) {
+                                    const MCDisassembler *Decoder) {
   int Offset = SignExtend32<12>(Insn & 0xfff);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
 
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
   Inst.addOperand(MCOperand::createImm(Hint));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
-                                    unsigned Insn,
+static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
                                     uint64_t Address,
-                                    const void *Decoder) {
+                                    const MCDisassembler *Decoder) {
   int Offset = SignExtend32<9>(Insn & 0x1ff);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
 
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
   Inst.addOperand(MCOperand::createImm(Hint));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
-                                             unsigned Insn,
+static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   int Offset = SignExtend32<9>(Insn >> 7);
   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
   Inst.addOperand(MCOperand::createImm(Hint));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeSyncI(MCInst &Inst,
-                              unsigned Insn,
-                              uint64_t Address,
-                              const void *Decoder) {
+static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                const MCDisassembler *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeSynciR6(MCInst &Inst,
-                                  unsigned Insn,
-                                  uint64_t Address,
-                                  const void *Decoder) {
+static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   int Immediate = SignExtend32<16>(Insn & 0xffff);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Immediate));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 
   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Reg));
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
   case Mips::ST_D:
     Inst.addOperand(MCOperand::createImm(Offset * 8));
     break;
   }
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
-                                    unsigned Insn,
+static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
                                     uint64_t Address,
-                                    const void *Decoder) {
+                                    const MCDisassembler *Decoder) {
   unsigned Offset = Insn & 0xf;
   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
   unsigned Base = fieldFromInstruction(Insn, 4, 3);
 
   switch (Inst.getOpcode()) {
     case Mips::LBU16_MM:
     case Mips::LHU16_MM:
     case Mips::LW16_MM:
switch (Inst.getOpcode()) {
     case Mips::SW16_MMR6:
       Inst.addOperand(MCOperand::createImm(Offset << 2));
       break;
   }
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
-                                          unsigned Insn,
+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   unsigned Offset = Insn & 0x1F;
   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
 
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Mips::SP));
   Inst.addOperand(MCOperand::createImm(Offset << 2));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
-                                          unsigned Insn,
+static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   unsigned Offset = Insn & 0x7F;
   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
 
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Mips::GP));
   Inst.addOperand(MCOperand::createImm(Offset << 2));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
-                                               unsigned Insn,
+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   int Offset;
   switch (Inst.getOpcode()) {
   case Mips::LWM16_MMR6:
   case Mips::SWM16_MMR6:
     Offset = fieldFromInstruction(Insn, 4, 4);
     break;
   default:
     Offset = SignExtend32<4>(Insn & 0xf);
     break;
   }
 
   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
       == MCDisassembler::Fail)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(Mips::SP));
   Inst.addOperand(MCOperand::createImm(Offset << 2));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
-                                    unsigned Insn,
+static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
                                     uint64_t Address,
-                                    const void *Decoder) {
+                                    const MCDisassembler *Decoder) {
   int Offset = SignExtend32<9>(Insn & 0x1ff);
   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
     Inst.addOperand(MCOperand::createReg(Reg));
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
-                                     unsigned Insn,
+static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
                                      uint64_t Address,
-                                     const void *Decoder) {
+                                     const MCDisassembler *Decoder) {
   int Offset = SignExtend32<12>(Insn & 0x0fff);
   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   switch (Inst.getOpcode()) {
default:
 
     Inst.addOperand(MCOperand::createReg(Base));
     Inst.addOperand(MCOperand::createImm(Offset));
   }
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
-                                     unsigned Insn,
+static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
                                      uint64_t Address,
-                                     const void *Decoder) {
+                                     const MCDisassembler *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeFMem(MCInst &Inst,
-                               unsigned Insn,
-                               uint64_t Address,
-                               const void *Decoder) {
+static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
+                               const MCDisassembler *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   // This function is the same as DecodeFMem but with the Reg and Base fields
   // swapped according to microMIPS spec.
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 
   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeFMem2(MCInst &Inst,
-                               unsigned Insn,
-                               uint64_t Address,
-                               const void *Decoder) {
+static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                const MCDisassembler *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeFMem3(MCInst &Inst,
-                               unsigned Insn,
-                               uint64_t Address,
-                               const void *Decoder) {
+static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                const MCDisassembler *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
-                                    unsigned Insn,
+static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
                                      uint64_t Address,
-                                    const void *Decoder) {
+                                     const MCDisassembler *Decoder) {
   int Offset = SignExtend32<11>(Insn & 0x07ff);
   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 
   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   int Offset = SignExtend32<11>(Insn & 0x07ff);
   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 
   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
-                                       unsigned Insn,
+static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
                                        uint64_t Address,
-                                       const void *Decoder) {
+                                       const MCDisassembler *Decoder) {
   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
     Inst.addOperand(MCOperand::createReg(Rt));
   }
 
   Inst.addOperand(MCOperand::createReg(Rt));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
-                                              unsigned RegNo,
+static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   // Currently only hardware register 29 is supported.
   if (RegNo != 29)
     return  MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(Mips::HWR29));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
-                                              unsigned RegNo,
+static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo > 30 || RegNo %2)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
-                                                unsigned RegNo,
+static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   if (RegNo >= 4)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo >= 4)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo >= 4)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
-                                            unsigned RegNo,
+static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
-                                            unsigned RegNo,
+static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeBranchTarget(MCInst &Inst,
-                                       unsigned Offset,
+static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
                                        uint64_t Address,
-                                       const void *Decoder) {
+                                       const MCDisassembler *Decoder) {
   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
-                                              unsigned Offset,
+static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeJumpTarget(MCInst &Inst,
-                                     unsigned Insn,
+static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
                                      uint64_t Address,
-                                     const void *Decoder) {
+                                     const MCDisassembler *Decoder) {
   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
   Inst.addOperand(MCOperand::createImm(JumpOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
-                                         unsigned Offset,
+static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
 
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
-                                           unsigned Offset,
+static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
 
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
-                                         unsigned Offset,
+static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
 
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
-                                          unsigned Offset,
+static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   int32_t BranchOffset = SignExtend32<8>(Offset << 1);
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
-                                           unsigned Offset,
+static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   int32_t BranchOffset = SignExtend32<11>(Offset << 1);
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
-                                         unsigned Offset,
+static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
-  unsigned Offset,
+static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
                                            uint64_t Address,
-  const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   int32_t BranchOffset = SignExtend32<27>(Offset << 1);
 
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
-                                       unsigned Insn,
+static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
                                        uint64_t Address,
-                                       const void *Decoder) {
+                                       const MCDisassembler *Decoder) {
   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
   Inst.addOperand(MCOperand::createImm(JumpOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
-                                        unsigned Insn,
+static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
                                         uint64_t Address,
-                                        const void *Decoder) {
+                                        const MCDisassembler *Decoder) {
   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
   Inst.addOperand(MCOperand::createImm(JumpOffset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
-                                       unsigned Value,
+static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
                                        uint64_t Address,
-                                       const void *Decoder) {
+                                       const MCDisassembler *Decoder) {
   if (Value == 0)
     Inst.addOperand(MCOperand::createImm(1));
   else if (Value == 0x7)
     Inst.addOperand(MCOperand::createImm(-1));
   else
     Inst.addOperand(MCOperand::createImm(Value << 2));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeLi16Imm(MCInst &Inst,
-                                  unsigned Value,
+static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
                                   uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   if (Value == 0x7F)
     Inst.addOperand(MCOperand::createImm(-1));
   else
     Inst.addOperand(MCOperand::createImm(Value));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
-                                              unsigned Value,
+static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
   return MCDisassembler::Success;
 }
 
 template <unsigned Bits, int Offset, int Scale>
-static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   Value &= ((1 << Bits) - 1);
   Value *= Scale;
   Inst.addOperand(MCOperand::createImm(Value + Offset));
   return MCDisassembler::Success;
 }
 
 template <unsigned Bits, int Offset, int ScaleBy>
-static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
   Inst.addOperand(MCOperand::createImm(Imm + Offset));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeInsSize(MCInst &Inst,
-                                  unsigned Insn,
-                                  uint64_t Address,
-                                  const void *Decoder) {
+static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   // First we need to grab the pos(lsb) from MCInst.
   // This function only handles the 32 bit variants of ins, as dins
   // variants are handled differently.
   int Pos = Inst.getOperand(2).getImm();
   int Size = (int) Insn - Pos + 1;
   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
-                                     uint64_t Address, const void *Decoder) {
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
-                                     uint64_t Address, const void *Decoder) {
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   int32_t DecodedValue;
   switch (Insn) {
   case 0: DecodedValue = 256; break;
   case 1: DecodedValue = 257; break;
   case 510: DecodedValue = -258; break;
   case 511: DecodedValue = -257; break;
   default: DecodedValue = SignExtend32<9>(Insn); break;
   }
   Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   // Insn must be >= 0, since it is unsigned that condition is always true.
   assert(Insn < 16);
   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
                              255, 32768, 65535};
   Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeRegListOperand(MCInst &Inst,
-                                         unsigned Insn,
+static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
                      Mips::S6, Mips::S7, Mips::FP};
   unsigned RegNum;
 
   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
 
   // Empty register lists are not allowed.
   if (RegLst == 0)
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
   if (RegLst & 0x10)
     Inst.addOperand(MCOperand::createReg(Mips::RA));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
   unsigned RegLst;
   switch(Inst.getOpcode()) {
   default:
     RegLst = fieldFromInstruction(Insn, 4, 2);
     break;
   case Mips::LWM16_MMR6:
   case Mips::SWM16_MMR6:
     RegLst = fieldFromInstruction(Insn, 8, 2);
     break;
   }
   unsigned RegNum = RegLst & 0x3;
 
   for (unsigned i = 0; i <= RegNum; i++)
     Inst.addOperand(MCOperand::createReg(Regs[i]));
 
   Inst.addOperand(MCOperand::createReg(Mips::RA));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
-                                          uint64_t Address,
-                                          const void *Decoder) {
+                                        const MCDisassembler *Decoder) {
   unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
   if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
 
   unsigned RegRs;
   if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6())
     RegRs = fieldFromInstruction(Insn, 0, 2) |
             (fieldFromInstruction(Insn, 3, 1) << 2);
   else
     RegRs = fieldFromInstruction(Insn, 1, 3);
   if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
 
   unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
   if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
       MCDisassembler::Fail)
     return MCDisassembler::Fail;
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   switch (RegPair) {
   default:
     return MCDisassembler::Fail;
   case 0:
     Inst.addOperand(MCOperand::createReg(Mips::A1));
     Inst.addOperand(MCOperand::createReg(Mips::A2));
     break;
   case 1:
case 7:
     Inst.addOperand(MCOperand::createReg(Mips::A3));
     break;
   }
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
-                                     uint64_t Address, const void *Decoder) {
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
                                               uint64_t Address,
-  const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   // We have:
   //    0b000111 ttttt sssss iiiiiiiiiiiiiiii
   //      Invalid      if rt == 0
   //      BGTZALC_MMR6 if rs == 0 && rt != 0
   //      BLTZALC_MMR6 if rs != 0 && rs == rt
   //      BLTUC_MMR6   if rs != 0 && rs != rt
 
   InsnType Rt = fieldFromInstruction(insn, 21, 5);
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
 
   MI.addOperand(MCOperand::createImm(Imm));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
                                               uint64_t Address,
-  const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   // We have:
   //    0b000110 ttttt sssss iiiiiiiiiiiiiiii
   //      Invalid        if rt == 0
   //      BLEZALC_MMR6   if rs == 0  && rt != 0
   //      BGEZALC_MMR6   if rs == rt && rt != 0
   //      BGEUC_MMR6     if rs != rt && rs != 0  && rt != 0
 
   InsnType Rt = fieldFromInstruction(insn, 21, 5);

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() {
   TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),
                                          createPPCDisassembler);
   TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),
                                          createPPCLEDisassembler);
 }
 
 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
                                        uint64_t /*Address*/,
-                                       const void * /*Decoder*/) {
+                                       const MCDisassembler * /*Decoder*/) {
   Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
                                          uint64_t /*Address*/,
-                                         const void * /*Decoder*/) {
+                                         const MCDisassembler * /*Decoder*/) {
   int32_t Offset = SignExtend32<24>(Imm);
   Inst.addOperand(MCOperand::createImm(Offset));
   return MCDisassembler::Success;
 }
 
 // FIXME: These can be generated by TableGen from the existing register
 // encoding values!
 
 template <std::size_t N>
 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
                                         const MCPhysReg (&Regs)[N]) {
   assert(RegNo < N && "Invalid register number");
   Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, CRRegs);
 }
 
 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                            const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, CRBITRegs);
 }
 
 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, FRegs);
 }
 
 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, FRegs);
 }
 
 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, VFRegs);
 }
 
 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, VRegs);
 }
 
 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, VSRegs);
 }
 
 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                            const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, VSFRegs);
 }
 
 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                            const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, VSSRegs);
 }
 
 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, RRegs);
 }
 
-static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
-                                            uint64_t Address,
-                                            const void *Decoder) {
+static DecodeStatus
+DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
 }
 
 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, XRegs);
 }
 
 static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, XRegs);
 }
 
-static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
-                                            uint64_t Address,
-                                            const void *Decoder) {
+static DecodeStatus
+DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
 }
 
 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
 
 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                            const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SPERegs);
 }
 
 static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, ACCRegs);
 }
 
 static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, VSRpRegs);
 }
 
 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
 
-template<unsigned N>
+template <unsigned N>
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
-                                      int64_t Address, const void *Decoder) {
+                                      int64_t Address,
+                                      const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
-template<unsigned N>
+template <unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
-                                      int64_t Address, const void *Decoder) {
+                                      int64_t Address,
+                                      const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
-                                         int64_t Address, const void *Decoder) {
+                                         int64_t Address,
+                                         const MCDisassembler *Decoder) {
   if (Imm != 0)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo & 1)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
-                                        int64_t Address, const void *Decoder) {
+                                        int64_t Address,
+                                        const MCDisassembler *Decoder) {
   // Decode the memri field (imm, reg), which has the low 16-bits as the
   // displacement and the next 5 bits as the register #.
 
   uint64_t Base = Imm >> 16;
   uint64_t Disp = Imm & 0xFFFF;
 
   assert(Base < 32 && "Invalid base register");
 
static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
   }
 
   Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
-                                         int64_t Address, const void *Decoder) {
+                                         int64_t Address,
+                                         const MCDisassembler *Decoder) {
   // Decode the memrix field (imm, reg), which has the low 14-bits as the
   // displacement and the next 5 bits as the register #.
 
   uint64_t Base = Imm >> 14;
   uint64_t Disp = Imm & 0x3FFF;
 
   assert(Base < 32 && "Invalid base register");
 
   if (Inst.getOpcode() == PPC::LDU)
     // Add the tied output operand.
     Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   else if (Inst.getOpcode() == PPC::STDU)
     Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
 
   Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
                                             int64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   // Decode the memrix field for a hash store or hash check operation.
   // The field is composed of a register and an immediate value that is 6 bits
   // and covers the range -8 to -512. The immediate is always negative and 2s
   // complement which is why we sign extend a 7 bit value.
   const uint64_t Base = Imm >> 6;
   const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
 
   assert(Base < 32 && "Invalid base register");
 
   Inst.addOperand(MCOperand::createImm(Disp));
   Inst.addOperand(MCOperand::createReg(RRegs[Base]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
-                                         int64_t Address, const void *Decoder) {
+                                           int64_t Address,
+                                           const MCDisassembler *Decoder) {
   // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
   // displacement with 16-byte aligned, and the next 5 bits as the register #.
 
   uint64_t Base = Imm >> 12;
   uint64_t Disp = Imm & 0xFFF;
 
   assert(Base < 32 && "Invalid base register");
 
   Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
                                                int64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
   // displacement, and the next 5 bits as an immediate 0.
   uint64_t Base = Imm >> 34;
   uint64_t Disp = Imm & 0x3FFFFFFFFUL;
 
   assert(Base < 32 && "Invalid base register");
 
   Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
   return decodeImmZeroOperand(Inst, Base, Address, Decoder);
 }
 
 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   // Decode the memri34 field (imm, reg), which has the low 34-bits as the
   // displacement, and the next 5 bits as the register #.
   uint64_t Base = Imm >> 34;
   uint64_t Disp = Imm & 0x3FFFFFFFFUL;
 
   assert(Base < 32 && "Invalid base register");
 
   Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
-                                         int64_t Address, const void *Decoder) {
+                                       int64_t Address,
+                                       const MCDisassembler *Decoder) {
   // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
   // displacement with 8-byte aligned, and the next 5 bits as the register #.
 
   uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
 
   assert(Base < 32 && "Invalid base register");
 
   Inst.addOperand(MCOperand::createImm(Disp << 3));
   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
-                                         int64_t Address, const void *Decoder) {
+                                       int64_t Address,
+                                       const MCDisassembler *Decoder) {
   // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
   // displacement with 4-byte aligned, and the next 5 bits as the register #.
 
   uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
 
   assert(Base < 32 && "Invalid base register");
 
   Inst.addOperand(MCOperand::createImm(Disp << 2));
   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
-                                         int64_t Address, const void *Decoder) {
+                                       int64_t Address,
+                                       const MCDisassembler *Decoder) {
   // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
   // displacement with 2-byte aligned, and the next 5 bits as the register #.
 
   uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
 
   assert(Base < 32 && "Invalid base register");
 
   Inst.addOperand(MCOperand::createImm(Disp << 1));
   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
-                                        int64_t Address, const void *Decoder) {
+                                        int64_t Address,
+                                        const MCDisassembler *Decoder) {
   // The cr bit encoding is 0x80 >> cr_reg_num.
 
   unsigned Zeros = countTrailingZeros(Imm);
   assert(Zeros < 8 && "Invalid CR bit value");
 
   Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
   return MCDisassembler::Success;
 }

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
   TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
                                          createRISCVDisassembler);
   TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
                                          createRISCVDisassembler);
 }
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   const FeatureBitset &FeatureBits =
-      static_cast<const MCDisassembler *>(Decoder)
-          ->getSubtargetInfo()
-          .getFeatureBits();
+      Decoder->getSubtargetInfo().getFeatureBits();
   bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
 
   if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::X0 + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::F0_H + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::F0_F + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo >= 8) {
     return MCDisassembler::Fail;
   }
   MCRegister Reg = RISCV::F8_F + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::F0_D + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo >= 8) {
     return MCDisassembler::Fail;
   }
   MCRegister Reg = RISCV::F8_D + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo == 0) {
     return MCDisassembler::Fail;
   }
 
   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   if (RegNo == 2) {
     return MCDisassembler::Fail;
   }
 
   return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo >= 8)
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::X8 + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo >= 32 || RegNo & 1)
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::X0 + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::V0 + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   if (RegNo % 2)
     return MCDisassembler::Fail;
 
   const RISCVDisassembler *Dis =
       static_cast<const RISCVDisassembler *>(Decoder);
   const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
   MCRegister Reg =
       RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
                               &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   if (RegNo % 4)
     return MCDisassembler::Fail;
 
   const RISCVDisassembler *Dis =
       static_cast<const RISCVDisassembler *>(Decoder);
   const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
   MCRegister Reg =
       RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
                               &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   if (RegNo % 8)
     return MCDisassembler::Fail;
 
   const RISCVDisassembler *Dis =
       static_cast<const RISCVDisassembler *>(Decoder);
   const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
   MCRegister Reg =
       RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
                               &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
 
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   MCRegister Reg = RISCV::NoRegister;
   switch (RegNo) {
   default:
     return MCDisassembler::Fail;
   case 0:
     Reg = RISCV::V0;
     break;
   case 1:
     break;
   }
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 // Add implied SP operand for instructions *SP compressed instructions. The SP
 // operand isn't explicitly encoded in the instruction.
-static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
+static void addImplySP(MCInst &Inst, int64_t Address,
+                       const MCDisassembler *Decoder) {
   if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
       Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
       Inst.getOpcode() == RISCV::C_FLWSP ||
       Inst.getOpcode() == RISCV::C_FSWSP ||
       Inst.getOpcode() == RISCV::C_FLDSP ||
       Inst.getOpcode() == RISCV::C_FSDSP ||
       Inst.getOpcode() == RISCV::C_ADDI4SPN) {
     DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
   }
   if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
     DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
     DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
   }
 }
 
 template <unsigned N>
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
-                                      int64_t Address, const void *Decoder) {
+                                      int64_t Address,
+                                      const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   addImplySP(Inst, Address, Decoder);
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 template <unsigned N>
 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
                                              int64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (Imm == 0)
     return MCDisassembler::Fail;
   return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
 }
 
 template <unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
-                                      int64_t Address, const void *Decoder) {
+                                      int64_t Address,
+                                      const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   addImplySP(Inst, Address, Decoder);
   // Sign-extend the number in the bottom N bits of Imm
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
   return MCDisassembler::Success;
 }
 
 template <unsigned N>
 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
                                              int64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (Imm == 0)
     return MCDisassembler::Fail;
   return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
 }
 
 template <unsigned N>
 static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
                                              int64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   // Sign-extend the number in the bottom N bits of Imm after accounting for
   // the fact that the N bit immediate is stored in N-1 bits (the LSB is
   // always zero)
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
                                          int64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   assert(isUInt<6>(Imm) && "Invalid immediate");
   if (Imm > 31) {
     Imm = (SignExtend64<6>(Imm) & 0xfffff);
   }
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
-                                 int64_t Address,
-                                 const void *Decoder) {
+static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address,
+                                 const MCDisassembler *Decoder) {
   assert(isUInt<3>(Imm) && "Invalid immediate");
   if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
-                                       uint64_t Address, const void *Decoder);
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder);
 
 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
-                                         uint64_t Address, const void *Decoder);
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder);
 
 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
                                             uint64_t Address,
-                                            const void *Decoder);
+                                            const MCDisassembler *Decoder);
 
 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 
 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
 #include "RISCVGenDisassemblerTables.inc"
 
 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   uint64_t SImm6 =
       fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
   DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
   (void)Result;
   assert(Result == MCDisassembler::Success && "Invalid immediate");
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
   uint64_t SImm6 =
       fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
   DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
   (void)Result;
   assert(Result == MCDisassembler::Success && "Invalid immediate");
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
   Inst.addOperand(Inst.getOperand(0));
   uint64_t UImm6 =
       fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
   DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
   (void)Result;
   assert(Result == MCDisassembler::Success && "Invalid immediate");
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(Insn, 7, 5);
   unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
   DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
   DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   unsigned Rd = fieldFromInstruction(Insn, 7, 5);
   unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
   DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
   Inst.addOperand(Inst.getOperand(0));
   DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
   return MCDisassembler::Success;
 }
 

llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

 
 static const uint16_t CPPairDecoderTable[] = {
   SP::C0_C1,   SP::C2_C3,   SP::C4_C5,   SP::C6_C7,
   SP::C8_C9,   SP::C10_C11, SP::C12_C13, SP::C14_C15,
   SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
   SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
 };
 
-static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = IntRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = IntRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-
-static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
-                                              unsigned RegNo,
+static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = FPRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-
-static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = DFPRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-
-static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
+static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = QFPRegDecoderTable[RegNo];
   if (Reg == ~0U)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst,
-                                               unsigned RegNo,
-                                               uint64_t Address,
-                                               const void *Decoder) {
+static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+                                              const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = CPRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 3)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                               uint64_t Address,
-                                               const void *Decoder) {
+                                              const MCDisassembler *Decoder) {
   if (RegNo >= array_lengthof(PRRegDecoderTable))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   if ((RegNo & 1))
     S = MCDisassembler::SoftFail;
 
   unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
   Inst.addOperand(MCOperand::createReg(RegisterPair));
   return S;
 }
 
 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
   Inst.addOperand(MCOperand::createReg(RegisterPair));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder);
-static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder);
+                                  const MCDisassembler *Decoder);
+static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn,
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder);
 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder);
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder);
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder);
-static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder);
+                                 const MCDisassembler *Decoder);
+static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn,
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder);
 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
-                                  uint64_t Address, const void *Decoder);
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder);
+static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
+static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
-                               uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
-                                 uint64_t Address, const void *Decoder);
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder);
+static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address,
+                               const MCDisassembler *Decoder);
+static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
-                               const void *Decoder);
+                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
-                               const void *Decoder);
+                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address,
-                               const void *Decoder);
+                               const MCDisassembler *Decoder);
 
 #include "SparcGenDisassemblerTables.inc"
 
 /// Read four bytes from the ArrayRef and return 32 bit word.
 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
                                       uint64_t &Size, uint32_t &Insn,
                                       bool IsLittleEndian) {
   // We want to read exactly 4 Bytes of data.
DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
   if (Result != MCDisassembler::Fail) {
     Size = 4;
     return Result;
   }
 
   return MCDisassembler::Fail;
 }
 
-
 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
-                                   const void *Decoder);
+                                   const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
-                              const void *Decoder,
-                              bool isLoad, DecodeFunc DecodeRD) {
+                              const MCDisassembler *Decoder, bool isLoad,
+                              DecodeFunc DecodeRD) {
   unsigned rd = fieldFromInstruction(insn, 25, 5);
   unsigned rs1 = fieldFromInstruction(insn, 14, 5);
   bool isImm = fieldFromInstruction(insn, 13, 1);
   bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
   unsigned asi = fieldFromInstruction(insn, 5, 8);
   unsigned rs2 = 0;
   unsigned simm13 = 0;
   if (isImm)
if (!isLoad) {
     status = DecodeRD(MI, rd, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
                    DecodeIntRegsRegisterClass);
 }
 
-static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder) {
+static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn,
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
                    DecodeIntPairRegisterClass);
 }
 
 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
                    DecodeFPRegsRegisterClass);
 }
 
 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
                    DecodeDFPRegsRegisterClass);
 }
 
 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
                    DecodeQFPRegsRegisterClass);
 }
 
 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
                    DecodeCPRegsRegisterClass);
 }
 
-static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder) {
+static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn,
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true,
                    DecodeCPPairRegisterClass);
 }
 
 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
                    DecodeIntRegsRegisterClass);
 }
 
 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
                    DecodeIntPairRegisterClass);
 }
 
 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
                    DecodeFPRegsRegisterClass);
 }
 
 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
                    DecodeDFPRegsRegisterClass);
 }
 
 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
                    DecodeQFPRegsRegisterClass);
 }
 
-static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address,
+                                  const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
                    DecodeCPRegsRegisterClass);
 }
 
 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
-                                   uint64_t Address, const void *Decoder) {
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false,
                    DecodeCPPairRegisterClass);
 }
 
-static bool tryAddingSymbolicOperand(int64_t Value,  bool isBranch,
+static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
                                      uint64_t Address, uint64_t Offset,
                                      uint64_t Width, MCInst &MI,
-                                     const void *Decoder) {
-  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
-  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
-                                       Offset, Width);
+                                     const MCDisassembler *Decoder) {
+  return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
+                                           Width);
 }
 
-static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
-                               uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address,
+                               const MCDisassembler *Decoder) {
   unsigned tgt = fieldFromInstruction(insn, 0, 30);
   tgt <<= 2;
   if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
                                 0, 30, MI, Decoder))
     MI.addOperand(MCOperand::createImm(tgt));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
-                                 uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
   MI.addOperand(MCOperand::createImm(tgt));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
-                               const void *Decoder) {
+                               const MCDisassembler *Decoder) {
 
   unsigned rd = fieldFromInstruction(insn, 25, 5);
   unsigned rs1 = fieldFromInstruction(insn, 14, 5);
   unsigned isImm = fieldFromInstruction(insn, 13, 1);
   unsigned rs2 = 0;
   unsigned simm13 = 0;
   if (isImm)
     simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
else {
     status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
 
   unsigned rs1 = fieldFromInstruction(insn, 14, 5);
   unsigned isImm = fieldFromInstruction(insn, 13, 1);
   unsigned rs2 = 0;
   unsigned simm13 = 0;
   if (isImm)
     simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
   else
else {
     status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
-                               const void *Decoder) {
+                               const MCDisassembler *Decoder) {
 
   unsigned rd = fieldFromInstruction(insn, 25, 5);
   unsigned rs1 = fieldFromInstruction(insn, 14, 5);
   unsigned isImm = fieldFromInstruction(insn, 13, 1);
   bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
   unsigned asi = fieldFromInstruction(insn, 5, 8);
   unsigned rs2 = 0;
   unsigned simm13 = 0;
static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
 
   if (hasAsi)
     MI.addOperand(MCOperand::createImm(asi));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address,
-                               const void *Decoder) {
+                               const MCDisassembler *Decoder) {
 
   unsigned rs1 = fieldFromInstruction(insn, 14, 5);
   unsigned isImm = fieldFromInstruction(insn, 13, 1);
   unsigned cc =fieldFromInstruction(insn, 25, 4);
   unsigned rs2 = 0;
   unsigned imm7 = 0;
   if (isImm)
     imm7 = fieldFromInstruction(insn, 0, 7);

llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp

 /// an MCExpr and that is added as an operand to the MCInst.  If getOpInfo()
 /// returns zero and isBranch is true then a symbol look up for immediate Value
 /// is done and if a symbol is found an MCExpr is created with that, else
 /// an MCExpr with the immediate Value is created.  This function returns true
 /// if it adds an operand to the MCInst and false otherwise.
 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
                                      uint64_t Address, uint64_t Offset,
                                      uint64_t Width, MCInst &MI,
-                                     const void *Decoder) {
-  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
-  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
-                                       Offset, Width);
+                                     const MCDisassembler *Decoder) {
+  return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
+                                           Width);
 }
 
 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
                                         const unsigned *Regs, unsigned Size) {
   assert(RegNo < Size && "Invalid register");
   RegNo = Regs[RegNo];
   if (RegNo == 0)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(RegNo));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
 }
 
 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
 }
 
 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
 }
 
 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
 }
 
-static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
 }
 
 static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
 }
 
 static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16);
 }
 
 static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16);
 }
 
 static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32);
 }
 
 static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32);
 }
 
 static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32);
 }
 
 static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16);
 }
 
 static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16);
 }
 
 template<unsigned N>
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
   if (!isUInt<N>(Imm))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 template<unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
   if (!isUInt<N>(Imm))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   return decodeUImmOperand<1>(Inst, Imm);
 }
 
 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   return decodeUImmOperand<2>(Inst, Imm);
 }
 
 static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   return decodeUImmOperand<3>(Inst, Imm);
 }
 
 static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   return decodeUImmOperand<4>(Inst, Imm);
 }
 
 static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   return decodeUImmOperand<6>(Inst, Imm);
 }
 
 static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   return decodeUImmOperand<8>(Inst, Imm);
 }
 
 static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   return decodeUImmOperand<12>(Inst, Imm);
 }
 
 static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   return decodeUImmOperand<16>(Inst, Imm);
 }
 
 static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   return decodeUImmOperand<32>(Inst, Imm);
 }
 
 static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm,
-                                       uint64_t Address, const void *Decoder) {
+                                       uint64_t Address,
+                                       const MCDisassembler *Decoder) {
   return decodeSImmOperand<8>(Inst, Imm);
 }
 
 static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   return decodeSImmOperand<16>(Inst, Imm);
 }
 
 static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   return decodeSImmOperand<32>(Inst, Imm);
 }
 
-template<unsigned N>
+template <unsigned N>
 static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
-                                       uint64_t Address,
-                                       bool isBranch,
-                                       const void *Decoder) {
+                                       uint64_t Address, bool isBranch,
+                                       const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
   uint64_t Value = SignExtend64<N>(Imm) * 2 + Address;
 
   if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, N / 8,
                                 Inst, Decoder))
     Inst.addOperand(MCOperand::createImm(Value));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder);
 }
 
 static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder);
 }
 
 static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder);
 }
 
 static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm,
                                                uint64_t Address,
-                                               const void *Decoder) {
+                                               const MCDisassembler *Decoder) {
   return decodePCDBLOperand<32>(Inst, Imm, Address, true, Decoder);
 }
 
 static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm,
                                          uint64_t Address,
-                                         const void *Decoder) {
+                                         const MCDisassembler *Decoder) {
   return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
 }
 
 static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field,
                                           const unsigned *Regs) {
   uint64_t Base = Field >> 12;
   uint64_t Disp = Field & 0xfff;
   assert(Base < 16 && "Invalid BDAddr12");
static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field,
   Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
   Inst.addOperand(MCOperand::createImm(Disp));
   Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs);
 }
 
 static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs);
 }
 
 static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
 }
 
 static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
 }
 
-static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
 }
 
-static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
 }
 
-static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst &Inst,
-                                                     uint64_t Field,
-                                                     uint64_t Address,
-                                                     const void *Decoder) {
+static DecodeStatus
+decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   return decodeBDLAddr12Len4Operand(Inst, Field, SystemZMC::GR64Regs);
 }
 
-static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst,
-                                                     uint64_t Field,
-                                                     uint64_t Address,
-                                                     const void *Decoder) {
+static DecodeStatus
+decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
+                                 const MCDisassembler *Decoder) {
   return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs);
 }
 
-static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst &Inst,
-                                                 uint64_t Field,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   return decodeBDRAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
 }
 
-static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
-                                                 uint64_t Address,
-                                                 const void *Decoder) {
+static DecodeStatus
+decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
+                             const MCDisassembler *Decoder) {
   return decodeBDVAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
 }
 
 #include "SystemZGenDisassemblerTables.inc"
 
 DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                                  ArrayRef<uint8_t> Bytes,
                                                  uint64_t Address,

llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp

static const unsigned MiscRegDecoderTable[] = {
     VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
     VE::PMC0,       VE::PMC1,       VE::PMC2,       VE::PMC3,
     VE::PMC4,       VE::PMC5,       VE::PMC6,       VE::PMC7,
     VE::PMC8,       VE::PMC9,       VE::PMC10,      VE::PMC11,
     VE::PMC12,      VE::PMC13,      VE::PMC14};
 
 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 63)
     return MCDisassembler::Fail;
   unsigned Reg = I32RegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 63)
     return MCDisassembler::Fail;
   unsigned Reg = I64RegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (RegNo > 63)
     return MCDisassembler::Fail;
   unsigned Reg = F32RegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo % 2 || RegNo > 63)
     return MCDisassembler::Fail;
   unsigned Reg = F128RegDecoderTable[RegNo / 2];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   unsigned Reg = VE::NoRegister;
   if (RegNo == 255)
     Reg = VE::VIX;
   else if (RegNo > 63)
     return MCDisassembler::Fail;
   else
     Reg = V64RegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
   unsigned Reg = VMRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder) {
+                                             const MCDisassembler *Decoder) {
   if (RegNo % 2 || RegNo > 15)
     return MCDisassembler::Fail;
   unsigned Reg = VM512RegDecoderTable[RegNo / 2];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
-                                            const void *Decoder) {
+                                            const MCDisassembler *Decoder) {
   if (RegNo > 30)
     return MCDisassembler::Fail;
   unsigned Reg = MiscRegDecoderTable[RegNo];
   if (Reg == VE::NoRegister)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address,
-                              const void *Decoder);
+                              const MCDisassembler *Decoder);
 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                  const void *Decoder);
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                  const void *Decoder);
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                  const void *Decoder);
+                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
-                                     uint64_t Address, const void *Decoder);
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder);
 static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
-                               const void *Decoder);
+                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                const void *Decoder);
+                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeSIMM32(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus DecodeRDOperand(MCInst &Inst, uint64_t insn,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn,
                                           uint64_t Address,
-                                          const void *Decoder);
+                                          const MCDisassembler *Decoder);
 static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn,
                                                 uint64_t Address,
-                                                const void *Decoder);
+                                                const MCDisassembler *Decoder);
 
 #include "VEGenDisassemblerTables.inc"
 
 /// Read four bytes from the ArrayRef and return 32 bit word.
 static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,
                                       uint64_t &Size, uint64_t &Insn,
                                       bool IsLittleEndian) {
   // We want to read exactly 8 Bytes of data.
if (Result != MCDisassembler::Fail) {
     Size = 8;
     return Result;
   }
 
   return MCDisassembler::Fail;
 }
 
 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address,
-                                   const void *Decoder);
+                                   const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address,
-                              const void *Decoder) {
+                              const MCDisassembler *Decoder) {
   unsigned sy = fieldFromInstruction(insn, 40, 7);
   bool cy = fieldFromInstruction(insn, 47, 1);
   unsigned sz = fieldFromInstruction(insn, 32, 7);
   bool cz = fieldFromInstruction(insn, 39, 1);
   uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
   DecodeStatus status;
 
   // Decode sz.
static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address,
 
   // Decode simm32.
   MI.addOperand(MCOperand::createImm(simm32));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address,
-                             const void *Decoder) {
+                             const MCDisassembler *Decoder) {
   unsigned sz = fieldFromInstruction(insn, 32, 7);
   bool cz = fieldFromInstruction(insn, 39, 1);
   uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
   DecodeStatus status;
 
   // Decode sz.
   if (cz) {
     status = DecodeI64RegisterClass(MI, sz, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   } else {
     MI.addOperand(MCOperand::createImm(0));
   }
 
   // Decode simm32.
   MI.addOperand(MCOperand::createImm(simm32));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address,
-                              const void *Decoder, bool isLoad,
+                              const MCDisassembler *Decoder, bool isLoad,
                               DecodeFunc DecodeSX) {
   unsigned sx = fieldFromInstruction(insn, 48, 7);
 
   DecodeStatus status;
   if (isLoad) {
     status = DecodeSX(MI, sx, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
 
   status = DecodeASX(MI, insn, Address, Decoder);
   if (status != MCDisassembler::Success)
     return status;
 
   if (!isLoad) {
     status = DecodeSX(MI, sx, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address,
-                                const void *Decoder, bool isLoad,
+                                const MCDisassembler *Decoder, bool isLoad,
                                 DecodeFunc DecodeSX) {
   unsigned sx = fieldFromInstruction(insn, 48, 7);
 
   DecodeStatus status;
   if (isLoad) {
     status = DecodeSX(MI, sx, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
 
   status = DecodeAS(MI, insn, Address, Decoder);
   if (status != MCDisassembler::Success)
     return status;
 
   if (!isLoad) {
     status = DecodeSX(MI, sx, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass);
 }
 
 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass);
 }
 
 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);
 }
 
 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass);
 }
 
 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
-                                  const void *Decoder) {
+                                  const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass);
 }
 
 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);
 }
 
 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   return DecodeMemAS(Inst, insn, Address, Decoder, true,
                      DecodeI64RegisterClass);
 }
 
 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
-                                     uint64_t Address, const void *Decoder) {
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
   return DecodeMemAS(Inst, insn, Address, Decoder, false,
                      DecodeI64RegisterClass);
 }
 
 static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,
-                              const void *Decoder, bool isImmOnly, bool isUImm,
-                              DecodeFunc DecodeSX) {
+                              const MCDisassembler *Decoder, bool isImmOnly,
+                              bool isUImm, DecodeFunc DecodeSX) {
   unsigned sx = fieldFromInstruction(insn, 48, 7);
   bool cy = fieldFromInstruction(insn, 47, 1);
   unsigned sy = fieldFromInstruction(insn, 40, 7);
 
   // Add $sx.
   DecodeStatus status;
   status = DecodeSX(MI, sx, Address, Decoder);
   if (status != MCDisassembler::Success)
static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,
   status = DecodeSX(MI, sx, Address, Decoder);
   if (status != MCDisassembler::Success)
     return status;
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address,
-                                   const void *Decoder) {
+                                   const MCDisassembler *Decoder) {
   return DecodeCAS(MI, insn, Address, Decoder, false, true,
                    DecodeI64RegisterClass);
 }
 
 static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address,
-                                   const void *Decoder) {
+                                   const MCDisassembler *Decoder) {
   return DecodeCAS(MI, insn, Address, Decoder, false, true,
                    DecodeI32RegisterClass);
 }
 
 static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   return DecodeCAS(MI, insn, Address, Decoder, false, false,
                    DecodeI64RegisterClass);
 }
 
 static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   return DecodeCAS(MI, insn, Address, Decoder, false, false,
                    DecodeI32RegisterClass);
 }
 
 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
-                               const void *Decoder) {
+                               const MCDisassembler *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);
 }
 
 static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address,
-                                const void *Decoder) {
+                                const MCDisassembler *Decoder) {
   uint64_t tgt = SignExtend64<7>(insn);
   MI.addOperand(MCOperand::createImm(tgt));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSIMM32(MCInst &MI, uint64_t insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   uint64_t tgt = SignExtend64<32>(insn);
   MI.addOperand(MCOperand::createImm(tgt));
   return MCDisassembler::Success;
 }
 
 static bool isIntegerBCKind(MCInst &MI) {
 
 #define BCm_kind(NAME)                                                         \
#define BCRm_kind(NAME)                                                        \
   }
 #undef BCm_kind
 
   return false;
 }
 
 // Decode CC Operand field.
 static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address,
-                                    const void *Decoder) {
+                                    const MCDisassembler *Decoder) {
   MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));
   return MCDisassembler::Success;
 }
 
 // Decode RD Operand field.
 static DecodeStatus DecodeRDOperand(MCInst &MI, uint64_t cf, uint64_t Address,
-                                    const void *Decoder) {
+                                    const MCDisassembler *Decoder) {
   MI.addOperand(MCOperand::createImm(VEValToRD(cf)));
   return MCDisassembler::Success;
 }
 
 // Decode branch condition instruction and CCOperand field in it.
 static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn,
                                           uint64_t Address,
-                                          const void *Decoder) {
+                                          const MCDisassembler *Decoder) {
   unsigned cf = fieldFromInstruction(insn, 48, 4);
   bool cy = fieldFromInstruction(insn, 47, 1);
   unsigned sy = fieldFromInstruction(insn, 40, 7);
 
   // Decode cf.
   MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));
 
   // Decode sy.
   DecodeStatus status;
   if (cy) {
     status = DecodeI64RegisterClass(MI, sy, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   } else {
     MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
   }
 
   // Decode MEMri.
   return DecodeAS(MI, insn, Address, Decoder);
 }
 
 static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn,
                                                 uint64_t Address,
-                                                const void *Decoder) {
+                                                const MCDisassembler *Decoder) {
   // Decode MEMri.
   return DecodeAS(MI, insn, Address, Decoder);
 }

llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

if (Bytes.size() < 4) {
     return false;
   }
   // Encoded as a little-endian 32-bit word in the stream.
   Insn =
       (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
   return true;
 }
 
-static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
-  const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
-  const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
+static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
+  const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 }
 
-static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
-                                              unsigned RegNo,
+static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder);
+                                              const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder);
+                                             const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
-                                      uint64_t Address, const void *Decoder);
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder);
-
-static DecodeStatus Decode2RInstruction(MCInst &Inst,
-                                        unsigned Insn,
                                         uint64_t Address,
-                                        const void *Decoder);
+                                        const MCDisassembler *Decoder);
 
-static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
-                                           unsigned Insn,
-                                           uint64_t Address,
-                                           const void *Decoder);
+static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,
+                                        const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
-                                         unsigned Insn,
+static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
-                                         const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
-static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
-                                              unsigned Insn,
-                                              uint64_t Address,
-                                              const void *Decoder);
+static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,
+                                         const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
-                                         unsigned Insn,
+static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,
                                               uint64_t Address,
-                                         const void *Decoder);
+                                              const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
-                                             unsigned Insn,
-                                             uint64_t Address,
-                                             const void *Decoder);
+static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,
+                                         const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
-                                                   unsigned Insn,
-                                                   uint64_t Address,
-                                                   const void *Decoder);
+static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,
+                                             const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
-                                         unsigned Insn,
-                                         uint64_t Address,
-                                         const void *Decoder);
+static DecodeStatus
+DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
-                                          unsigned Insn,
-                                          uint64_t Address,
-                                          const void *Decoder);
+static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn,
+                                         const MCDisassembler *Decoder);
 
-static DecodeStatus Decode3RInstruction(MCInst &Inst,
-                                        unsigned Insn,
+static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn,
                                           uint64_t Address,
-                                        const void *Decoder);
+                                          const MCDisassembler *Decoder);
 
-static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
-                                           unsigned Insn,
-                                           uint64_t Address,
-                                           const void *Decoder);
+static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn,
+                                        const MCDisassembler *Decoder);
 
-static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
-                                          unsigned Insn,
+static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
-                                          const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
-static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
-                                              unsigned Insn,
-                                              uint64_t Address,
-                                              const void *Decoder);
+static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn,
+                                          const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
-                                         unsigned Insn,
+static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
                                               uint64_t Address,
-                                         const void *Decoder);
+                                              const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
-                                               unsigned Insn,
-                                               uint64_t Address,
-                                               const void *Decoder);
+static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn,
+                                         const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
-                                           unsigned Insn,
+static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn,
                                                uint64_t Address,
-                                           const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
-                                               unsigned Insn,
-                                               uint64_t Address,
-                                               const void *Decoder);
+static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn,
+                                           const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
-                                         unsigned Insn,
+static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
                                                uint64_t Address,
-                                         const void *Decoder);
+                                               const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
-                                         unsigned Insn,
+static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn,
                                          uint64_t Address,
-                                         const void *Decoder);
+                                         const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
-                                               unsigned Insn,
-                                               uint64_t Address,
-                                               const void *Decoder);
+static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn,
+                                         const MCDisassembler *Decoder);
 
-static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
-                                                     unsigned Insn,
-                                                     uint64_t Address,
-                                                     const void *Decoder);
+static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn,
+                                               const MCDisassembler *Decoder);
+
+static DecodeStatus
+DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const MCDisassembler *Decoder);
 
 #include "XCoreGenDisassemblerTables.inc"
 
-static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
-                                              unsigned RegNo,
+static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
-                                              const void *Decoder)
-{
+                                              const MCDisassembler *Decoder) {
   if (RegNo > 11)
     return MCDisassembler::Fail;
   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
-                                             unsigned RegNo,
+static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
-                                             const void *Decoder)
-{
+                                             const MCDisassembler *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
   unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
-                                      uint64_t Address, const void *Decoder) {
+                                      uint64_t Address,
+                                      const MCDisassembler *Decoder) {
   if (Val > 11)
     return MCDisassembler::Fail;
   static const unsigned Values[] = {
     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
   };
   Inst.addOperand(MCOperand::createImm(Values[Val]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   Inst.addOperand(MCOperand::createImm(-(int64_t)Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus
 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
   if (Combined < 27)
Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
   unsigned Op2High = (Combined / 3) % 3;
   unsigned Op3High = Combined / 9;
   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
   return MCDisassembler::Success;
 }
 
-static DecodeStatus
-Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
-                         const void *Decoder) {
+static DecodeStatus Decode2OpInstructionFail(MCInst &Inst, unsigned Insn,
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   // Try and decode as a 3R instruction.
   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
   switch (Opcode) {
   case 0x0:
     Inst.setOpcode(XCore::STW_2rus);
     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
   case 0x1:
     Inst.setOpcode(XCore::LDW_2rus);
case 0x18:
     return Decode3RInstruction(Inst, Insn, Address, Decoder);
   case 0x19:
     Inst.setOpcode(XCore::LSU_3r);
     return Decode3RInstruction(Inst, Insn, Address, Decoder);
   }
   return MCDisassembler::Fail;
 }
 
-static DecodeStatus
-Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                    const void *Decoder) {
+static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   unsigned Op1, Op2;
   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
   if (S != MCDisassembler::Success)
     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
   return S;
 }
 
-static DecodeStatus
-Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                       const void *Decoder) {
+static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   unsigned Op1, Op2;
   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
   if (S != MCDisassembler::Success)
     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 
   Inst.addOperand(MCOperand::createImm(Op1));
   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
   return S;
 }
 
-static DecodeStatus
-DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                     const void *Decoder) {
+static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   unsigned Op1, Op2;
   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
   if (S != MCDisassembler::Success)
     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
   return S;
 }
 
-static DecodeStatus
-Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                          const void *Decoder) {
+static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
   unsigned Op1, Op2;
   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
   if (S != MCDisassembler::Success)
     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
   return S;
 }
 
-static DecodeStatus
-DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                     const void *Decoder) {
+static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   unsigned Op1, Op2;
   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
   if (S != MCDisassembler::Success)
     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   Inst.addOperand(MCOperand::createImm(Op2));
   return S;
 }
 
-static DecodeStatus
-DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                         const void *Decoder) {
+static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   unsigned Op1, Op2;
   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
   if (S != MCDisassembler::Success)
     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeBitpOperand(Inst, Op2, Address, Decoder);
   return S;
 }
 
 static DecodeStatus
 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                               const void *Decoder) {
+                               const MCDisassembler *Decoder) {
   unsigned Op1, Op2;
   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
   if (S != MCDisassembler::Success)
     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeBitpOperand(Inst, Op2, Address, Decoder);
   return S;
 }
 
-static DecodeStatus
-DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
-                          const void *Decoder) {
+static DecodeStatus DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
   // Try and decode as a L3R / L2RUS instruction.
   unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
                     fieldFromInstruction(Insn, 27, 5) << 4;
   switch (Opcode) {
   case 0x0c:
     Inst.setOpcode(XCore::STW_l3r);
     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
   case 0x1c:
case 0x18c:
     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
   case 0x19c:
     Inst.setOpcode(XCore::REMU_l3r);
     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
   }
   return MCDisassembler::Fail;
 }
 
-static DecodeStatus
-DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                               const void *Decoder) {
+static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   unsigned Op1, Op2;
   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
                                         Op1, Op2);
   if (S != MCDisassembler::Success)
     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
   return S;
 }
 
-static DecodeStatus
-DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                               const void *Decoder) {
+static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn,
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   unsigned Op1, Op2;
   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
                                         Op1, Op2);
   if (S != MCDisassembler::Success)
     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 
   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   return S;
 }
 
-static DecodeStatus
-Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                    const void *Decoder) {
+static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn,
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
   }
   return S;
 }
 
-static DecodeStatus
-Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                       const void *Decoder) {
+static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn,
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     Inst.addOperand(MCOperand::createImm(Op1));
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
   }
   return S;
 }
 
-static DecodeStatus
-Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                      const void *Decoder) {
+static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn,
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
     Inst.addOperand(MCOperand::createImm(Op3));
   }
   return S;
 }
 
-static DecodeStatus
-Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                      const void *Decoder) {
+static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
     DecodeBitpOperand(Inst, Op3, Address, Decoder);
   }
   return S;
 }
 
-static DecodeStatus
-DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                     const void *Decoder) {
+static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S =
     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
   }
   return S;
 }
 
-static DecodeStatus
-DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                           const void *Decoder) {
+static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S =
   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
   }
   return S;
 }
 
-static DecodeStatus
-DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                       const void *Decoder) {
+static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn,
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S =
   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
     Inst.addOperand(MCOperand::createImm(Op3));
   }
   return S;
 }
 
-static DecodeStatus
-DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                           const void *Decoder) {
+static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S =
   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
     DecodeBitpOperand(Inst, Op3, Address, Decoder);
   }
   return S;
 }
 
-static DecodeStatus
-DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                     const void *Decoder) {
+static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3, Op4, Op5, Op6;
   DecodeStatus S =
     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S != MCDisassembler::Success)
     return S;
   S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
   if (S != MCDisassembler::Success)
     return S;
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
   return S;
 }
 
-static DecodeStatus
-DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
-                     const void *Decoder) {
+static DecodeStatus DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn,
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
   // Try and decode as a L6R instruction.
   Inst.clear();
   unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
   switch (Opcode) {
   case 0x00:
     Inst.setOpcode(XCore::LMUL_l6r);
     return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
   }
   return MCDisassembler::Fail;
 }
 
-static DecodeStatus
-DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                     const void *Decoder) {
+static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3, Op4, Op5;
   DecodeStatus S =
     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S != MCDisassembler::Success)
     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
   S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
   if (S != MCDisassembler::Success)
     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 
   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
   return S;
 }
 
-static DecodeStatus
-DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                           const void *Decoder) {
+static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
   DecodeStatus S =
     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
   }
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
   }
   return S;
 }
 
 static DecodeStatus
 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
   DecodeStatus S =
   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
   }

llvm/utils/TableGen/FixedLenDecoderEmitter.cpp

 void FixedLenDecoderEmitter::
 emitDecoderFunction(formatted_raw_ostream &OS, DecoderSet &Decoders,
                     unsigned Indentation) const {
   // The decoder function is just a big switch statement based on the
   // input decoder index.
   OS.indent(Indentation) << "template <typename InsnType>\n";
   OS.indent(Indentation) << "static DecodeStatus decodeToMCInst(DecodeStatus S,"
     << " unsigned Idx, InsnType insn, MCInst &MI,\n";
-  OS.indent(Indentation) << "                                   uint64_t "
-    << "Address, const void *Decoder, bool &DecodeComplete) {\n";
+  OS.indent(Indentation)
+      << "                                   uint64_t "
+      << "Address, const MCDisassembler *Decoder, bool &DecodeComplete) {\n";
   Indentation += 2;
   OS.indent(Indentation) << "DecodeComplete = true;\n";
   // TODO: When InsnType is large, using uint64_t limits all fields to 64 bits
   // It would be better for emitBinaryParser to use a 64-bit tmp whenever
   // possible but fall back to an InsnType-sized tmp for truly large fields.
   OS.indent(Indentation) << "using TmpType = "
                             "std::conditional_t<std::is_integral<InsnType>::"
                             "value, InsnType, uint64_t>;\n";

 // emitDecodeInstruction - Emit the templated helper function
 // decodeInstruction().
 static void emitDecodeInstruction(formatted_raw_ostream &OS) {
   OS << "template <typename InsnType>\n"
      << "static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], "
         "MCInst &MI,\n"
      << "                                      InsnType insn, uint64_t "
         "Address,\n"
-     << "                                      const void *DisAsm,\n"
+     << "                                      const MCDisassembler *DisAsm,\n"
      << "                                      const MCSubtargetInfo &STI) {\n"
      << "  const FeatureBitset &Bits = STI.getFeatureBits();\n"
      << "\n"
      << "  const uint8_t *Ptr = DecodeTable;\n"
      << "  InsnType CurFieldValue = 0;\n"
      << "  DecodeStatus S = MCDisassembler::Success;\n"
      << "  while (true) {\n"
      << "    ptrdiff_t Loc = Ptr - DecodeTable;\n"