[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.

[craig.topper]

Summary

If we have a variable shift amount and the demanded mask has leading
zeros, we can propagate those leading zeros to not demand those bits
from operand 0. This can allow zero_extend/sign_extend to become
any_extend. This pattern can occur due to C integer promotion rules.

This transform is already done by InstCombineSimplifyDemanded.cpp where
sign_extend can be turned into zero_extend for example.

[arsenm]

Seems like it should get a dedicated test to stress the edge cases

[RKSimon]

In D121833#3387866, @arsenm wrote:

Seems like it should get a dedicated test to stress the edge cases

SGTM - @foad do you have any particular concerns or tests you'd expect?

[foad]

LGTM (modulo Matt's request for more tests). Obviously we could do the same thing for low order bits for right shifts.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

1683

Need to drop poison flags here.

[craig.topper]

Rebase

[craig.topper]

Drop poison flags

[craig.topper]

Slightly simplify the RISCV tests.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

1690

Having reviewed what happens on the RISCV test cases for dropping poison, I think this can be simplified both here and in ISD::ADD/SUB/MUL. I've posted D129511 for that simplification. If it's accepted I'll apply it here too.

[craig.topper]

Simplify dropping poison flags.
More directed tests.

[spatel]

LGTM

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (const APInt *SA =
       // low bits known zero.
       Known.Zero.setLowBits(ShAmt);
 
       // Try shrinking the operation as long as the shift amount will still be
       // in range.
       if ((ShAmt < DemandedBits.getActiveBits()) &&
           ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
         return true;
+    } else {
+      // This is a variable shift, so we can't shift the demand mask by a known
+      // amount. But if we are not demanding high bits, then we are not
+      // demanding those bits from the pre-shifted operand either.
+      if (unsigned CTLZ = DemandedBits.countLeadingZeros()) {
+        APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ));
+        if (SimplifyDemandedBits(Op0, DemandedFromOp, DemandedElts, Known, TLO, Depth + 1))
+          return true;
+        Known.resetAll();
+      }
     }
 
     // If we are only demanding sign bits then we can use the shift source
     // directly.
     if (const APInt *MaxSA =
             TLO.DAG.getValidMaximumShiftAmountConstant(Op, DemandedElts)) {
       unsigned ShAmt = MaxSA->getZExtValue();
       unsigned NumSignBits =
           TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
       unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros();
       if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits))
         return TLO.CombineTo(Op, Op0);
     }

llvm/test/CodeGen/AMDGPU/shl.ll

 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: shl_v2i16:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 2, @12, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @8
 ; EG-NEXT:    ALU 0, @15, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @10
-; EG-NEXT:    ALU 12, @16, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 11, @16, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T7.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 8:
 ; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 4, #1
 ; EG-NEXT:    Fetch clause starting at 10:
 ; EG-NEXT:     VTX_READ_32 T7.X, T7.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 12:
 ; EG-NEXT:     LSHL * T0.W, T0.X, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ; EG-NEXT:     ADD_INT * T0.X, KC0[2].Z, PV.W,
 ; EG-NEXT:    ALU clause starting at 15:
 ; EG-NEXT:     MOV * T7.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 16:
-; EG-NEXT:     AND_INT T0.Y, T0.X, literal.x,
-; EG-NEXT:     AND_INT T0.Z, T7.X, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT:     AND_INT T0.Z, T0.X, literal.x,
 ; EG-NEXT:     LSHR T0.W, T0.X, literal.y,
 ; EG-NEXT:     LSHR * T1.W, T7.X, literal.y,
 ; EG-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
 ; EG-NEXT:     LSHL T0.W, PS, PV.W,
-; EG-NEXT:     LSHL * T1.W, PV.Z, PV.Y,
+; EG-NEXT:     LSHL * T1.W, T7.X, PV.Z,
 ; EG-NEXT:     AND_INT T1.W, PS, literal.x,
 ; EG-NEXT:     LSHL * T0.W, PV.W, literal.y,
 ; EG-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
 ; EG-NEXT:     OR_INT T0.X, PV.W, PS,
 ; EG-NEXT:     LSHR * T7.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
   %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i32 %tid

 ; VI-NEXT:    v_or_b32_e32 v0, v3, v0
 ; VI-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: shl_v4i16:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 2, @8, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @6
-; EG-NEXT:    ALU 53, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 51, @11, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T10.XY, T0.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_128 T10.XYZW, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 8:
 ; EG-NEXT:     LSHL * T0.W, T0.X, literal.x,
 ; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
 ; EG-NEXT:     ADD_INT * T0.X, KC0[2].Z, PV.W,
 ; EG-NEXT:    ALU clause starting at 11:
 ; EG-NEXT:     MOV T4.X, T10.X,
 ; EG-NEXT:     MOV * T5.X, T10.Y,
 ; EG-NEXT:     MOV T0.X, PV.X,
 ; EG-NEXT:     MOV T0.Y, PS,
 ; EG-NEXT:     MOV * T2.X, T10.Z,
 ; EG-NEXT:     MOV T3.X, T10.W,
 ; EG-NEXT:     MOV * T0.Z, T6.X,
 ; EG-NEXT:     MOV * T1.Y, T2.X,
-; EG-NEXT:     AND_INT T1.W, PV.Y, literal.x,
-; EG-NEXT:     AND_INT * T2.W, T0.X, literal.x,
+; EG-NEXT:     AND_INT * T1.W, PV.Y, literal.x,
 ; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
-; EG-NEXT:     LSHL * T1.W, PS, PV.W,
+; EG-NEXT:     LSHL * T1.W, T0.X, PV.W,
 ; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
 ; EG-NEXT:     AND_INT * T2.W, T0.Z, literal.y,
 ; EG-NEXT:    65535(9.183409e-41), -65536(nan)
 ; EG-NEXT:     OR_INT * T1.W, PS, PV.W,
 ; EG-NEXT:     MOV * T0.Z, T3.X,
 ; EG-NEXT:     MOV * T6.X, T1.W,
 ; EG-NEXT:     MOV T1.Z, PV.X,
 ; EG-NEXT:     LSHR T1.W, T1.Y, literal.x,
 ; EG-NEXT:     LSHR * T2.W, T0.X, literal.x,
 ; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
 ; EG-NEXT:     LSHL T1.W, PS, PV.W,
 ; EG-NEXT:     AND_INT * T2.W, PV.Z, literal.x,
 ; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
 ; EG-NEXT:     LSHL * T1.W, PV.W, literal.x,
 ; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
 ; EG-NEXT:     OR_INT * T1.W, T2.W, PV.W,
 ; EG-NEXT:     MOV T6.X, PV.W,
 ; EG-NEXT:     MOV * T0.X, T7.X,
-; EG-NEXT:     AND_INT T1.W, T0.Z, literal.x,
-; EG-NEXT:     AND_INT * T2.W, T0.Y, literal.x,
+; EG-NEXT:     AND_INT * T1.W, T0.Z, literal.x,
 ; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
-; EG-NEXT:     LSHL T1.W, PS, PV.W,
+; EG-NEXT:     LSHL T1.W, T0.Y, PV.W,
 ; EG-NEXT:     AND_INT * T2.W, T0.X, literal.x,
 ; EG-NEXT:    -65536(nan), 0(0.000000e+00)
 ; EG-NEXT:     AND_INT * T1.W, PV.W, literal.x,
 ; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
 ; EG-NEXT:     OR_INT * T1.W, T2.W, PV.W,
 ; EG-NEXT:     MOV * T7.X, PV.W,
 ; EG-NEXT:     MOV T0.X, PV.X,
 ; EG-NEXT:     LSHR T1.W, T0.Z, literal.x,

llvm/test/CodeGen/AMDGPU/shl.v2i16.ll

 ; GFX9-NEXT:    v_pk_lshlrev_b16 v0, s3, v0
 ; GFX9-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; VI-LABEL: s_shl_v2i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    s_mov_b32 s6, 0xffff
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    s_and_b32 s7, s4, s6
-; VI-NEXT:    s_lshr_b32 s4, s4, 16
-; VI-NEXT:    s_lshr_b32 s8, s5, 16
-; VI-NEXT:    s_lshl_b32 s4, s4, s8
-; VI-NEXT:    s_lshl_b32 s5, s7, s5
-; VI-NEXT:    s_lshl_b32 s4, s4, 16
-; VI-NEXT:    s_and_b32 s5, s5, s6
-; VI-NEXT:    s_or_b32 s4, s5, s4
+; VI-NEXT:    s_lshr_b32 s6, s4, 16
+; VI-NEXT:    s_lshr_b32 s7, s5, 16
+; VI-NEXT:    s_lshl_b32 s6, s6, s7
+; VI-NEXT:    s_lshl_b32 s4, s4, s5
+; VI-NEXT:    s_lshl_b32 s5, s6, 16
+; VI-NEXT:    s_and_b32 s4, s4, 0xffff
+; VI-NEXT:    s_or_b32 s4, s4, s5
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: s_shl_v2i16:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
 ; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9

llvm/test/CodeGen/RISCV/alu16.ll

; RV64I-NEXT:    ret
   %1 = shl i16 %a, %b
   ret i16 %1
 }
 
 ; Test the pattern we get from C integer promotion.
 define void @sll_ext(i16 %a, i16 %b, i16* %p) nounwind {
 ; RV32I-LABEL: sll_ext:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a0, a0, 16
-; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    sll a0, a0, a1
 ; RV32I-NEXT:    sh a0, 0(a2)
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sll_ext:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 48
-; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    sllw a0, a0, a1
 ; RV64I-NEXT:    sh a0, 0(a2)
 ; RV64I-NEXT:    ret
   %1 = zext i16 %a to i32
   %2 = zext i16 %b to i32
   %3 = shl i32 %1, %2
   %4 = trunc i32 %3 to i16
   store i16 %4, i16* %p

llvm/test/CodeGen/RISCV/alu8.ll

; RV64I-NEXT:    ret
   %1 = shl i8 %a, %b
   ret i8 %1
 }
 
 ; Test the pattern we get from C integer promotion.
 define void @sll_ext(i8 %a, i8 %b, i8* %p) nounwind {
 ; RV32I-LABEL: sll_ext:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 255
 ; RV32I-NEXT:    sll a0, a0, a1
 ; RV32I-NEXT:    sb a0, 0(a2)
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sll_ext:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
 ; RV64I-NEXT:    sllw a0, a0, a1
 ; RV64I-NEXT:    sb a0, 0(a2)
 ; RV64I-NEXT:    ret
   %1 = zext i8 %a to i32
   %2 = zext i8 %b to i32
   %3 = shl i32 %1, %2
   %4 = trunc i32 %3 to i8
   store i8 %4, i8* %p

llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll

 ; CHECK-LABEL: b:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    .setfp r7, sp, #12
 ; CHECK-NEXT:    add r7, sp, #12
 ; CHECK-NEXT:    .save {r8, r9, r10, r11}
 ; CHECK-NEXT:    push.w {r8, r9, r10, r11}
-; CHECK-NEXT:    .pad #12
-; CHECK-NEXT:    sub sp, #12
+; CHECK-NEXT:    .pad #16
+; CHECK-NEXT:    sub sp, #16
 ; CHECK-NEXT:    wls lr, r1, .LBB2_3
 ; CHECK-NEXT:  @ %bb.1: @ %while.body.preheader
-; CHECK-NEXT:    mov r4, r2
-; CHECK-NEXT:    adds r2, r3, #4
-; CHECK-NEXT:    add.w r9, r0, #4
-; CHECK-NEXT:    mvn r11, #1
-; CHECK-NEXT:    @ implicit-def: $r6
-; CHECK-NEXT:    @ implicit-def: $r12
-; CHECK-NEXT:    str r4, [sp] @ 4-byte Spill
+; CHECK-NEXT:    mov r12, r0
+; CHECK-NEXT:    add.w r10, r3, #4
+; CHECK-NEXT:    adds r0, #4
+; CHECK-NEXT:    mvn r9, #1
+; CHECK-NEXT:    @ implicit-def: $r8
+; CHECK-NEXT:    @ implicit-def: $r4
+; CHECK-NEXT:    str r2, [sp] @ 4-byte Spill
 ; CHECK-NEXT:  .LBB2_2: @ %while.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ldr r1, [r9, #-4]
-; CHECK-NEXT:    ldr.w r10, [r2]
-; CHECK-NEXT:    str r0, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT:    muls r1, r3, r1
-; CHECK-NEXT:    adds.w r8, r1, #-2147483648
-; CHECK-NEXT:    asr.w r5, r1, #31
-; CHECK-NEXT:    adc r1, r5, #0
-; CHECK-NEXT:    mul r5, r10, r0
-; CHECK-NEXT:    mov r0, r2
-; CHECK-NEXT:    ldr.w r2, [r11, #4]
-; CHECK-NEXT:    str r2, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT:    ldr r2, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT:    add.w r5, r5, #-2147483648
-; CHECK-NEXT:    asrl r8, r1, r5
-; CHECK-NEXT:    smull r4, r5, r10, r8
-; CHECK-NEXT:    lsll r4, r5, #30
-; CHECK-NEXT:    asrs r1, r5, #31
-; CHECK-NEXT:    mov r4, r5
-; CHECK-NEXT:    lsll r4, r1, r10
-; CHECK-NEXT:    lsll r4, r1, #30
-; CHECK-NEXT:    ldr.w r4, [r11]
-; CHECK-NEXT:    asrs r5, r1, #31
-; CHECK-NEXT:    mov r8, r1
-; CHECK-NEXT:    muls r4, r6, r4
-; CHECK-NEXT:    adds r4, #2
-; CHECK-NEXT:    lsll r8, r5, r4
-; CHECK-NEXT:    ldr r4, [r9], #4
-; CHECK-NEXT:    asr.w r5, r12, #31
-; CHECK-NEXT:    add.w r8, r8, #-2147483648
+; CHECK-NEXT:    ldr r2, [r0]
+; CHECK-NEXT:    asrs r5, r4, #31
+; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT:    muls r2, r3, r2
+; CHECK-NEXT:    adds r4, r4, r2
+; CHECK-NEXT:    adc.w r2, r5, r2, asr #31
+; CHECK-NEXT:    ldr.w r5, [r9, #4]
+; CHECK-NEXT:    adds.w r4, r4, #-2147483648
+; CHECK-NEXT:    adc r1, r2, #0
+; CHECK-NEXT:    str r1, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT:    smull r5, r6, r5, r8
+; CHECK-NEXT:    ldr.w r2, [r9]
+; CHECK-NEXT:    asrs r4, r1, #31
+; CHECK-NEXT:    str r2, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT:    subs r5, r1, r5
+; CHECK-NEXT:    sbcs r4, r6
+; CHECK-NEXT:    adds.w r6, r5, #-2147483648
+; CHECK-NEXT:    adc r5, r4, #0
+; CHECK-NEXT:    ldr r4, [r0, #-4]
 ; CHECK-NEXT:    muls r4, r3, r4
 ; CHECK-NEXT:    adds r3, #4
-; CHECK-NEXT:    adds.w r1, r12, r4
-; CHECK-NEXT:    adc.w r5, r5, r4, asr #31
-; CHECK-NEXT:    smull r6, r4, r2, r6
-; CHECK-NEXT:    adds.w r1, r1, #-2147483648
-; CHECK-NEXT:    adc r1, r5, #0
-; CHECK-NEXT:    mov r2, r0
-; CHECK-NEXT:    asrs r5, r1, #31
-; CHECK-NEXT:    subs r6, r1, r6
-; CHECK-NEXT:    sbcs r5, r4
-; CHECK-NEXT:    adds.w r6, r6, #-2147483648
-; CHECK-NEXT:    adc r5, r5, #0
-; CHECK-NEXT:    asrl r6, r5, r8
+; CHECK-NEXT:    adds.w r0, r4, #-2147483648
+; CHECK-NEXT:    asr.w r1, r4, #31
+; CHECK-NEXT:    ldr.w r4, [r10]
+; CHECK-NEXT:    adc r1, r1, #0
+; CHECK-NEXT:    mul r2, r4, r12
+; CHECK-NEXT:    add.w r12, r12, #4
+; CHECK-NEXT:    add.w r2, r2, #-2147483648
+; CHECK-NEXT:    asrl r0, r1, r2
+; CHECK-NEXT:    ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT:    smull r0, r1, r4, r0
+; CHECK-NEXT:    lsll r0, r1, #30
+; CHECK-NEXT:    asr.w r11, r1, #31
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    ldr r1, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT:    lsll r0, r11, r4
+; CHECK-NEXT:    lsrl r0, r11, #2
+; CHECK-NEXT:    mul r1, r1, r8
+; CHECK-NEXT:    adds r1, #2
+; CHECK-NEXT:    lsll r0, r11, r1
+; CHECK-NEXT:    ldr r1, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT:    add.w r0, r0, #-2147483648
+; CHECK-NEXT:    asrl r6, r5, r0
+; CHECK-NEXT:    movs r0, #2
 ; CHECK-NEXT:    lsrl r6, r5, #2
-; CHECK-NEXT:    movs r5, #2
-; CHECK-NEXT:    str r6, [r5]
-; CHECK-NEXT:    ldr r5, [r11], #-4
-; CHECK-NEXT:    mls r1, r5, r10, r1
-; CHECK-NEXT:    adds.w r12, r1, #-2147483648
-; CHECK-NEXT:    asr.w r4, r1, #31
-; CHECK-NEXT:    adc r1, r4, #0
-; CHECK-NEXT:    ldrd r4, r0, [sp] @ 8-byte Folded Reload
-; CHECK-NEXT:    lsrl r12, r1, #2
-; CHECK-NEXT:    rsb.w r1, r12, #0
+; CHECK-NEXT:    str r6, [r0]
+; CHECK-NEXT:    mov r8, r6
+; CHECK-NEXT:    ldr r0, [r9], #-4
+; CHECK-NEXT:    mls r0, r0, r4, r1
+; CHECK-NEXT:    adds.w r4, r0, #-2147483648
+; CHECK-NEXT:    asr.w r1, r0, #31
+; CHECK-NEXT:    adc r1, r1, #0
+; CHECK-NEXT:    lsrl r4, r1, #2
+; CHECK-NEXT:    rsbs r0, r4, #0
+; CHECK-NEXT:    str r0, [r2]
+; CHECK-NEXT:    str r0, [r10, #-4]
+; CHECK-NEXT:    add.w r10, r10, #4
+; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
 ; CHECK-NEXT:    adds r0, #4
-; CHECK-NEXT:    str r1, [r4]
-; CHECK-NEXT:    str r1, [r2, #-4]
-; CHECK-NEXT:    adds r2, #4
 ; CHECK-NEXT:    le lr, .LBB2_2
 ; CHECK-NEXT:  .LBB2_3: @ %while.end
-; CHECK-NEXT:    add sp, #12
+; CHECK-NEXT:    add sp, #16
 ; CHECK-NEXT:    pop.w {r8, r9, r10, r11}
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
 entry:
   %0 = inttoptr i32 %e to i32*
   %tobool.not70 = icmp eq i32 %d, 0
   br i1 %tobool.not70, label %while.end, label %while.body
 
 while.body:                                       ; preds = %entry, %while.body