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[AArch64][SVE] Implement PFALSE with explicit AArch64ISD node.
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Authored by sdesmalen on Jan 24 2022, 9:51 AM.

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Summary

The ISel patterns for PFALSE helps recognise the instructions as being
free of side-effects, which helps MachineCSE remove redundant
PFALSE instructions.

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sdesmalen created this revision.Jan 24 2022, 9:51 AM
sdesmalen requested review of this revision.Jan 24 2022, 9:51 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 24 2022, 9:51 AM

It looks like AArch64TargetLowering::LowerSPLAT_VECTOR is using DAG.getMachineNode in an inappropriate way: generally, in SelectionDAG, we shouldn't be creating Machine nodes before isel (AArch64DAGToDAGISel::Select). The "proper" construct is to define AArch64ISD::PFALSE, then add a pattern to lower it during isel.

The reason I bring this up is that hasSideEffects is usually inferred from isel patterns.

sdesmalen updated this revision to Diff 402842.Jan 25 2022, 4:20 AM

Implement with AArch64ISD::PFALSE and patterns.

It looks like AArch64TargetLowering::LowerSPLAT_VECTOR is using DAG.getMachineNode in an inappropriate way: generally, in SelectionDAG, we shouldn't be creating Machine nodes before isel (AArch64DAGToDAGISel::Select). The "proper" construct is to define AArch64ISD::PFALSE, then add a pattern to lower it during isel.

The reason I bring this up is that hasSideEffects is usually inferred from isel patterns.

Ah that makes a lot of sense! I was a bit puzzled as to why it just worked for PTRUE, but not for PFALSE.
I've reimplemented it now by creating an explicit AArch64ISD node for it instead with patterns.

sdesmalen retitled this revision from [AArch64][SVE] Mark PFALSE as side-effect free. to [AArch64][SVE] Implement PFALSE with explicit AArch64ISD node..Jan 25 2022, 4:23 AM
sdesmalen edited the summary of this revision. (Show Details)
dmgreen added inline comments.
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
2202–2203

Add a case here too, so it gets printed nicely in debug output.

llvm/lib/Target/AArch64/SVEInstrFormats.td
337

Does SDTCVecEltisVT imply SDTCisVec?

sdesmalen updated this revision to Diff 402883.Jan 25 2022, 6:17 AM

Added CASE statement for pretty printing of node.

sdesmalen added inline comments.Jan 25 2022, 6:18 AM
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
2202–2203

Good spot, cheers!

llvm/lib/Target/AArch64/SVEInstrFormats.td
337

Not sure, but when I add a pattern with i1 type, tblgen seems to go into an infinite loop.

dmgreen accepted this revision.Jan 25 2022, 2:00 PM

Thanks. LGTM

llvm/lib/Target/AArch64/SVEInstrFormats.td
337

I think it should be fine without, from the use of SDTCVecEltisVT in other backends (and, you know, we only create AArch64ISD::PFALSE for vectors anyway..)

This revision is now accepted and ready to land.Jan 25 2022, 2:00 PM
Matt added a subscriber: Matt.Jan 25 2022, 3:22 PM
This revision was landed with ongoing or failed builds.Jan 27 2022, 2:30 AM
This revision was automatically updated to reflect the committed changes.