[AArch64][SVE] Implement PFALSE with explicit AArch64ISD node.

[sdesmalen]

Summary

The ISel patterns for PFALSE helps recognise the instructions as being
free of side-effects, which helps MachineCSE remove redundant
PFALSE instructions.

[efriedma]

It looks like AArch64TargetLowering::LowerSPLAT_VECTOR is using DAG.getMachineNode in an inappropriate way: generally, in SelectionDAG, we shouldn't be creating Machine nodes before isel (AArch64DAGToDAGISel::Select). The "proper" construct is to define AArch64ISD::PFALSE, then add a pattern to lower it during isel.

The reason I bring this up is that hasSideEffects is usually inferred from isel patterns.

[sdesmalen]

Implement with AArch64ISD::PFALSE and patterns.

[sdesmalen]

In D118054#3267812, @efriedma wrote:

It looks like AArch64TargetLowering::LowerSPLAT_VECTOR is using DAG.getMachineNode in an inappropriate way: generally, in SelectionDAG, we shouldn't be creating Machine nodes before isel (AArch64DAGToDAGISel::Select). The "proper" construct is to define AArch64ISD::PFALSE, then add a pattern to lower it during isel.

The reason I bring this up is that hasSideEffects is usually inferred from isel patterns.

Ah that makes a lot of sense! I was a bit puzzled as to why it just worked for PTRUE, but not for PFALSE.
I've reimplemented it now by creating an explicit AArch64ISD node for it instead with patterns.

[dmgreen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

2198 ↗

(On Diff #402842)

Add a case here too, so it gets printed nicely in debug output.

llvm/lib/Target/AArch64/SVEInstrFormats.td

337

Does SDTCVecEltisVT imply SDTCisVec?

[sdesmalen]

Added CASE statement for pretty printing of node.

[sdesmalen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

2198 ↗

(On Diff #402842)

Good spot, cheers!

llvm/lib/Target/AArch64/SVEInstrFormats.td

337

Not sure, but when I add a pattern with i1 type, tblgen seems to go into an infinite loop.

[dmgreen]

Thanks. LGTM

llvm/lib/Target/AArch64/SVEInstrFormats.td

337

I think it should be fine without, from the use of SDTCVecEltisVT in other backends (and, you know, we only create AArch64ISD::PFALSE for vectors anyway..)

llvm/lib/Target/AArch64/SVEInstrFormats.td

multiclass sve_int_ptrue<bits<3> opc, string asm, SDPatternOperator op> {
   def : InstAlias<asm # "\t$Pd",
                   (!cast<Instruction>(NAME # _S) PPR32:$Pd, 0b11111), 1>;
   def : InstAlias<asm # "\t$Pd",
                   (!cast<Instruction>(NAME # _D) PPR64:$Pd, 0b11111), 1>;
 }
 
 def SDT_AArch64PTrue : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
 def AArch64ptrue : SDNode<"AArch64ISD::PTRUE", SDT_AArch64PTrue>;
 
 let Predicates = [HasSVEorStreamingSVE] in {
   defm PTRUE  : sve_int_ptrue<0b000, "ptrue", AArch64ptrue>;
   defm PTRUES : sve_int_ptrue<0b001, "ptrues", null_frag>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE pattern match helpers.
 //===----------------------------------------------------------------------===//
: I<(outs PPR8:$Pd), (ins),
   let Inst{23-22} = opc{5-4};
   let Inst{21-19} = 0b011;
   let Inst{18-16} = opc{3-1};
   let Inst{15-10} = 0b111001;
   let Inst{9}     = opc{0};
   let Inst{8-4}   = 0b00000;
   let Inst{3-0}   = Pd;
 
+  let hasSideEffects = 0;
   let isReMaterializable = 1;
 }
 
 class sve_int_ptest<bits<6> opc, string asm>
 : I<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
   asm, "\t$Pg, $Pn",
   "",
   []>, Sched<[]> {

llvm/test/CodeGen/AArch64/sve-pfalse-machine-cse.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass=machine-cse -mtriple=aarch64 -mattr=+sve -o - %s | FileCheck %s
+---
+name:            pfalse
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $p0
+
+    ; CHECK-LABEL: name: pfalse
+    ; CHECK: liveins: $p0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:ppr = COPY $p0
+    ; CHECK-NEXT: [[PFALSE:%[0-9]+]]:ppr = PFALSE
+    ; CHECK-NEXT: [[UZP1_PPP_B:%[0-9]+]]:ppr = UZP1_PPP_B [[COPY]], [[PFALSE]]
+    ; CHECK-NEXT: [[UZP1_PPP_B1:%[0-9]+]]:ppr = UZP1_PPP_B killed [[UZP1_PPP_B]], [[PFALSE]]
+    ; CHECK-NEXT: $p0 = COPY [[UZP1_PPP_B1]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $p0
+    %0:ppr = COPY $p0
+    %2:ppr = PFALSE
+    %3:ppr = UZP1_PPP_B %0, %2
+    %4:ppr = PFALSE
+    %5:ppr = UZP1_PPP_B killed %3, %4
+    $p0 = COPY %5
+    RET_ReallyLR implicit $p0
+...