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Differential D118035

[test][DAGCombine] Add tests for combining carry diamond. NFC
AbandonedPublic

Authored by chfast on Jan 24 2022, 4:21 AM.

Details

Reviewers
craig.topper
RKSimon
davezarzycki
spatel
lebedev.ri
xbolva00
Summary

Hi, I just wanted to make sure it is fine more test like these for combineCarryDiamond(). I plan to do some refactoring and extend it scope and the tests will help me not to break basics.

Diff Detail

Event Timeline

chfast created this revision.Jan 24 2022, 4:21 AM
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RKSimon added reviewers: craig.topper, RKSimon.Jan 24 2022, 4:25 AM
chfast edited the summary of this revision. (Show Details)Jan 24 2022, 4:28 AM
chfast added a reviewer: davezarzycki.
Harbormaster completed remote builds in B145210: Diff 402476.Jan 24 2022, 9:36 AM
chfast added reviewers: spatel, lebedev.ri.Jan 25 2022, 9:31 AM
chfast added a reviewer: xbolva00.Jan 26 2022, 3:28 AM
chfast abandoned this revision.Jan 26 2022, 3:33 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
36 lines
X86/
225 lines
253 lines

Diff 402476

llvm/test/CodeGen/RISCV/addcarry.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RISCV32 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RISCV32
; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY. ; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY.
; Signed fixed point multiplication eventually expands down to an ADDCARRY. ; Signed fixed point multiplication eventually expands down to an ADDCARRY.
declare i64 @llvm.smul.fix.i64 (i64, i64, i32) declare i64 @llvm.smul.fix.i64 (i64, i64, i32)
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
define i64 @addcarry(i64 %x, i64 %y) nounwind { define i64 @addcarry(i64 %x, i64 %y) nounwind {
; RISCV32-LABEL: addcarry: ; RISCV32-LABEL: addcarry:
; RISCV32: # %bb.0: ; RISCV32: # %bb.0:
; RISCV32-NEXT: mul a4, a0, a3 ; RISCV32-NEXT: mul a4, a0, a3
; RISCV32-NEXT: mulhu a7, a0, a2 ; RISCV32-NEXT: mulhu a7, a0, a2
; RISCV32-NEXT: add a4, a7, a4 ; RISCV32-NEXT: add a4, a7, a4
; RISCV32-NEXT: mul a5, a1, a2 ; RISCV32-NEXT: mul a5, a1, a2
Show All 21 Lines
; RISCV32-NEXT: slli a3, a6, 30 ; RISCV32-NEXT: slli a3, a6, 30
; RISCV32-NEXT: mul a0, a0, a2 ; RISCV32-NEXT: mul a0, a0, a2
; RISCV32-NEXT: srli a0, a0, 2 ; RISCV32-NEXT: srli a0, a0, 2
; RISCV32-NEXT: or a0, a3, a0 ; RISCV32-NEXT: or a0, a3, a0
; RISCV32-NEXT: ret ; RISCV32-NEXT: ret
%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2); %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2);
ret i64 %tmp; ret i64 %tmp;
} }
; negative test for combineCarryDiamond(): ADDCARRY not legal
define { i32, i32, i1 } @addcarry_2x32(i32 %x0, i32 %x1, i32 %y0, i32 %y1) nounwind {
; RISCV32-LABEL: addcarry_2x32:
; RISCV32: # %bb.0:
; RISCV32-NEXT: add a3, a1, a3
; RISCV32-NEXT: sltu a1, a3, a1
; RISCV32-NEXT: add a4, a2, a4
; RISCV32-NEXT: sltu a2, a4, a2
; RISCV32-NEXT: add a1, a4, a1
; RISCV32-NEXT: sltu a4, a1, a4
; RISCV32-NEXT: or a2, a2, a4
; RISCV32-NEXT: sw a3, 0(a0)
; RISCV32-NEXT: sw a1, 4(a0)
; RISCV32-NEXT: sb a2, 8(a0)
; RISCV32-NEXT: ret
%t0 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x0, i32 %y0)
%s0 = extractvalue { i32, i1 } %t0, 0
%k0 = extractvalue { i32, i1 } %t0, 1
%t1 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x1, i32 %y1)
%s1 = extractvalue { i32, i1 } %t1, 0
%k1 = extractvalue { i32, i1 } %t1, 1
%zk0 = zext i1 %k0 to i32
%t2 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %s1, i32 %zk0)
%s2 = extractvalue { i32, i1 } %t2, 0
%k2 = extractvalue { i32, i1 } %t2, 1
%k = or i1 %k1, %k2
%r0 = insertvalue { i32, i32, i1 } poison, i32 %s0, 0
%r1 = insertvalue { i32, i32, i1 } %r0, i32 %s2, 1
%r = insertvalue { i32, i32, i1 } %r1, i1 %k, 2
ret { i32, i32, i1 } %r
}

llvm/test/CodeGen/X86/addcarry.ll

Show First 20 Lines • Show All 409 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%sum1 = add i128 %a128, 1 %sum1 = add i128 %a128, 1
%sub1 = add i128 %sum1, %notb128 %sub1 = add i128 %sum1, %notb128
%hi = lshr i128 %sub1, 64 %hi = lshr i128 %sub1, 64
%sum2 = add i128 %hi, %a128 %sum2 = add i128 %hi, %a128
%sub2 = add i128 %sum2, %notb128 %sub2 = add i128 %sum2, %notb128
ret i128 %sub2 ret i128 %sub2
} }
; basic test for combineCarryDiamond()
define { i64, i64, i1 } @addcarry_2x64(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: addcarry_2x64:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: adcq %rcx, %rsi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = or i1 %k1, %k2
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; basic test for combineCarryDiamond() with or operands reversed
define { i64, i64, i1 } @addcarry_2x64_or_reversed(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: addcarry_2x64_or_reversed:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: adcq %rcx, %rsi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = or i1 %k2, %k1 ; reverse natural order of operands
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; basic test for combineCarryDiamond() with xor operands reversed
define { i64, i64, i1 } @addcarry_2x64_xor_reversed(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: addcarry_2x64_xor_reversed:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: adcq %rcx, %rsi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = xor i1 %k2, %k1 ; reverse natural order of operands
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; basic test for combineCarryDiamond() with and operands reversed
define { i64, i64, i1 } @addcarry_2x64_and_reversed(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: addcarry_2x64_and_reversed:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: adcq %rcx, %rsi
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = and i1 %k2, %k1 ; reverse natural order of operands
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; basic test for combineCarryDiamond() with add operands reversed
define { i64, i64, i1 } @addcarry_2x64_add_reversed(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: addcarry_2x64_add_reversed:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: adcq %rcx, %rsi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = add i1 %k2, %k1 ; reverse natural order of operands
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; Here %carryin is considered as valid carry flag for combining into ADDCARRY
; although %carryin does not come from any carry-producing instruction.
define { i64, i1 } @addcarry_fake_carry(i64 %a, i64 %b, i1 %carryin) {
; CHECK-LABEL: addcarry_fake_carry:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: andb $1, %dl
; CHECK-NEXT: addb $-1, %dl
; CHECK-NEXT: adcq %rsi, %rax
; CHECK-NEXT: setb %dl
; CHECK-NEXT: retq
%t1 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%partial = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zcarryin = zext i1 %carryin to i64
%sum = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %partial, i64 %zcarryin)
%k2 = extractvalue { i64, i1 } %sum, 1
%carryout = or i1 %k1, %k2
%ret = insertvalue { i64, i1 } %sum, i1 %carryout, 1
ret { i64, i1 } %ret
}
; negative test: %carryin does not look like carry
define { i64, i1 } @addcarry_carry_not_zext(i64 %a, i64 %b, i64 %carryin) {
; CHECK-LABEL: addcarry_carry_not_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: setb %cl
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: setb %dl
; CHECK-NEXT: orb %cl, %dl
; CHECK-NEXT: retq
%t1 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%partial = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%sum = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %partial, i64 %carryin)
%k2 = extractvalue { i64, i1 } %sum, 1
%carryout = or i1 %k1, %k2
%ret = insertvalue { i64, i1 } %sum, i1 %carryout, 1
ret { i64, i1 } %ret
}
; negative test: %carryin does not look like carry
define { i64, i1 } @addcarry_carry_not_i1(i64 %a, i64 %b, i8 %carryin) {
; CHECK-LABEL: addcarry_carry_not_i1:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movzbl %dl, %eax
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: setb %dl
; CHECK-NEXT: orb %cl, %dl
; CHECK-NEXT: retq
%t1 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%partial = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zcarryin = zext i8 %carryin to i64
%sum = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %partial, i64 %zcarryin)
%k2 = extractvalue { i64, i1 } %sum, 1
%carryout = or i1 %k1, %k2
%ret = insertvalue { i64, i1 } %sum, i1 %carryout, 1
ret { i64, i1 } %ret
}
%struct.U320 = type { [5 x i64] } %struct.U320 = type { [5 x i64] }
define i32 @add_U320_without_i128_add(%struct.U320* nocapture dereferenceable(40) %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5) { define i32 @add_U320_without_i128_add(%struct.U320* nocapture dereferenceable(40) %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5) {
; CHECK-LABEL: add_U320_without_i128_add: ; CHECK-LABEL: add_U320_without_i128_add:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pushq %r14 ; CHECK-NEXT: pushq %r14
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
▲ Show 20 Lines • Show All 610 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/subcarry.ll

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%val = extractvalue {i64, i1} %agg, 0 %val = extractvalue {i64, i1} %agg, 0
%ov = extractvalue {i64, i1} %agg, 1 %ov = extractvalue {i64, i1} %agg, 1
store i64 %val, i64* %valout, align 4 store i64 %val, i64* %valout, align 4
%carry = zext i1 %ov to i64 %carry = zext i1 %ov to i64
%res = sub i64 %carry, %z %res = sub i64 %carry, %z
ret i64 %res ret i64 %res
} }
; basic test for combineCarryDiamond()
define { i64, i64, i1 } @subcarry_2x64(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: subcarry_2x64:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: subq %rdx, %rax
; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = or i1 %k1, %k2
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; basic test for combineCarryDiamond() with or operands reversed
define { i64, i64, i1 } @subcarry_2x64_or_reversed(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: subcarry_2x64_or_reversed:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: subq %rdx, %rax
; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = or i1 %k2, %k1 ; reverse natural order of operands
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; basic test for combineCarryDiamond() with xor operands reversed
define { i64, i64, i1 } @subcarry_2x64_xor_reversed(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: subcarry_2x64_xor_reversed:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: subq %rdx, %rax
; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = xor i1 %k2, %k1 ; reverse natural order of operands
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; basic test for combineCarryDiamond() with and operands reversed
define { i64, i64, i1 } @subcarry_2x64_and_reversed(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: subcarry_2x64_and_reversed:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: subq %rdx, %rax
; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = and i1 %k2, %k1 ; reverse natural order of operands
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; basic test for combineCarryDiamond() with add operands reversed
define { i64, i64, i1 } @subcarry_2x64_add_reversed(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: subcarry_2x64_add_reversed:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: subq %rdx, %rax
; CHECK-NEXT: setb %dil
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: subq %rcx, %rdx
; CHECK-NEXT: subq %rdi, %rdx
; CHECK-NEXT: setb %dil
; CHECK-NEXT: cmpq %rcx, %rsi
; CHECK-NEXT: adcb $0, %dil
; CHECK-NEXT: movl %edi, %ecx
; CHECK-NEXT: retq
%t0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x0, i64 %y0)
%s0 = extractvalue { i64, i1 } %t0, 0
%k0 = extractvalue { i64, i1 } %t0, 1
%t1 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %x1, i64 %y1)
%s1 = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zk0 = zext i1 %k0 to i64
%t2 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %s1, i64 %zk0)
%s2 = extractvalue { i64, i1 } %t2, 0
%k2 = extractvalue { i64, i1 } %t2, 1
%k = add i1 %k2, %k1 ; reverse natural order of operands
%r0 = insertvalue { i64, i64, i1 } poison, i64 %s0, 0
%r1 = insertvalue { i64, i64, i1 } %r0, i64 %s2, 1
%r = insertvalue { i64, i64, i1 } %r1, i1 %k, 2
ret { i64, i64, i1 } %r
}
; Here %carryin is considered as valid carry flag for combining into ADDCARRY
; although %carryin does not come from any carry-producing instruction.
define { i64, i1 } @subcarry_fake_carry(i64 %a, i64 %b, i1 %carryin) {
; CHECK-LABEL: subcarry_fake_carry:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: andb $1, %dl
; CHECK-NEXT: addb $-1, %dl
; CHECK-NEXT: sbbq %rsi, %rax
; CHECK-NEXT: setb %dl
; CHECK-NEXT: retq
%t1 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%partial = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zcarryin = zext i1 %carryin to i64
%s = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %partial, i64 %zcarryin)
%k2 = extractvalue { i64, i1 } %s, 1
%carryout = or i1 %k1, %k2
%ret = insertvalue { i64, i1 } %s, i1 %carryout, 1
ret { i64, i1 } %ret
}
; negative test: %carryin does not look like carry
define { i64, i1 } @subcarry_carry_not_zext(i64 %a, i64 %b, i64 %carryin) {
; CHECK-LABEL: subcarry_carry_not_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: subq %rsi, %rax
; CHECK-NEXT: setb %cl
; CHECK-NEXT: subq %rdx, %rax
; CHECK-NEXT: setb %dl
; CHECK-NEXT: orb %cl, %dl
; CHECK-NEXT: retq
%t1 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%partial = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%s = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %partial, i64 %carryin)
%k2 = extractvalue { i64, i1 } %s, 1
%carryout = or i1 %k1, %k2
%ret = insertvalue { i64, i1 } %s, i1 %carryout, 1
ret { i64, i1 } %ret
}
; negative test: %carryin does not look like carry
define { i64, i1 } @subcarry_carry_not_i1(i64 %a, i64 %b, i8 %carryin) {
; CHECK-LABEL: subcarry_carry_not_i1:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: subq %rsi, %rax
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movzbl %dl, %edx
; CHECK-NEXT: subq %rdx, %rax
; CHECK-NEXT: setb %dl
; CHECK-NEXT: orb %cl, %dl
; CHECK-NEXT: retq
%t1 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%partial = extractvalue { i64, i1 } %t1, 0
%k1 = extractvalue { i64, i1 } %t1, 1
%zcarryin = zext i8 %carryin to i64
%s = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %partial, i64 %zcarryin)
%k2 = extractvalue { i64, i1 } %s, 1
%carryout = or i1 %k1, %k2
%ret = insertvalue { i64, i1 } %s, i1 %carryout, 1
ret { i64, i1 } %ret
}
%struct.U320 = type { [5 x i64] } %struct.U320 = type { [5 x i64] }
define i32 @sub_U320_without_i128_or(%struct.U320* nocapture dereferenceable(40) %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5) { define i32 @sub_U320_without_i128_or(%struct.U320* nocapture dereferenceable(40) %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5) {
; CHECK-LABEL: sub_U320_without_i128_or: ; CHECK-LABEL: sub_U320_without_i128_or:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq %rsi, (%rdi) ; CHECK-NEXT: subq %rsi, (%rdi)
; CHECK-NEXT: sbbq %rdx, 8(%rdi) ; CHECK-NEXT: sbbq %rdx, 8(%rdi)
; CHECK-NEXT: sbbq %rcx, 16(%rdi) ; CHECK-NEXT: sbbq %rcx, 16(%rdi)
▲ Show 20 Lines • Show All 230 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%39 = getelementptr inbounds %uint256, %uint256* %0, i64 0, i32 0, i32 1 %39 = getelementptr inbounds %uint256, %uint256* %0, i64 0, i32 0, i32 1
store i64 %17, i64* %39, align 8 store i64 %17, i64* %39, align 8
%40 = getelementptr inbounds %uint256, %uint256* %0, i64 0, i32 1, i32 0 %40 = getelementptr inbounds %uint256, %uint256* %0, i64 0, i32 1, i32 0
store i64 %34, i64* %40, align 8 store i64 %34, i64* %40, align 8
%41 = getelementptr inbounds %uint256, %uint256* %0, i64 0, i32 1, i32 1 %41 = getelementptr inbounds %uint256, %uint256* %0, i64 0, i32 1, i32 1
store i64 %37, i64* %41, align 8 store i64 %37, i64* %41, align 8
ret void ret void
} }
define i1 @ult_2x64(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
; CHECK-LABEL: ult_2x64:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rdx, %rdi
; CHECK-NEXT: setb %al
; CHECK-NEXT: subq %rcx, %rsi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: cmpq %rax, %rsi
; CHECK-NEXT: setb %al
; CHECK-NEXT: orb %cl, %al
; CHECK-NEXT: retq
%b0 = icmp ult i64 %x0, %y0
%d1 = sub i64 %x1, %y1
%b10 = icmp ult i64 %x1, %y1
%b0z = zext i1 %b0 to i64
%b11 = icmp ult i64 %d1, %b0z
%b1 = or i1 %b10, %b11
ret i1 %b1
}