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Differential D118012

[DAGCombiner][RISCV] Canonicalize (bswap(bitreverse(x))->bitreverse(bswap(x)).
ClosedPublic

Authored by craig.topper on Jan 23 2022, 7:25 PM.

Details

Reviewers
spatel
RKSimon
efriedma
Commits
rGa43ed49f5b16: [DAGCombiner][RISCV] Canonicalize (bswap(bitreverse(x))->bitreverse(bswap(x)).
Summary

If the bitreverse gets expanded, it will introduce a new bswap. By
putting a bswap before the bitreverse, we can ensure it gets cancelled
out when this happens.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 23 2022, 7:25 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 26 others. · View Herald TranscriptJan 23 2022, 7:25 PM
craig.topper requested review of this revision.Jan 23 2022, 7:25 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 23 2022, 7:25 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper added a parent revision: D118007: [SelectionDAG][RISCV] Teach getNode to fold bswap(bswap(x))->x..Jan 23 2022, 7:25 PM
Harbormaster completed remote builds in B145149: Diff 402384.Jan 23 2022, 7:26 PM
craig.topper updated this revision to Diff 402386.Jan 23 2022, 7:33 PM

Upload whole patch

Herald added subscribers: ecnelises, hiraditya. · View Herald TranscriptJan 23 2022, 7:33 PM
Harbormaster completed remote builds in B145151: Diff 402386.Jan 23 2022, 9:54 PM
RKSimon accepted this revision.Jan 24 2022, 2:13 AM

LGTM - cheers

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
9380

Maybe mention its because expandBITREVERSE tries to perform a bswap first?

This revision is now accepted and ready to land.Jan 24 2022, 2:13 AM
Closed by commit rGa43ed49f5b16: [DAGCombiner][RISCV] Canonicalize (bswap(bitreverse(x))->bitreverse(bswap(x)). (authored by craig.topper). · Explain WhyJan 24 2022, 8:32 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGa43ed49f5b16: [DAGCombiner][RISCV] Canonicalize (bswap(bitreverse(x))->bitreverse(bswap(x))..

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
9 lines
test/
CodeGen/
RISCV/
384 lines
150 lines
130 lines

Diff 402386

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===// //===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 9,361 Lines • ▼ Show 20 LinesSDValue DAGCombiner::visitBSWAP(SDNode *N) {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
// fold (bswap c1) -> c2 // fold (bswap c1) -> c2
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N0); return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N0);
// fold (bswap (bswap x)) -> x // fold (bswap (bswap x)) -> x
if (N0.getOpcode() == ISD::BSWAP) if (N0.getOpcode() == ISD::BSWAP)
return N0->getOperand(0); return N0->getOperand(0);
// Canonicalize bswap(bitreverse(x)) -> bitreverse(bswap(x)). This helps
// when bitreverse gets expanded.
RKSimonUnsubmitted
Not Done
ReplyInline Actions

Maybe mention its because expandBITREVERSE tries to perform a bswap first?

RKSimon: Maybe mention its because expandBITREVERSE tries to perform a bswap first?
if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) {
SDLoc DL(N);
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0));
return DAG.getNode(ISD::BITREVERSE, DL, VT, BSwap);
}
return SDValue(); return SDValue();
} }
SDValue DAGCombiner::visitBITREVERSE(SDNode *N) { SDValue DAGCombiner::visitBITREVERSE(SDNode *N) {
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
// fold (bitreverse c1) -> c2 // fold (bitreverse c1) -> c2
▲ Show 20 Lines • Show All 14,697 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/bswap-bitreverse-ctlz-cttz-ctpop.ll

Show First 20 Lines • Show All 1,033 Lines • ▼ Show 20 Lines; RV64ZBB-NEXT: ret
%tmp = call i64 @llvm.bswap.i64(i64 %a) %tmp = call i64 @llvm.bswap.i64(i64 %a)
%tmp2 = call i64 @llvm.bitreverse.i64(i64 %tmp) %tmp2 = call i64 @llvm.bitreverse.i64(i64 %tmp)
ret i64 %tmp2 ret i64 %tmp2
} }
define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind { define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bitreverse_bswap_i16: ; RV32I-LABEL: test_bitreverse_bswap_i16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 8
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: lui a2, 1 ; RV32I-NEXT: lui a2, 1
; RV32I-NEXT: addi a2, a2, -241 ; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: lui a2, 3 ; RV32I-NEXT: lui a2, 3
; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 5 ; RV32I-NEXT: lui a2, 5
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_bitreverse_bswap_i16: ; RV64I-LABEL: test_bitreverse_bswap_i16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 8
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 1 ; RV64I-NEXT: lui a2, 1
; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a0, a0, 4 ; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: lui a2, 3 ; RV64I-NEXT: lui a2, 3
; RV64I-NEXT: addiw a2, a2, 819 ; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 5 ; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: slli a0, a0, 8
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32ZBB-LABEL: test_bitreverse_bswap_i16: ; RV32ZBB-LABEL: test_bitreverse_bswap_i16:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a0, a0 ; RV32ZBB-NEXT: srli a1, a0, 4
; RV32ZBB-NEXT: srli a1, a0, 12 ; RV32ZBB-NEXT: lui a2, 1
; RV32ZBB-NEXT: lui a2, 15 ; RV32ZBB-NEXT: addi a2, a2, -241
; RV32ZBB-NEXT: addi a2, a2, 240
; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: srli a0, a0, 20 ; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: andi a0, a0, -241 ; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a0, a0, a1 ; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 2 ; RV32ZBB-NEXT: srli a1, a0, 2
; RV32ZBB-NEXT: lui a2, 3 ; RV32ZBB-NEXT: lui a2, 3
; RV32ZBB-NEXT: addi a2, a2, 819 ; RV32ZBB-NEXT: addi a2, a2, 819
; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: slli a0, a0, 2 ; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a1, a0 ; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: lui a2, 5 ; RV32ZBB-NEXT: lui a2, 5
; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: addi a2, a2, 1365
; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: slli a0, a0, 1 ; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: or a0, a1, a0 ; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: srli a0, a0, 16
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV64ZBB-LABEL: test_bitreverse_bswap_i16: ; RV64ZBB-LABEL: test_bitreverse_bswap_i16:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0 ; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: srli a1, a0, 44 ; RV64ZBB-NEXT: lui a2, 1
; RV64ZBB-NEXT: lui a2, 15 ; RV64ZBB-NEXT: addiw a2, a2, -241
; RV64ZBB-NEXT: addiw a2, a2, 240
; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: srli a0, a0, 52 ; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: andi a0, a0, -241 ; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a0, a1 ; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: lui a2, 3 ; RV64ZBB-NEXT: lui a2, 3
; RV64ZBB-NEXT: addiw a2, a2, 819 ; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: slli a0, a0, 2 ; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0 ; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: lui a2, 5 ; RV64ZBB-NEXT: lui a2, 5
; RV64ZBB-NEXT: addiw a2, a2, 1365 ; RV64ZBB-NEXT: addiw a2, a2, 1365
; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: slli a0, a0, 1 ; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0 ; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: srli a0, a0, 48
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%tmp = call i16 @llvm.bitreverse.i16(i16 %a) %tmp = call i16 @llvm.bitreverse.i16(i16 %a)
%tmp2 = call i16 @llvm.bswap.i16(i16 %tmp) %tmp2 = call i16 @llvm.bswap.i16(i16 %tmp)
ret i16 %tmp2 ret i16 %tmp2
} }
define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind { define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bitreverse_bswap_i32: ; RV32I-LABEL: test_bitreverse_bswap_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a3, a0, 8
; RV32I-NEXT: lui a4, 4080
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 24
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_bitreverse_bswap_i32: ; RV64I-LABEL: test_bitreverse_bswap_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: lui a4, 4080
; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a3, 61681 ; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a3, a3, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slliw a0, a0, 4 ; RV64I-NEXT: slliw a0, a0, 4
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: lui a3, 209715 ; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a3, a3, 819 ; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slliw a0, a0, 2 ; RV64I-NEXT: slliw a0, a0, 2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a3, 349525 ; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a3, a3, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slliw a0, a0, 1 ; RV64I-NEXT: slliw a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a2, a0, 24
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32ZBB-LABEL: test_bitreverse_bswap_i32: ; RV32ZBB-LABEL: test_bitreverse_bswap_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: srli a1, a0, 4 ; RV32ZBB-NEXT: srli a1, a0, 4
; RV32ZBB-NEXT: lui a2, 61681 ; RV32ZBB-NEXT: lui a2, 61681
; RV32ZBB-NEXT: addi a2, a2, -241 ; RV32ZBB-NEXT: addi a2, a2, -241
; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: slli a0, a0, 4 ; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a0, a1, a0 ; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 2 ; RV32ZBB-NEXT: srli a1, a0, 2
; RV32ZBB-NEXT: lui a2, 209715 ; RV32ZBB-NEXT: lui a2, 209715
; RV32ZBB-NEXT: addi a2, a2, 819 ; RV32ZBB-NEXT: addi a2, a2, 819
; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: slli a0, a0, 2 ; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a1, a0 ; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: lui a2, 349525 ; RV32ZBB-NEXT: lui a2, 349525
; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: addi a2, a2, 1365
; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: slli a0, a0, 1 ; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: or a0, a1, a0 ; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV64ZBB-LABEL: test_bitreverse_bswap_i32: ; RV64ZBB-LABEL: test_bitreverse_bswap_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0 ; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: srli a1, a0, 36
; RV64ZBB-NEXT: lui a2, 61681 ; RV64ZBB-NEXT: lui a2, 61681
; RV64ZBB-NEXT: addiw a2, a2, -241 ; RV64ZBB-NEXT: addiw a2, a2, -241
; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: srli a0, a0, 28
; RV64ZBB-NEXT: lui a2, 986895
; RV64ZBB-NEXT: addiw a2, a2, 240
; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: sext.w a0, a0 ; RV64ZBB-NEXT: slliw a0, a0, 4
; RV64ZBB-NEXT: or a0, a1, a0 ; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: lui a2, 209715 ; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: addiw a2, a2, 819 ; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: slliw a0, a0, 2 ; RV64ZBB-NEXT: slliw a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0 ; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: lui a2, 349525 ; RV64ZBB-NEXT: lui a2, 349525
; RV64ZBB-NEXT: addiw a2, a2, 1365 ; RV64ZBB-NEXT: addiw a2, a2, 1365
; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: slli a0, a0, 1 ; RV64ZBB-NEXT: slliw a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0 ; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: srli a0, a0, 32
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%tmp = call i32 @llvm.bitreverse.i32(i32 %a) %tmp = call i32 @llvm.bitreverse.i32(i32 %a)
%tmp2 = call i32 @llvm.bswap.i32(i32 %tmp) %tmp2 = call i32 @llvm.bswap.i32(i32 %tmp)
ret i32 %tmp2 ret i32 %tmp2
} }
define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind { define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bitreverse_bswap_i64: ; RV32I-LABEL: test_bitreverse_bswap_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a3, a1, 8 ; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a2, a2, -256 ; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a3, a3, a2 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: or a4, a3, a4
; RV32I-NEXT: slli a5, a1, 8
; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a5
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: lui a5, 61681
; RV32I-NEXT: addi a5, a5, -241
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: lui a7, 349525
; RV32I-NEXT: addi a7, a7, 1365
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a0, 8
; RV32I-NEXT: and a4, a4, a2
; RV32I-NEXT: srli t0, a0, 24
; RV32I-NEXT: or a4, a4, t0
; RV32I-NEXT: slli t0, a0, 8
; RV32I-NEXT: and t0, t0, a3
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, t0
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: srli a4, a0, 4
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a4, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: srli a4, a0, 2 ; RV32I-NEXT: srli a2, a0, 2
; RV32I-NEXT: and a4, a4, a6 ; RV32I-NEXT: lui a4, 209715
; RV32I-NEXT: and a0, a0, a6 ; RV32I-NEXT: addi a4, a4, 819
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a4, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: srli a4, a0, 1 ; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a4, a4, a7 ; RV32I-NEXT: lui a5, 349525
; RV32I-NEXT: and a0, a0, a7 ; RV32I-NEXT: addi a5, a5, 1365
; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a4, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: srli a4, a0, 8 ; RV32I-NEXT: srli a2, a1, 4
; RV32I-NEXT: and a4, a4, a2 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a5, a0, 24 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: or a4, a4, a5 ; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: slli a5, a0, 8 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: srli a2, a1, 2
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: or a0, a0, a5 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: or a0, a0, a4 ; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: srli a4, a1, 8 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: and a2, a4, a2 ; RV32I-NEXT: srli a2, a1, 1
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: or a2, a2, a4 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: slli a4, a1, 8 ; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_bitreverse_bswap_i64: ; RV64I-LABEL: test_bitreverse_bswap_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 24 ; RV64I-NEXT: lui a1, %hi(.LCPI12_0)
; RV64I-NEXT: lui a2, 4080 ; RV64I-NEXT: ld a1, %lo(.LCPI12_0)(a1)
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: srli a3, a0, 8 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: li a4, 255 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a5, a4, 24 ; RV64I-NEXT: lui a1, %hi(.LCPI12_1)
; RV64I-NEXT: and a3, a3, a5 ; RV64I-NEXT: ld a1, %lo(.LCPI12_1)(a1)
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: srli a3, a0, 40
; RV64I-NEXT: lui a6, 16
; RV64I-NEXT: addiw a6, a6, -256
; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: srli a7, a0, 56
; RV64I-NEXT: or a3, a3, a7
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a3, a0, 24
; RV64I-NEXT: slli a7, a4, 40
; RV64I-NEXT: and a3, a3, a7
; RV64I-NEXT: srliw t0, a0, 24
; RV64I-NEXT: slli t0, t0, 32
; RV64I-NEXT: or a3, a3, t0
; RV64I-NEXT: slli t0, a0, 40
; RV64I-NEXT: slli a4, a4, 48
; RV64I-NEXT: and t0, t0, a4
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, t0
; RV64I-NEXT: lui t0, %hi(.LCPI12_0)
; RV64I-NEXT: ld t0, %lo(.LCPI12_0)(t0)
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a1, a1, t0
; RV64I-NEXT: and a0, a0, t0
; RV64I-NEXT: lui a3, %hi(.LCPI12_1)
; RV64I-NEXT: ld a3, %lo(.LCPI12_1)(a3)
; RV64I-NEXT: slli a0, a0, 4 ; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a3, %hi(.LCPI12_2) ; RV64I-NEXT: lui a1, %hi(.LCPI12_2)
; RV64I-NEXT: ld a3, %lo(.LCPI12_2)(a3) ; RV64I-NEXT: ld a1, %lo(.LCPI12_2)(a1)
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: and a1, a1, a6
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: and a3, a3, a5
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: slli a2, a0, 24
; RV64I-NEXT: and a2, a2, a7
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: or a2, a2, a3
; RV64I-NEXT: slli a3, a0, 40
; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32ZBB-LABEL: test_bitreverse_bswap_i64: ; RV32ZBB-LABEL: test_bitreverse_bswap_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a1, a1 ; RV32ZBB-NEXT: srli a2, a0, 4
; RV32ZBB-NEXT: srli a2, a1, 4
; RV32ZBB-NEXT: lui a3, 61681 ; RV32ZBB-NEXT: lui a3, 61681
; RV32ZBB-NEXT: addi a3, a3, -241 ; RV32ZBB-NEXT: addi a3, a3, -241
; RV32ZBB-NEXT: and a2, a2, a3 ; RV32ZBB-NEXT: and a2, a2, a3
; RV32ZBB-NEXT: and a1, a1, a3
; RV32ZBB-NEXT: slli a1, a1, 4
; RV32ZBB-NEXT: or a1, a2, a1
; RV32ZBB-NEXT: srli a2, a1, 2
; RV32ZBB-NEXT: lui a4, 209715
; RV32ZBB-NEXT: addi a4, a4, 819
; RV32ZBB-NEXT: and a2, a2, a4
; RV32ZBB-NEXT: and a1, a1, a4
; RV32ZBB-NEXT: slli a1, a1, 2
; RV32ZBB-NEXT: or a1, a2, a1
; RV32ZBB-NEXT: srli a2, a1, 1
; RV32ZBB-NEXT: lui a5, 349525
; RV32ZBB-NEXT: addi a5, a5, 1365
; RV32ZBB-NEXT: and a2, a2, a5
; RV32ZBB-NEXT: and a1, a1, a5
; RV32ZBB-NEXT: slli a1, a1, 1
; RV32ZBB-NEXT: or a1, a2, a1
; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: srli a2, a0, 4
; RV32ZBB-NEXT: and a2, a2, a3
; RV32ZBB-NEXT: and a0, a0, a3 ; RV32ZBB-NEXT: and a0, a0, a3
; RV32ZBB-NEXT: slli a0, a0, 4 ; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a0, a2, a0 ; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: srli a2, a0, 2 ; RV32ZBB-NEXT: srli a2, a0, 2
; RV32ZBB-NEXT: lui a4, 209715
; RV32ZBB-NEXT: addi a4, a4, 819
; RV32ZBB-NEXT: and a2, a2, a4 ; RV32ZBB-NEXT: and a2, a2, a4
; RV32ZBB-NEXT: and a0, a0, a4 ; RV32ZBB-NEXT: and a0, a0, a4
; RV32ZBB-NEXT: slli a0, a0, 2 ; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a2, a0 ; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: srli a2, a0, 1 ; RV32ZBB-NEXT: srli a2, a0, 1
; RV32ZBB-NEXT: lui a5, 349525
; RV32ZBB-NEXT: addi a5, a5, 1365
; RV32ZBB-NEXT: and a2, a2, a5 ; RV32ZBB-NEXT: and a2, a2, a5
; RV32ZBB-NEXT: and a0, a0, a5 ; RV32ZBB-NEXT: and a0, a0, a5
; RV32ZBB-NEXT: slli a0, a0, 1 ; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: or a0, a2, a0 ; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: rev8 a0, a0 ; RV32ZBB-NEXT: srli a2, a1, 4
; RV32ZBB-NEXT: rev8 a1, a1 ; RV32ZBB-NEXT: and a2, a2, a3
; RV32ZBB-NEXT: and a1, a1, a3
; RV32ZBB-NEXT: slli a1, a1, 4
; RV32ZBB-NEXT: or a1, a2, a1
; RV32ZBB-NEXT: srli a2, a1, 2
; RV32ZBB-NEXT: and a2, a2, a4
; RV32ZBB-NEXT: and a1, a1, a4
; RV32ZBB-NEXT: slli a1, a1, 2
; RV32ZBB-NEXT: or a1, a2, a1
; RV32ZBB-NEXT: srli a2, a1, 1
; RV32ZBB-NEXT: and a2, a2, a5
; RV32ZBB-NEXT: and a1, a1, a5
; RV32ZBB-NEXT: slli a1, a1, 1
; RV32ZBB-NEXT: or a1, a2, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV64ZBB-LABEL: test_bitreverse_bswap_i64: ; RV64ZBB-LABEL: test_bitreverse_bswap_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lui a1, %hi(.LCPI12_0) ; RV64ZBB-NEXT: lui a1, %hi(.LCPI12_0)
; RV64ZBB-NEXT: ld a1, %lo(.LCPI12_0)(a1) ; RV64ZBB-NEXT: ld a1, %lo(.LCPI12_0)(a1)
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: srli a2, a0, 4 ; RV64ZBB-NEXT: srli a2, a0, 4
; RV64ZBB-NEXT: and a2, a2, a1 ; RV64ZBB-NEXT: and a2, a2, a1
; RV64ZBB-NEXT: and a0, a0, a1 ; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: lui a1, %hi(.LCPI12_1) ; RV64ZBB-NEXT: lui a1, %hi(.LCPI12_1)
; RV64ZBB-NEXT: ld a1, %lo(.LCPI12_1)(a1) ; RV64ZBB-NEXT: ld a1, %lo(.LCPI12_1)(a1)
; RV64ZBB-NEXT: slli a0, a0, 4 ; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a2, a0 ; RV64ZBB-NEXT: or a0, a2, a0
; RV64ZBB-NEXT: srli a2, a0, 2 ; RV64ZBB-NEXT: srli a2, a0, 2
; RV64ZBB-NEXT: and a2, a2, a1 ; RV64ZBB-NEXT: and a2, a2, a1
; RV64ZBB-NEXT: and a0, a0, a1 ; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: lui a1, %hi(.LCPI12_2) ; RV64ZBB-NEXT: lui a1, %hi(.LCPI12_2)
; RV64ZBB-NEXT: ld a1, %lo(.LCPI12_2)(a1) ; RV64ZBB-NEXT: ld a1, %lo(.LCPI12_2)(a1)
; RV64ZBB-NEXT: slli a0, a0, 2 ; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a2, a0 ; RV64ZBB-NEXT: or a0, a2, a0
; RV64ZBB-NEXT: srli a2, a0, 1 ; RV64ZBB-NEXT: srli a2, a0, 1
; RV64ZBB-NEXT: and a2, a2, a1 ; RV64ZBB-NEXT: and a2, a2, a1
; RV64ZBB-NEXT: and a0, a0, a1 ; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: slli a0, a0, 1 ; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: or a0, a2, a0 ; RV64ZBB-NEXT: or a0, a2, a0
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%tmp = call i64 @llvm.bitreverse.i64(i64 %a) %tmp = call i64 @llvm.bitreverse.i64(i64 %a)
%tmp2 = call i64 @llvm.bswap.i64(i64 %tmp) %tmp2 = call i64 @llvm.bswap.i64(i64 %tmp)
ret i64 %tmp2 ret i64 %tmp2
} }
define i8 @test_cttz_i8(i8 %a) nounwind { define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-LABEL: test_cttz_i8: ; RV32I-LABEL: test_cttz_i8:
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llvm/test/CodeGen/RISCV/rv32zbp.ll

Show First 20 Lines • Show All 2,398 Lines • ▼ Show 20 Lines; RV32ZBP-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a) %1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16) %2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16)
ret i32 %2 ret i32 %2
} }
define i32 @bitreverse_bswap_i32(i32 %a) { define i32 @bitreverse_bswap_i32(i32 %a) {
; RV32I-LABEL: bitreverse_bswap_i32: ; RV32I-LABEL: bitreverse_bswap_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a3, a0, 8
; RV32I-NEXT: lui a4, 4080
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 24
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: bitreverse_bswap_i32: ; RV32ZBP-LABEL: bitreverse_bswap_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0 ; RV32ZBP-NEXT: rev.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = call i32 @llvm.bitreverse.i32(i32 %a) %1 = call i32 @llvm.bitreverse.i32(i32 %a)
%2 = call i32 @llvm.bswap.i32(i32 %1) %2 = call i32 @llvm.bswap.i32(i32 %1)
ret i32 %2 ret i32 %2
} }
define i64 @bitreverse_bswap_i64(i64 %a) { define i64 @bitreverse_bswap_i64(i64 %a) {
; RV32I-LABEL: bitreverse_bswap_i64: ; RV32I-LABEL: bitreverse_bswap_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a3, a1, 8 ; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a2, a2, -256 ; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a3, a3, a2 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: or a4, a3, a4
; RV32I-NEXT: slli a5, a1, 8
; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a5
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: lui a5, 61681
; RV32I-NEXT: addi a5, a5, -241
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: lui a7, 349525
; RV32I-NEXT: addi a7, a7, 1365
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a0, 8
; RV32I-NEXT: and a4, a4, a2
; RV32I-NEXT: srli t0, a0, 24
; RV32I-NEXT: or a4, a4, t0
; RV32I-NEXT: slli t0, a0, 8
; RV32I-NEXT: and t0, t0, a3
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, t0
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: srli a4, a0, 4
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a4, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: srli a4, a0, 2 ; RV32I-NEXT: srli a2, a0, 2
; RV32I-NEXT: and a4, a4, a6 ; RV32I-NEXT: lui a4, 209715
; RV32I-NEXT: and a0, a0, a6 ; RV32I-NEXT: addi a4, a4, 819
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a4, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: srli a4, a0, 1 ; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a4, a4, a7 ; RV32I-NEXT: lui a5, 349525
; RV32I-NEXT: and a0, a0, a7 ; RV32I-NEXT: addi a5, a5, 1365
; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a4, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: srli a4, a0, 8 ; RV32I-NEXT: srli a2, a1, 4
; RV32I-NEXT: and a4, a4, a2 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a5, a0, 24 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: or a4, a4, a5 ; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: slli a5, a0, 8 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: srli a2, a1, 2
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: or a0, a0, a5 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: or a0, a0, a4 ; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: srli a4, a1, 8 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: and a2, a4, a2 ; RV32I-NEXT: srli a2, a1, 1
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: or a2, a2, a4 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: slli a4, a1, 8 ; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: bitreverse_bswap_i64: ; RV32ZBP-LABEL: bitreverse_bswap_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0 ; RV32ZBP-NEXT: rev.b a0, a0
; RV32ZBP-NEXT: rev.b a1, a1 ; RV32ZBP-NEXT: rev.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a) %1 = call i64 @llvm.bitreverse.i64(i64 %a)
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llvm/test/CodeGen/RISCV/rv64zbp.ll

Show First 20 Lines • Show All 2,345 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a) %1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16) %2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16)
ret i32 %2 ret i32 %2
} }
define i32 @bitreverse_bswap_i32(i32 %a) { define i32 @bitreverse_bswap_i32(i32 %a) {
; RV64I-LABEL: bitreverse_bswap_i32: ; RV64I-LABEL: bitreverse_bswap_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: lui a4, 4080
; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a3, 61681 ; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a3, a3, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slliw a0, a0, 4 ; RV64I-NEXT: slliw a0, a0, 4
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: lui a3, 209715 ; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a3, a3, 819 ; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slliw a0, a0, 2 ; RV64I-NEXT: slliw a0, a0, 2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a3, 349525 ; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a3, a3, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slliw a0, a0, 1 ; RV64I-NEXT: slliw a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a2, a0, 24
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: bitreverse_bswap_i32: ; RV64ZBP-LABEL: bitreverse_bswap_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 7 ; RV64ZBP-NEXT: greviw a0, a0, 7
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = call i32 @llvm.bitreverse.i32(i32 %a) %1 = call i32 @llvm.bitreverse.i32(i32 %a)
%2 = call i32 @llvm.bswap.i32(i32 %1) %2 = call i32 @llvm.bswap.i32(i32 %1)
ret i32 %2 ret i32 %2
} }
define i64 @bitreverse_bswap_i64(i64 %a) { define i64 @bitreverse_bswap_i64(i64 %a) {
; RV64I-LABEL: bitreverse_bswap_i64: ; RV64I-LABEL: bitreverse_bswap_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 24 ; RV64I-NEXT: lui a1, %hi(.LCPI68_0)
; RV64I-NEXT: lui a2, 4080 ; RV64I-NEXT: ld a1, %lo(.LCPI68_0)(a1)
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: srli a3, a0, 8 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: li a4, 255 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a5, a4, 24 ; RV64I-NEXT: lui a1, %hi(.LCPI68_1)
; RV64I-NEXT: and a3, a3, a5 ; RV64I-NEXT: ld a1, %lo(.LCPI68_1)(a1)
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: srli a3, a0, 40
; RV64I-NEXT: lui a6, 16
; RV64I-NEXT: addiw a6, a6, -256
; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: srli a7, a0, 56
; RV64I-NEXT: or a3, a3, a7
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a3, a0, 24
; RV64I-NEXT: slli a7, a4, 40
; RV64I-NEXT: and a3, a3, a7
; RV64I-NEXT: srliw t0, a0, 24
; RV64I-NEXT: slli t0, t0, 32
; RV64I-NEXT: or a3, a3, t0
; RV64I-NEXT: slli t0, a0, 40
; RV64I-NEXT: slli a4, a4, 48
; RV64I-NEXT: and t0, t0, a4
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, t0
; RV64I-NEXT: lui t0, %hi(.LCPI68_0)
; RV64I-NEXT: ld t0, %lo(.LCPI68_0)(t0)
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a1, a1, t0
; RV64I-NEXT: and a0, a0, t0
; RV64I-NEXT: lui a3, %hi(.LCPI68_1)
; RV64I-NEXT: ld a3, %lo(.LCPI68_1)(a3)
; RV64I-NEXT: slli a0, a0, 4 ; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a3, %hi(.LCPI68_2) ; RV64I-NEXT: lui a1, %hi(.LCPI68_2)
; RV64I-NEXT: ld a3, %lo(.LCPI68_2)(a3) ; RV64I-NEXT: ld a1, %lo(.LCPI68_2)(a1)
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: and a1, a1, a6
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: and a3, a3, a5
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: slli a2, a0, 24
; RV64I-NEXT: and a2, a2, a7
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: or a2, a2, a3
; RV64I-NEXT: slli a3, a0, 40
; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: bitreverse_bswap_i64: ; RV64ZBP-LABEL: bitreverse_bswap_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.b a0, a0 ; RV64ZBP-NEXT: rev.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a) %1 = call i64 @llvm.bitreverse.i64(i64 %a)
%2 = call i64 @llvm.bswap.i64(i64 %1) %2 = call i64 @llvm.bswap.i64(i64 %1)
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