[RISCV] Support Sinval extension and hypervisor memory management fence instructions

[tangxingxin1008]

Summary

According to Privileged spec version-20211203

Add Supervisor Memory-Management Instructions:
    - SINVAL.VMA, SFENCE.W.INVAL, SFENCE.INVAL.IR
Add Hypervisor Memory-Management Instructions:
    - HFENCE.VVMA, HFENCE.GVMA, HINVAL.VVMA, HINVAL.GVMA

Signed-off-by: eric.tang <[e-mail]>

[tangxingxin1008]

rebase

[asb]

Thanks for the patch. I'm not seeing any errors or major issues in this version, but I've suggested a slight cleanup that would reduce duplication across the different instruction definitions.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

683

If you defined a Priv_rr class, you could use that for sfence.vma, sinval.vma, hfence.{v,g}vma and hinval.{v,g}vma.

697

I think these hfence instructions are technically not part of Sinval, but defined in the hypervisor extension. I understand there's a bit of a circular dependency here, so my suggestion would just be to modify the commit title to something like "Support Sinval extension and hypervisor memory management fence instructions"

[tangxingxin1008]

Address asb's comment.

[tangxingxin1008]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

683

done.

697

done.

[asb]

Thanks, LGTM.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

854

Should there be aliases for hfence.vvma?

[tangxingxin1008]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

854

yes, I think so, but I miss it. I rise up a patch[D120878] to discuss this.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 } // isBarrier = 1, isReturn = 1, isTerminator = 1
 
 def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
   let rd = 0;
   let rs1 = 0;
   let rs2 = 0b00101;
 }
 
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 , rd = 0 in {
 def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
                          (ins GPR:$rs1, GPR:$rs2),
-                         "sfence.vma", "$rs1, $rs2">, Sched<[]> {
-  let rd = 0;
+                         "sfence.vma", "$rs1, $rs2">, Sched<[]>;
+def SINVAL_VMA : RVInstR<0b0001011, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "sinval.vma", "$rs1, $rs2">, Sched<[]>;
+
+def SFENCE_W_INVAL : Priv<"sfence.w.inval", 0b0001100>, Sched<[]> {
+  let rs1 = 0;
+  let rs2 = 0;
+}
+
+def SFENCE_INVAL_IR : Priv<"sfence.inval.ir", 0b0001100>, Sched<[]> {
+  let rs1 = 0;
+  let rs2 = 0b00001;
+}
+
+def HFENCE_VVMA : RVInstR<0b0010001, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "hfence.vvma", "$rs1, $rs2">, Sched<[]>;
+
+def HFENCE_GVMA : RVInstR<0b0110001, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "hfence.gvma", "$rs1, $rs2">, Sched<[]>;
+
+def HINVAL_VVMA : RVInstR<0b0010011, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "hinval.vvma", "$rs1, $rs2">, Sched<[]>;
+
+def HINVAL_GVMA : RVInstR<0b0110011, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "hinval.gvma", "$rs1, $rs2">, Sched<[]>;
 }
 
 //===----------------------------------------------------------------------===//
 // Debug instructions
 //===----------------------------------------------------------------------===//
 
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
 def DRET : Priv<"dret", 0b0111101>, Sched<[]> {

 def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 }
 
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
+def : InstAlias<"hfence.gvma",     (HFENCE_GVMA      X0, X0)>;
+def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs, X0)>;
+
 let EmitPriority = 0 in {
 def : InstAlias<"lb $rd, (${rs1})",
                 (LB  GPR:$rd, GPR:$rs1, 0)>;
 def : InstAlias<"lh $rd, (${rs1})",
                 (LH  GPR:$rd, GPR:$rs1, 0)>;
 def : InstAlias<"lw $rd, (${rs1})",
                 (LW  GPR:$rd, GPR:$rs1, 0)>;
 def : InstAlias<"lbu $rd, (${rs1})",

llvm/test/MC/RISCV/priv-invalid.s

 # RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
 
 mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
 
 sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
 
 sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sinval.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+
+sinval.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sfence.w.inval 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sfence.inval.ir 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hfence.gvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hinval.vvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hinval.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hinval.gvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hinval.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction

llvm/test/MC/RISCV/priv-valid.s

 
 # CHECK-INST: sfence.vma zero, zero
 # CHECK: encoding: [0x73,0x00,0x00,0x12]
 sfence.vma zero, zero
 
 # CHECK-INST: sfence.vma a0, a1
 # CHECK: encoding: [0x73,0x00,0xb5,0x12]
 sfence.vma a0, a1
+
+# CHECK-INST: sinval.vma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x16]
+sinval.vma zero, zero
+
+# CHECK-INST: sinval.vma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x16]
+sinval.vma a0, a1
+
+# CHECK-INST: sfence.w.inval
+# CHECK: encoding: [0x73,0x00,0x00,0x18]
+sfence.w.inval
+
+# CHECK-INST: sfence.inval.ir
+# CHECK: encoding: [0x73,0x00,0x10,0x18]
+sfence.inval.ir
+
+# CHECK-INST: hfence.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x22]
+hfence.vvma zero, zero
+
+# CHECK-INST: hfence.vvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x22]
+hfence.vvma a0, a1
+
+# CHECK-INST: hfence.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x62]
+hfence.gvma zero, zero
+
+# CHECK-INST: hfence.gvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x62]
+hfence.gvma a0, a1
+
+# CHECK-INST: hinval.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x26]
+hinval.vvma zero, zero
+
+# CHECK-INST: hinval.vvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x26]
+hinval.vvma a0, a1
+
+# CHECK-INST: hinval.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x66]
+hinval.gvma zero, zero
+
+# CHECK-INST: hinval.gvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x66]
+hinval.gvma a0, a1

llvm/test/MC/RISCV/rvi-aliases-valid.s

 csrrc t0, 0x140, 0x11
 
 # CHECK-S-OBJ-NOALIAS: sfence.vma zero, zero
 # CHECK-S-OBJ: sfence.vma
 sfence.vma
 # CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero
 # CHECK-S-OBJ: sfence.vma a0
 sfence.vma a0
+# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero
+# CHECK-S-OBJ: hfence.gvma
+hfence.gvma
+# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero
+# CHECK-S-OBJ: hfence.gvma a0
+hfence.gvma a0
 
 # The following aliases are accepted as input but the canonical form
 # of the instruction will always be printed.
 # CHECK-S-OBJ-NOALIAS: addi a2, a3, 4
 # CHECK-S-OBJ: addi a2, a3, 4
 add a2, a3, 4
 # CHECK-S-OBJ-NOALIAS: andi a2, a3, 4
 # CHECK-S-OBJ: andi a2, a3, 4