[SVE][CodeGen] Bail out for scalable vectors in AArch64TargetLowering::ReconstructShuffle

[david-arm]

Summary

Previously the code in AArch64TargetLowering::ReconstructShuffle assumed
the input vectors were always fixed-width, however this is not always
the case since you can extract elements from scalable vectors and insert
into fixed-width ones. We were hitting crashes here for two different
cases:

1. When lowering a fixed-length vector extract from a scalable vector

with i1 element types. This happens due to the fact the i1 elements
get promoted to larger integer types for fixed-width vectors and leads
to sequences of INSERT_VECTOR_ELT and EXTRACT_VECTOR_ELT nodes. In this
case AArch64TargetLowering::ReconstructShuffle will still fail to make
a transformation, but at least it no longer crashes.

2. When lowering a sequence of extractelement/insertelement operations

on mixed fixed-width/scalable vectors.

For now, I've just changed AArch64TargetLowering::ReconstructShuffle to
bail out if it finds a scalable vector.

Tests for both instances described above have been added here:

(1) CodeGen/AArch64/sve-extract-fixed-vector.ll
(2) CodeGen/AArch64/sve-fixed-length-reshuffle.ll

[david-arm]

• Split patch into two - first patch bails out of the optimisation, second patch will add support for it with scalable vectors.

[sdesmalen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

8989–8990

You can bail out sooner I think, by adding a || V.getOperand(0).getValueType().isScalableVectorType() here.

[sdesmalen]

LGTM, but I'd prefer if you could move out some of the tests.

llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll

26

Other than the test above, I'd suggest removing this test and the others below from this patch and submitting them as a separate NFC patch (as precursor to D119427).

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
   // First gather all vectors used as an immediate source for this BUILD_VECTOR
   // node.
   SmallVector<ShuffleSourceInfo, 2> Sources;
   for (unsigned i = 0; i < NumElts; ++i) {
     SDValue V = Op.getOperand(i);
     if (V.isUndef())
       continue;
     else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
-             !isa<ConstantSDNode>(V.getOperand(1))) {
+             !isa<ConstantSDNode>(V.getOperand(1)) ||
+             V.getOperand(0).getValueType().isScalableVector()) {
       LLVM_DEBUG(
           dbgs() << "Reshuffle failed: "
                     "a shuffle can only come from building a vector from "
-                    "various elements of other vectors, provided their "
-                    "indices are constant\n");
+                    "various elements of other fixed-width vectors, provided "
+                    "their indices are constant\n");
       return SDValue();
     }
 
     // Add this element source to the list if it's not already there.
     SDValue SourceVec = V.getOperand(0);
     auto Source = find(Sources, SourceVec);
     if (Source == Sources.end())
       Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
   EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
 
   // If the source vector is too wide or too narrow, we may nevertheless be able
   // to construct a compatible shuffle either by concatenating it with UNDEF or
   // extracting a suitable range of elements.
   for (auto &Src : Sources) {
     EVT SrcVT = Src.ShuffleVec.getValueType();
 
-    uint64_t SrcVTSize = SrcVT.getFixedSizeInBits();
-    if (SrcVTSize == VTSize)
+    TypeSize SrcVTSize = SrcVT.getSizeInBits();
+    if (SrcVTSize == TypeSize::Fixed(VTSize))
       continue;
 
     // This stage of the search produces a source with the same element type as
     // the original, but with a total width matching the BUILD_VECTOR output.
     EVT EltVT = SrcVT.getVectorElementType();
     unsigned NumSrcElts = VTSize / EltVT.getFixedSizeInBits();
     EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
 
-    if (SrcVTSize < VTSize) {
+    if (SrcVTSize.getFixedValue() < VTSize) {
       assert(2 * SrcVTSize == VTSize);
       // We can pad out the smaller vector for free, so if it's part of a
       // shuffle...
       Src.ShuffleVec =
           DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
                       DAG.getUNDEF(Src.ShuffleVec.getValueType()));
       continue;
     }
 
-    if (SrcVTSize != 2 * VTSize) {
+    if (SrcVTSize.getFixedValue() != 2 * VTSize) {
       LLVM_DEBUG(
           dbgs() << "Reshuffle failed: result vector too small to extract\n");
       return SDValue();
     }
 
     if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
       LLVM_DEBUG(
           dbgs() << "Reshuffle failed: span too large for a VEXT to cope\n");

llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll

 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8> %vec, i64 16)
   ret <16 x i8> %retval
 }
 
+
+; Predicates
+
+define <2 x i1> @extract_v2i1_nxv2i1(<vscale x 2 x i1> %inmask) {
+; CHECK-LABEL: extract_v2i1_nxv2i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.d, p0/z, #1 // =0x1
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    mov x8, v0.d[1]
+; CHECK-NEXT:    fmov s0, w0
+; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %mask = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %inmask, i64 0)
+  ret <2 x i1> %mask
+}
+
+define <4 x i1> @extract_v4i1_nxv4i1(<vscale x 4 x i1> %inmask) {
+; CHECK-LABEL: extract_v4i1_nxv4i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #1 // =0x1
+; CHECK-NEXT:    mov w8, v1.s[1]
+; CHECK-NEXT:    mov w9, v1.s[2]
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    mov v0.h[1], w8
+; CHECK-NEXT:    mov w8, v1.s[3]
+; CHECK-NEXT:    mov v0.h[2], w9
+; CHECK-NEXT:    mov v0.h[3], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %mask = call <4 x i1> @llvm.experimental.vector.extract.v4i1.nxv4i1(<vscale x 4 x i1> %inmask, i64 0)
+  ret <4 x i1> %mask
+}
+
+define <8 x i1> @extract_v8i1_nxv8i1(<vscale x 8 x i1> %inmask) {
+; CHECK-LABEL: extract_v8i1_nxv8i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #1 // =0x1
+; CHECK-NEXT:    umov w8, v1.h[1]
+; CHECK-NEXT:    umov w9, v1.h[2]
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    mov v0.b[1], w8
+; CHECK-NEXT:    umov w8, v1.h[3]
+; CHECK-NEXT:    mov v0.b[2], w9
+; CHECK-NEXT:    umov w9, v1.h[4]
+; CHECK-NEXT:    mov v0.b[3], w8
+; CHECK-NEXT:    umov w8, v1.h[5]
+; CHECK-NEXT:    mov v0.b[4], w9
+; CHECK-NEXT:    umov w9, v1.h[6]
+; CHECK-NEXT:    mov v0.b[5], w8
+; CHECK-NEXT:    umov w8, v1.h[7]
+; CHECK-NEXT:    mov v0.b[6], w9
+; CHECK-NEXT:    mov v0.b[7], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %mask = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv8i1(<vscale x 8 x i1> %inmask, i64 0)
+  ret <8 x i1> %mask
+}
+
+define <16 x i1> @extract_v16i1_nxv16i1(<vscale x 16 x i1> %inmask) {
+; CHECK-LABEL: extract_v16i1_nxv16i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.b, p0/z, #1 // =0x1
+; CHECK-NEXT:    umov w8, v1.b[1]
+; CHECK-NEXT:    umov w9, v1.b[2]
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    mov v0.b[1], w8
+; CHECK-NEXT:    umov w8, v1.b[3]
+; CHECK-NEXT:    mov v0.b[2], w9
+; CHECK-NEXT:    umov w9, v1.b[4]
+; CHECK-NEXT:    mov v0.b[3], w8
+; CHECK-NEXT:    umov w8, v1.b[5]
+; CHECK-NEXT:    mov v0.b[4], w9
+; CHECK-NEXT:    umov w9, v1.b[6]
+; CHECK-NEXT:    mov v0.b[5], w8
+; CHECK-NEXT:    umov w8, v1.b[7]
+; CHECK-NEXT:    mov v0.b[6], w9
+; CHECK-NEXT:    umov w9, v1.b[8]
+; CHECK-NEXT:    mov v0.b[7], w8
+; CHECK-NEXT:    umov w8, v1.b[9]
+; CHECK-NEXT:    mov v0.b[8], w9
+; CHECK-NEXT:    umov w9, v1.b[10]
+; CHECK-NEXT:    mov v0.b[9], w8
+; CHECK-NEXT:    umov w8, v1.b[11]
+; CHECK-NEXT:    mov v0.b[10], w9
+; CHECK-NEXT:    umov w9, v1.b[12]
+; CHECK-NEXT:    mov v0.b[11], w8
+; CHECK-NEXT:    umov w8, v1.b[13]
+; CHECK-NEXT:    mov v0.b[12], w9
+; CHECK-NEXT:    umov w9, v1.b[14]
+; CHECK-NEXT:    mov v0.b[13], w8
+; CHECK-NEXT:    umov w8, v1.b[15]
+; CHECK-NEXT:    mov v0.b[14], w9
+; CHECK-NEXT:    mov v0.b[15], w8
+; CHECK-NEXT:    ret
+  %mask = call <16 x i1> @llvm.experimental.vector.extract.v16i1.nxv16i1(<vscale x 16 x i1> %inmask, i64 0)
+  ret <16 x i1> %mask
+}
+
+
 ; Fixed length clamping
 
 define <2 x i64> @extract_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 {
 ; CHECK-LABEL: extract_fixed_v2i64_nxv2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-1
 ; CHECK-NEXT:    cntd x8

 declare <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16>, i64)
 declare <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16>, i64)
 
 declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8>, i64)
 declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8>, i64)
 declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8>, i64)
 declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8>, i64)
 
+declare <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1>, i64)
+declare <4 x i1> @llvm.experimental.vector.extract.v4i1.nxv4i1(<vscale x 4 x i1>, i64)
+declare <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv8i1(<vscale x 8 x i1>, i64)
+declare <16 x i1> @llvm.experimental.vector.extract.v16i1.nxv16i1(<vscale x 16 x i1>, i64)
+
 declare <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64>, i64)
 declare <2 x float> @llvm.experimental.vector.extract.v2f32.nxv4f32(<vscale x 4 x float>, i64)
 declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32>, i64)

llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; == Matching first N elements ==
+
+define <2 x i1> @reshuffle_v2i1_nxv2i1(<vscale x 2 x i1> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i1_nxv2i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.d, p0/z, #1 // =0x1
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    mov x8, v0.d[1]
+; CHECK-NEXT:    fmov s0, w0
+; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 2 x i1> %a, i32 0
+  %el1 = extractelement <vscale x 2 x i1> %a, i32 1
+  %v0 = insertelement <2 x i1> undef, i1 %el0, i32 0
+  %v1 = insertelement <2 x i1> %v0, i1 %el1, i32 1
+  ret <2 x i1> %v1
+}
+
+
+define <2 x i1> @reshuffle_v2i1_nxv4i1(<vscale x 4 x i1> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i1_nxv4i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.s, p0/z, #1 // =0x1
+; CHECK-NEXT:    mov w8, v0.s[1]
+; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i1> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i1> %a, i32 1
+  %v0 = insertelement <2 x i1> undef, i1 %el0, i32 0
+  %v1 = insertelement <2 x i1> %v0, i1 %el1, i32 1
+  ret <2 x i1> %v1
+}
+
+
+define <4 x i1> @reshuffle_v4i1_nxv4i1(<vscale x 4 x i1> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i1_nxv4i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.s, p0/z, #1 // =0x1
+; CHECK-NEXT:    mov w8, v1.s[1]
+; CHECK-NEXT:    mov w9, v1.s[2]
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    mov v0.h[1], w8
+; CHECK-NEXT:    mov w8, v1.s[3]
+; CHECK-NEXT:    mov v0.h[2], w9
+; CHECK-NEXT:    mov v0.h[3], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i1> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i1> %a, i32 1
+  %el2 = extractelement <vscale x 4 x i1> %a, i32 2
+  %el3 = extractelement <vscale x 4 x i1> %a, i32 3
+  %v0 = insertelement <4 x i1> undef, i1 %el0, i32 0
+  %v1 = insertelement <4 x i1> %v0, i1 %el1, i32 1
+  %v2 = insertelement <4 x i1> %v1, i1 %el2, i32 2
+  %v3 = insertelement <4 x i1> %v2, i1 %el3, i32 3
+  ret <4 x i1> %v3
+}
+
+
+define <4 x i1> @reshuffle_v4i1_nxv8i1(<vscale x 8 x i1> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i1_nxv8i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #1 // =0x1
+; CHECK-NEXT:    umov w8, v1.h[1]
+; CHECK-NEXT:    umov w9, v1.h[2]
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    mov v0.h[1], w8
+; CHECK-NEXT:    umov w8, v1.h[3]
+; CHECK-NEXT:    mov v0.h[2], w9
+; CHECK-NEXT:    mov v0.h[3], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i1> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i1> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i1> %a, i32 2
+  %el3 = extractelement <vscale x 8 x i1> %a, i32 3
+  %v0 = insertelement <4 x i1> undef, i1 %el0, i32 0
+  %v1 = insertelement <4 x i1> %v0, i1 %el1, i32 1
+  %v2 = insertelement <4 x i1> %v1, i1 %el2, i32 2
+  %v3 = insertelement <4 x i1> %v2, i1 %el3, i32 3
+  ret <4 x i1> %v3
+}
+
+
+define <8 x i1> @reshuffle_v8i1_nxv8i1(<vscale x 8 x i1> %a) #0 {
+; CHECK-LABEL: reshuffle_v8i1_nxv8i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.h, p0/z, #1 // =0x1
+; CHECK-NEXT:    umov w8, v1.h[1]
+; CHECK-NEXT:    umov w9, v1.h[2]
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    mov v0.b[1], w8
+; CHECK-NEXT:    umov w8, v1.h[3]
+; CHECK-NEXT:    mov v0.b[2], w9
+; CHECK-NEXT:    umov w9, v1.h[4]
+; CHECK-NEXT:    mov v0.b[3], w8
+; CHECK-NEXT:    umov w8, v1.h[5]
+; CHECK-NEXT:    mov v0.b[4], w9
+; CHECK-NEXT:    umov w9, v1.h[6]
+; CHECK-NEXT:    mov v0.b[5], w8
+; CHECK-NEXT:    umov w8, v1.h[7]
+; CHECK-NEXT:    mov v0.b[6], w9
+; CHECK-NEXT:    mov v0.b[7], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i1> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i1> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i1> %a, i32 2
+  %el3 = extractelement <vscale x 8 x i1> %a, i32 3
+  %el4 = extractelement <vscale x 8 x i1> %a, i32 4
+  %el5 = extractelement <vscale x 8 x i1> %a, i32 5
+  %el6 = extractelement <vscale x 8 x i1> %a, i32 6
+  %el7 = extractelement <vscale x 8 x i1> %a, i32 7
+  %v0 = insertelement <8 x i1> undef, i1 %el0, i32 0
+  %v1 = insertelement <8 x i1> %v0, i1 %el1, i32 1
+  %v2 = insertelement <8 x i1> %v1, i1 %el2, i32 2
+  %v3 = insertelement <8 x i1> %v2, i1 %el3, i32 3
+  %v4 = insertelement <8 x i1> %v3, i1 %el4, i32 4
+  %v5 = insertelement <8 x i1> %v4, i1 %el5, i32 5
+  %v6 = insertelement <8 x i1> %v5, i1 %el6, i32 6
+  %v7 = insertelement <8 x i1> %v6, i1 %el7, i32 7
+  ret <8 x i1> %v7
+}
+
+
+define <16 x i1> @reshuffle_v16i1_nxv16i1(<vscale x 16 x i1> %a) #0 {
+; CHECK-LABEL: reshuffle_v16i1_nxv16i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.b, p0/z, #1 // =0x1
+; CHECK-NEXT:    umov w8, v1.b[1]
+; CHECK-NEXT:    umov w9, v1.b[2]
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    mov v0.b[1], w8
+; CHECK-NEXT:    umov w8, v1.b[3]
+; CHECK-NEXT:    mov v0.b[2], w9
+; CHECK-NEXT:    umov w9, v1.b[4]
+; CHECK-NEXT:    mov v0.b[3], w8
+; CHECK-NEXT:    umov w8, v1.b[5]
+; CHECK-NEXT:    mov v0.b[4], w9
+; CHECK-NEXT:    umov w9, v1.b[6]
+; CHECK-NEXT:    mov v0.b[5], w8
+; CHECK-NEXT:    umov w8, v1.b[7]
+; CHECK-NEXT:    mov v0.b[6], w9
+; CHECK-NEXT:    umov w9, v1.b[8]
+; CHECK-NEXT:    mov v0.b[7], w8
+; CHECK-NEXT:    umov w8, v1.b[9]
+; CHECK-NEXT:    mov v0.b[8], w9
+; CHECK-NEXT:    umov w9, v1.b[10]
+; CHECK-NEXT:    mov v0.b[9], w8
+; CHECK-NEXT:    umov w8, v1.b[11]
+; CHECK-NEXT:    mov v0.b[10], w9
+; CHECK-NEXT:    umov w9, v1.b[12]
+; CHECK-NEXT:    mov v0.b[11], w8
+; CHECK-NEXT:    umov w8, v1.b[13]
+; CHECK-NEXT:    mov v0.b[12], w9
+; CHECK-NEXT:    umov w9, v1.b[14]
+; CHECK-NEXT:    mov v0.b[13], w8
+; CHECK-NEXT:    umov w8, v1.b[15]
+; CHECK-NEXT:    mov v0.b[14], w9
+; CHECK-NEXT:    mov v0.b[15], w8
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 16 x i1> %a, i32 0
+  %el1 = extractelement <vscale x 16 x i1> %a, i32 1
+  %el2 = extractelement <vscale x 16 x i1> %a, i32 2
+  %el3 = extractelement <vscale x 16 x i1> %a, i32 3
+  %el4 = extractelement <vscale x 16 x i1> %a, i32 4
+  %el5 = extractelement <vscale x 16 x i1> %a, i32 5
+  %el6 = extractelement <vscale x 16 x i1> %a, i32 6
+  %el7 = extractelement <vscale x 16 x i1> %a, i32 7
+  %el8 = extractelement <vscale x 16 x i1> %a, i32 8
+  %el9 = extractelement <vscale x 16 x i1> %a, i32 9
+  %el10 = extractelement <vscale x 16 x i1> %a, i32 10
+  %el11 = extractelement <vscale x 16 x i1> %a, i32 11
+  %el12 = extractelement <vscale x 16 x i1> %a, i32 12
+  %el13 = extractelement <vscale x 16 x i1> %a, i32 13
+  %el14 = extractelement <vscale x 16 x i1> %a, i32 14
+  %el15 = extractelement <vscale x 16 x i1> %a, i32 15
+  %v0 = insertelement <16 x i1> undef, i1 %el0, i32 0
+  %v1 = insertelement <16 x i1> %v0, i1 %el1, i32 1
+  %v2 = insertelement <16 x i1> %v1, i1 %el2, i32 2
+  %v3 = insertelement <16 x i1> %v2, i1 %el3, i32 3
+  %v4 = insertelement <16 x i1> %v3, i1 %el4, i32 4
+  %v5 = insertelement <16 x i1> %v4, i1 %el5, i32 5
+  %v6 = insertelement <16 x i1> %v5, i1 %el6, i32 6
+  %v7 = insertelement <16 x i1> %v6, i1 %el7, i32 7
+  %v8 = insertelement <16 x i1> %v7, i1 %el8, i32 8
+  %v9 = insertelement <16 x i1> %v8, i1 %el9, i32 9
+  %v10 = insertelement <16 x i1> %v9, i1 %el10, i32 10
+  %v11 = insertelement <16 x i1> %v10, i1 %el11, i32 11
+  %v12 = insertelement <16 x i1> %v11, i1 %el12, i32 12
+  %v13 = insertelement <16 x i1> %v12, i1 %el13, i32 13
+  %v14 = insertelement <16 x i1> %v13, i1 %el14, i32 14
+  %v15 = insertelement <16 x i1> %v14, i1 %el15, i32 15
+  ret <16 x i1> %v15
+}
+
+
+define <2 x i64> @reshuffle_v2i64_nxv2i64(<vscale x 2 x i64> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i64_nxv2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 2 x i64> %a, i32 0
+  %el1 = extractelement <vscale x 2 x i64> %a, i32 1
+  %v0 = insertelement <2 x i64> undef, i64 %el0, i32 0
+  %v1 = insertelement <2 x i64> %v0, i64 %el1, i32 1
+  ret <2 x i64> %v1
+}
+
+
+define <2 x i32> @reshuffle_v2i32_nxv2i32(<vscale x 2 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i32_nxv2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 2 x i32> %a, i32 0
+  %el1 = extractelement <vscale x 2 x i32> %a, i32 1
+  %v0 = insertelement <2 x i32> undef, i32 %el0, i32 0
+  %v1 = insertelement <2 x i32> %v0, i32 %el1, i32 1
+  ret <2 x i32> %v1
+}
+
+
+define <2 x i32> @reshuffle_v2i32_nxv4i32(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i32_nxv4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i32> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i32> %a, i32 1
+  %v0 = insertelement <2 x i32> undef, i32 %el0, i32 0
+  %v1 = insertelement <2 x i32> %v0, i32 %el1, i32 1
+  ret <2 x i32> %v1
+}
+
+
+define <4 x i32> @reshuffle_v4i32_nxv4i32(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i32_nxv4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i32> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i32> %a, i32 1
+  %el2 = extractelement <vscale x 4 x i32> %a, i32 2
+  %el3 = extractelement <vscale x 4 x i32> %a, i32 3
+  %v0 = insertelement <4 x i32> undef, i32 %el0, i32 0
+  %v1 = insertelement <4 x i32> %v0, i32 %el1, i32 1
+  %v2 = insertelement <4 x i32> %v1, i32 %el2, i32 2
+  %v3 = insertelement <4 x i32> %v2, i32 %el3, i32 3
+  ret <4 x i32> %v3
+}
+
+
+define <4 x i16> @reshuffle_v4i16_nxv4i16(<vscale x 4 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i16_nxv4i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    xtn v0.4h, v0.4s
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 4 x i16> %a, i32 2
+  %el3 = extractelement <vscale x 4 x i16> %a, i32 3
+  %v0 = insertelement <4 x i16> undef, i16 %el0, i32 0
+  %v1 = insertelement <4 x i16> %v0, i16 %el1, i32 1
+  %v2 = insertelement <4 x i16> %v1, i16 %el2, i32 2
+  %v3 = insertelement <4 x i16> %v2, i16 %el3, i32 3
+  ret <4 x i16> %v3
+}
+
+
+define <4 x i16> @reshuffle_v4i16_nxv8i16(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i16_nxv8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i16> %a, i32 2
+  %el3 = extractelement <vscale x 8 x i16> %a, i32 3
+  %v0 = insertelement <4 x i16> undef, i16 %el0, i32 0
+  %v1 = insertelement <4 x i16> %v0, i16 %el1, i32 1
+  %v2 = insertelement <4 x i16> %v1, i16 %el2, i32 2
+  %v3 = insertelement <4 x i16> %v2, i16 %el3, i32 3
+  ret <4 x i16> %v3
+}
+
+
+define <8 x i16> @reshuffle_v8i16_nxv8i16(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v8i16_nxv8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i16> %a, i32 2
+  %el3 = extractelement <vscale x 8 x i16> %a, i32 3
+  %el4 = extractelement <vscale x 8 x i16> %a, i32 4
+  %el5 = extractelement <vscale x 8 x i16> %a, i32 5
+  %el6 = extractelement <vscale x 8 x i16> %a, i32 6
+  %el7 = extractelement <vscale x 8 x i16> %a, i32 7
+  %v0 = insertelement <8 x i16> undef, i16 %el0, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %el1, i32 1
+  %v2 = insertelement <8 x i16> %v1, i16 %el2, i32 2
+  %v3 = insertelement <8 x i16> %v2, i16 %el3, i32 3
+  %v4 = insertelement <8 x i16> %v3, i16 %el4, i32 4
+  %v5 = insertelement <8 x i16> %v4, i16 %el5, i32 5
+  %v6 = insertelement <8 x i16> %v5, i16 %el6, i32 6
+  %v7 = insertelement <8 x i16> %v6, i16 %el7, i32 7
+  ret <8 x i16> %v7
+}
+
+
+define <16 x i8> @reshuffle_v16i8_nxv16i8(<vscale x 16 x i8> %a) #0 {
+; CHECK-LABEL: reshuffle_v16i8_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 16 x i8> %a, i32 0
+  %el1 = extractelement <vscale x 16 x i8> %a, i32 1
+  %el2 = extractelement <vscale x 16 x i8> %a, i32 2
+  %el3 = extractelement <vscale x 16 x i8> %a, i32 3
+  %el4 = extractelement <vscale x 16 x i8> %a, i32 4
+  %el5 = extractelement <vscale x 16 x i8> %a, i32 5
+  %el6 = extractelement <vscale x 16 x i8> %a, i32 6
+  %el7 = extractelement <vscale x 16 x i8> %a, i32 7
+  %el8 = extractelement <vscale x 16 x i8> %a, i32 8
+  %el9 = extractelement <vscale x 16 x i8> %a, i32 9
+  %el10 = extractelement <vscale x 16 x i8> %a, i32 10
+  %el11 = extractelement <vscale x 16 x i8> %a, i32 11
+  %el12 = extractelement <vscale x 16 x i8> %a, i32 12
+  %el13 = extractelement <vscale x 16 x i8> %a, i32 13
+  %el14 = extractelement <vscale x 16 x i8> %a, i32 14
+  %el15 = extractelement <vscale x 16 x i8> %a, i32 15
+  %v0 = insertelement <16 x i8> undef, i8 %el0, i32 0
+  %v1 = insertelement <16 x i8> %v0, i8 %el1, i32 1
+  %v2 = insertelement <16 x i8> %v1, i8 %el2, i32 2
+  %v3 = insertelement <16 x i8> %v2, i8 %el3, i32 3
+  %v4 = insertelement <16 x i8> %v3, i8 %el4, i32 4
+  %v5 = insertelement <16 x i8> %v4, i8 %el5, i32 5
+  %v6 = insertelement <16 x i8> %v5, i8 %el6, i32 6
+  %v7 = insertelement <16 x i8> %v6, i8 %el7, i32 7
+  %v8 = insertelement <16 x i8> %v7, i8 %el8, i32 8
+  %v9 = insertelement <16 x i8> %v8, i8 %el9, i32 9
+  %v10 = insertelement <16 x i8> %v9, i8 %el10, i32 10
+  %v11 = insertelement <16 x i8> %v10, i8 %el11, i32 11
+  %v12 = insertelement <16 x i8> %v11, i8 %el12, i32 12
+  %v13 = insertelement <16 x i8> %v12, i8 %el13, i32 13
+  %v14 = insertelement <16 x i8> %v13, i8 %el14, i32 14
+  %v15 = insertelement <16 x i8> %v14, i8 %el15, i32 15
+  ret <16 x i8> %v15
+}
+
+
+define <8 x i8> @reshuffle_v8i8_nxv16i8(<vscale x 16 x i8> %a) #0 {
+; CHECK-LABEL: reshuffle_v8i8_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 16 x i8> %a, i32 0
+  %el1 = extractelement <vscale x 16 x i8> %a, i32 1
+  %el2 = extractelement <vscale x 16 x i8> %a, i32 2
+  %el3 = extractelement <vscale x 16 x i8> %a, i32 3
+  %el4 = extractelement <vscale x 16 x i8> %a, i32 4
+  %el5 = extractelement <vscale x 16 x i8> %a, i32 5
+  %el6 = extractelement <vscale x 16 x i8> %a, i32 6
+  %el7 = extractelement <vscale x 16 x i8> %a, i32 7
+  %v0 = insertelement <8 x i8> undef, i8 %el0, i32 0
+  %v1 = insertelement <8 x i8> %v0, i8 %el1, i32 1
+  %v2 = insertelement <8 x i8> %v1, i8 %el2, i32 2
+  %v3 = insertelement <8 x i8> %v2, i8 %el3, i32 3
+  %v4 = insertelement <8 x i8> %v3, i8 %el4, i32 4
+  %v5 = insertelement <8 x i8> %v4, i8 %el5, i32 5
+  %v6 = insertelement <8 x i8> %v5, i8 %el6, i32 6
+  %v7 = insertelement <8 x i8> %v6, i8 %el7, i32 7
+  ret <8 x i8> %v7
+}
+
+
+define <2 x float> @reshuffle_v2f32_nxv2f32(<vscale x 2 x float> %a) #0 {
+; CHECK-LABEL: reshuffle_v2f32_nxv2f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT:    addvl sp, sp, #-1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
+; CHECK-NEXT:    .cfi_offset w29, -16
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    st1w { z0.d }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    addpl x8, sp, #4
+; CHECK-NEXT:    ldr d0, [x8]
+; CHECK-NEXT:    addvl sp, sp, #1
+; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 2 x float> %a, i32 0
+  %el1 = extractelement <vscale x 2 x float> %a, i32 1
+  %v0 = insertelement <2 x float> undef, float %el0, i32 0
+  %v1 = insertelement <2 x float> %v0, float %el1, i32 1
+  ret <2 x float> %v1
+}
+
+
+define <4 x float> @reshuffle_v4f32_nxv4f32(<vscale x 4 x float> %a) #0 {
+; CHECK-LABEL: reshuffle_v4f32_nxv4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x float> %a, i32 0
+  %el1 = extractelement <vscale x 4 x float> %a, i32 1
+  %el2 = extractelement <vscale x 4 x float> %a, i32 2
+  %el3 = extractelement <vscale x 4 x float> %a, i32 3
+  %v0 = insertelement <4 x float> undef, float %el0, i32 0
+  %v1 = insertelement <4 x float> %v0, float %el1, i32 1
+  %v2 = insertelement <4 x float> %v1, float %el2, i32 2
+  %v3 = insertelement <4 x float> %v2, float %el3, i32 3
+  ret <4 x float> %v3
+}
+
+
+; == Reversed first N elements ==
+
+define <4 x i16> @reshuffle_v4i16_nxv4i16_reverse(<vscale x 4 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i16_nxv4i16_reverse:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, v0.s[3]
+; CHECK-NEXT:    mov w9, v0.s[2]
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    mov w8, v0.s[1]
+; CHECK-NEXT:    mov v1.h[1], w9
+; CHECK-NEXT:    mov v1.h[2], w8
+; CHECK-NEXT:    fmov w8, s0
+; CHECK-NEXT:    mov v1.h[3], w8
+; CHECK-NEXT:    fmov d0, d1
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 4 x i16> %a, i32 2
+  %el3 = extractelement <vscale x 4 x i16> %a, i32 3
+  %v0 = insertelement <4 x i16> undef, i16 %el3, i32 0
+  %v1 = insertelement <4 x i16> %v0, i16 %el2, i32 1
+  %v2 = insertelement <4 x i16> %v1, i16 %el1, i32 2
+  %v3 = insertelement <4 x i16> %v2, i16 %el0, i32 3
+  ret <4 x i16> %v3
+}
+
+
+define <8 x i16> @reshuffle_v8i16_nxv8i16_reverse(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v8i16_nxv8i16_reverse:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[7]
+; CHECK-NEXT:    umov w9, v0.h[6]
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    umov w8, v0.h[5]
+; CHECK-NEXT:    mov v1.h[1], w9
+; CHECK-NEXT:    umov w9, v0.h[4]
+; CHECK-NEXT:    mov v1.h[2], w8
+; CHECK-NEXT:    umov w8, v0.h[3]
+; CHECK-NEXT:    mov v1.h[3], w9
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    mov v1.h[4], w8
+; CHECK-NEXT:    umov w8, v0.h[1]
+; CHECK-NEXT:    mov v1.h[5], w9
+; CHECK-NEXT:    mov v1.h[6], w8
+; CHECK-NEXT:    fmov w8, s0
+; CHECK-NEXT:    mov v1.h[7], w8
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i16> %a, i32 2
+  %el3 = extractelement <vscale x 8 x i16> %a, i32 3
+  %el4 = extractelement <vscale x 8 x i16> %a, i32 4
+  %el5 = extractelement <vscale x 8 x i16> %a, i32 5
+  %el6 = extractelement <vscale x 8 x i16> %a, i32 6
+  %el7 = extractelement <vscale x 8 x i16> %a, i32 7
+  %v0 = insertelement <8 x i16> undef, i16 %el7, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %el6, i32 1
+  %v2 = insertelement <8 x i16> %v1, i16 %el5, i32 2
+  %v3 = insertelement <8 x i16> %v2, i16 %el4, i32 3
+  %v4 = insertelement <8 x i16> %v3, i16 %el3, i32 4
+  %v5 = insertelement <8 x i16> %v4, i16 %el2, i32 5
+  %v6 = insertelement <8 x i16> %v5, i16 %el1, i32 6
+  %v7 = insertelement <8 x i16> %v6, i16 %el0, i32 7
+  ret <8 x i16> %v7
+}
+
+
+; == Result requires padding one source with undef elements ==
+
+define <2 x i32> @reshuffle_v2i32_nxv2i32_undef(<vscale x 2 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i32_nxv2i32_undef:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 2 x i32> %a, i32 0
+  %v0 = insertelement <2 x i32> undef, i32 %el0, i32 0
+  ret <2 x i32> %v0
+}
+
+
+define <2 x i32> @reshuffle_v2i32_nxv2i32_undef2(<vscale x 2 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i32_nxv2i32_undef2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, v0.s[2]
+; CHECK-NEXT:    dup v0.2s, w8
+; CHECK-NEXT:    ret
+  %el1 = extractelement <vscale x 2 x i32> %a, i32 1
+  %v0 = insertelement <2 x i32> undef, i32 %el1, i32 1
+  ret <2 x i32> %v0
+}
+
+
+define <2 x i32> @reshuffle_v2i32_nxv4i32_undef(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i32_nxv4i32_undef:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i32> %a, i32 0
+  %v0 = insertelement <2 x i32> undef, i32 %el0, i32 0
+  ret <2 x i32> %v0
+}
+
+
+define <2 x i32> @reshuffle_v2i32_nxv4i32_undef2(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i32_nxv4i32_undef2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, v0.s[1]
+; CHECK-NEXT:    dup v0.2s, w8
+; CHECK-NEXT:    ret
+  %el1 = extractelement <vscale x 4 x i32> %a, i32 1
+  %v0 = insertelement <2 x i32> undef, i32 %el1, i32 1
+  ret <2 x i32> %v0
+}
+
+
+define <4 x i32> @reshuffle_v4i32_nxv4i32_undef(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i32_nxv4i32_undef:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, v0.s[1]
+; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i32> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i32> %a, i32 1
+  %v0 = insertelement <4 x i32> undef, i32 %el0, i32 0
+  %v1 = insertelement <4 x i32> %v0, i32 %el1, i32 1
+  ret <4 x i32> %v1
+}
+
+
+define <4 x i32> @reshuffle_v4i32_nxv4i32_undef2(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i32_nxv4i32_undef2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, v0.s[2]
+; CHECK-NEXT:    mov w9, v0.s[3]
+; CHECK-NEXT:    mov v0.s[2], w8
+; CHECK-NEXT:    mov v0.s[3], w9
+; CHECK-NEXT:    ret
+  %el2 = extractelement <vscale x 4 x i32> %a, i32 2
+  %el3 = extractelement <vscale x 4 x i32> %a, i32 3
+  %v0 = insertelement <4 x i32> undef, i32 %el2, i32 2
+  %v1 = insertelement <4 x i32> %v0, i32 %el3, i32 3
+  ret <4 x i32> %v1
+}
+
+
+define <2 x i16> @reshuffle_v2i16_nxv8i16_undef(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i16_nxv8i16_undef:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %v0 = insertelement <2 x i16> undef, i16 %el0, i32 0
+  ret <2 x i16> %v0
+}
+
+
+define <2 x i16> @reshuffle_v2i16_nxv8i16_undef2(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v2i16_nxv8i16_undef2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[1]
+; CHECK-NEXT:    dup v0.2s, w8
+; CHECK-NEXT:    ret
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %v0 = insertelement <2 x i16> undef, i16 %el1, i32 1
+  ret <2 x i16> %v0
+}
+
+
+define <4 x i16> @reshuffle_v4i16_nxv8i16_undef(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i16_nxv8i16_undef:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[1]
+; CHECK-NEXT:    mov v0.h[1], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %v0 = insertelement <4 x i16> undef, i16 %el0, i32 0
+  %v1 = insertelement <4 x i16> %v0, i16 %el1, i32 1
+  ret <4 x i16> %v1
+}
+
+define <4 x i16> @reshuffle_v4i16_nxv8i16_undef2(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i16_nxv8i16_undef2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[2]
+; CHECK-NEXT:    umov w9, v0.h[3]
+; CHECK-NEXT:    mov v0.h[2], w8
+; CHECK-NEXT:    mov v0.h[3], w9
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %el2 = extractelement <vscale x 8 x i16> %a, i32 2
+  %el3 = extractelement <vscale x 8 x i16> %a, i32 3
+  %v0 = insertelement <4 x i16> undef, i16 %el2, i32 2
+  %v1 = insertelement <4 x i16> %v0, i16 %el3, i32 3
+  ret <4 x i16> %v1
+}
+
+
+define <8 x i16> @reshuffle_v8i16_nxv8i16_undef(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v8i16_nxv8i16_undef:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[1]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    umov w10, v0.h[3]
+; CHECK-NEXT:    mov v0.h[1], w8
+; CHECK-NEXT:    mov v0.h[2], w9
+; CHECK-NEXT:    mov v0.h[3], w10
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i16> %a, i32 2
+  %el3 = extractelement <vscale x 8 x i16> %a, i32 3
+  %v0 = insertelement <8 x i16> undef, i16 %el0, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %el1, i32 1
+  %v2 = insertelement <8 x i16> %v1, i16 %el2, i32 2
+  %v3 = insertelement <8 x i16> %v2, i16 %el3, i32 3
+  ret <8 x i16> %v3
+}
+
+
+define <8 x i16> @reshuffle_v8i16_nxv8i16_undef2(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v8i16_nxv8i16_undef2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[4]
+; CHECK-NEXT:    umov w9, v0.h[5]
+; CHECK-NEXT:    mov v1.h[4], w8
+; CHECK-NEXT:    umov w8, v0.h[6]
+; CHECK-NEXT:    mov v1.h[5], w9
+; CHECK-NEXT:    umov w9, v0.h[7]
+; CHECK-NEXT:    mov v1.h[6], w8
+; CHECK-NEXT:    mov v1.h[7], w9
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %el4 = extractelement <vscale x 8 x i16> %a, i32 4
+  %el5 = extractelement <vscale x 8 x i16> %a, i32 5
+  %el6 = extractelement <vscale x 8 x i16> %a, i32 6
+  %el7 = extractelement <vscale x 8 x i16> %a, i32 7
+  %v0 = insertelement <8 x i16> undef, i16 %el4, i32 4
+  %v1 = insertelement <8 x i16> %v0, i16 %el5, i32 5
+  %v2 = insertelement <8 x i16> %v1, i16 %el6, i32 6
+  %v3 = insertelement <8 x i16> %v2, i16 %el7, i32 7
+  ret <8 x i16> %v3
+}
+
+
+define <4 x i32> @reshuffle_v4i32_nxv4i32_reverse_undef(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i32_nxv4i32_reverse_undef:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, v0.s[1]
+; CHECK-NEXT:    fmov w9, s0
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    mov v0.s[1], w9
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i32> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i32> %a, i32 1
+  %v0 = insertelement <4 x i32> undef, i32 %el1, i32 0
+  %v1 = insertelement <4 x i32> %v0, i32 %el0, i32 1
+  ret <4 x i32> %v1
+}
+
+
+define <4 x i32> @reshuffle_v4i32_nxv4i32_reverse_undef2(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i32_nxv4i32_reverse_undef2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, v0.s[3]
+; CHECK-NEXT:    mov w9, v0.s[2]
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    mov v0.s[1], w9
+; CHECK-NEXT:    ret
+  %el2 = extractelement <vscale x 4 x i32> %a, i32 2
+  %el3 = extractelement <vscale x 4 x i32> %a, i32 3
+  %v0 = insertelement <4 x i32> undef, i32 %el3, i32 0
+  %v1 = insertelement <4 x i32> %v0, i32 %el2, i32 1
+  ret <4 x i32> %v1
+}
+
+
+define <8 x i16> @reshuffle_v8i16_nxv8i16_reverse_undef(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v8i16_nxv8i16_reverse_undef:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[3]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    umov w8, v0.h[1]
+; CHECK-NEXT:    mov v1.h[1], w9
+; CHECK-NEXT:    mov v1.h[2], w8
+; CHECK-NEXT:    fmov w8, s0
+; CHECK-NEXT:    mov v1.h[3], w8
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i16> %a, i32 2
+  %el3 = extractelement <vscale x 8 x i16> %a, i32 3
+  %v0 = insertelement <8 x i16> undef, i16 %el3, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %el2, i32 1
+  %v2 = insertelement <8 x i16> %v1, i16 %el1, i32 2
+  %v3 = insertelement <8 x i16> %v2, i16 %el0, i32 3
+  ret <8 x i16> %v3
+}
+
+
+define <8 x i16> @reshuffle_v8i16_nxv8i16_reverse_undef2(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reshuffle_v8i16_nxv8i16_reverse_undef2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[7]
+; CHECK-NEXT:    umov w9, v0.h[6]
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    umov w8, v0.h[5]
+; CHECK-NEXT:    mov v1.h[1], w9
+; CHECK-NEXT:    umov w9, v0.h[4]
+; CHECK-NEXT:    mov v1.h[2], w8
+; CHECK-NEXT:    mov v1.h[3], w9
+; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %el4 = extractelement <vscale x 8 x i16> %a, i32 4
+  %el5 = extractelement <vscale x 8 x i16> %a, i32 5
+  %el6 = extractelement <vscale x 8 x i16> %a, i32 6
+  %el7 = extractelement <vscale x 8 x i16> %a, i32 7
+  %v0 = insertelement <8 x i16> undef, i16 %el7, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %el6, i32 1
+  %v2 = insertelement <8 x i16> %v1, i16 %el5, i32 2
+  %v3 = insertelement <8 x i16> %v2, i16 %el4, i32 3
+  ret <8 x i16> %v3
+}
+
+
+; == Shuffle comes from two input sources ==
+
+define <2 x i64> @reshuffle_v2i64_2x_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
+; CHECK-LABEL: reshuffle_v2i64_2x_nxv2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov x8, d1
+; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 2 x i64> %a, i32 0
+  %el1 = extractelement <vscale x 2 x i64> %b, i32 0
+  %v0 = insertelement <2 x i64> undef, i64 %el0, i32 0
+  %v1 = insertelement <2 x i64> %v0, i64 %el1, i32 1
+  ret <2 x i64> %v1
+}
+
+
+define <2 x i32> @reshuffle_v2i32_2x_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
+; CHECK-LABEL: reshuffle_v2i32_2x_nxv2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov w8, s1
+; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 2 x i32> %a, i32 0
+  %el1 = extractelement <vscale x 2 x i32> %b, i32 0
+  %v0 = insertelement <2 x i32> undef, i32 %el0, i32 0
+  %v1 = insertelement <2 x i32> %v0, i32 %el1, i32 1
+  ret <2 x i32> %v1
+}
+
+
+define <4 x i32> @reshuffle_v4i32_2x_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
+; CHECK-LABEL: reshuffle_v4i32_2x_nxv4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, v0.s[1]
+; CHECK-NEXT:    mov w9, v1.s[1]
+; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fmov w8, s1
+; CHECK-NEXT:    mov v0.s[2], w8
+; CHECK-NEXT:    mov v0.s[3], w9
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i32> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i32> %a, i32 1
+  %el2 = extractelement <vscale x 4 x i32> %b, i32 0
+  %el3 = extractelement <vscale x 4 x i32> %b, i32 1
+  %v0 = insertelement <4 x i32> undef, i32 %el0, i32 0
+  %v1 = insertelement <4 x i32> %v0, i32 %el1, i32 1
+  %v2 = insertelement <4 x i32> %v1, i32 %el2, i32 2
+  %v3 = insertelement <4 x i32> %v2, i32 %el3, i32 3
+  ret <4 x i32> %v3
+}
+
+
+define <4 x i16> @reshuffle_v4i16_2x_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
+; CHECK-LABEL: reshuffle_v4i16_2x_nxv8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[1]
+; CHECK-NEXT:    umov w9, v1.h[1]
+; CHECK-NEXT:    mov v0.h[1], w8
+; CHECK-NEXT:    fmov w8, s1
+; CHECK-NEXT:    mov v0.h[2], w8
+; CHECK-NEXT:    mov v0.h[3], w9
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i16> %b, i32 0
+  %el3 = extractelement <vscale x 8 x i16> %b, i32 1
+  %v0 = insertelement <4 x i16> undef, i16 %el0, i32 0
+  %v1 = insertelement <4 x i16> %v0, i16 %el1, i32 1
+  %v2 = insertelement <4 x i16> %v1, i16 %el2, i32 2
+  %v3 = insertelement <4 x i16> %v2, i16 %el3, i32 3
+  ret <4 x i16> %v3
+}
+
+
+define <8 x i16> @reshuffle_v8i16_2x_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
+; CHECK-LABEL: reshuffle_v8i16_2x_nxv8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[1]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    umov w10, v0.h[3]
+; CHECK-NEXT:    mov v0.h[1], w8
+; CHECK-NEXT:    fmov w8, s1
+; CHECK-NEXT:    mov v0.h[2], w9
+; CHECK-NEXT:    umov w9, v1.h[1]
+; CHECK-NEXT:    mov v0.h[3], w10
+; CHECK-NEXT:    mov v0.h[4], w8
+; CHECK-NEXT:    umov w8, v1.h[2]
+; CHECK-NEXT:    mov v0.h[5], w9
+; CHECK-NEXT:    umov w9, v1.h[3]
+; CHECK-NEXT:    mov v0.h[6], w8
+; CHECK-NEXT:    mov v0.h[7], w9
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i16> %a, i32 2
+  %el3 = extractelement <vscale x 8 x i16> %a, i32 3
+  %el4 = extractelement <vscale x 8 x i16> %b, i32 0
+  %el5 = extractelement <vscale x 8 x i16> %b, i32 1
+  %el6 = extractelement <vscale x 8 x i16> %b, i32 2
+  %el7 = extractelement <vscale x 8 x i16> %b, i32 3
+  %v0 = insertelement <8 x i16> undef, i16 %el0, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %el1, i32 1
+  %v2 = insertelement <8 x i16> %v1, i16 %el2, i32 2
+  %v3 = insertelement <8 x i16> %v2, i16 %el3, i32 3
+  %v4 = insertelement <8 x i16> %v3, i16 %el4, i32 4
+  %v5 = insertelement <8 x i16> %v4, i16 %el5, i32 5
+  %v6 = insertelement <8 x i16> %v5, i16 %el6, i32 6
+  %v7 = insertelement <8 x i16> %v6, i16 %el7, i32 7
+  ret <8 x i16> %v7
+}
+
+
+; == Shuffle comes from two input sources and result requires padding with undef ==
+
+
+define <4 x i32> @reshuffle_v4i32_2x_nxv4i32_undef1(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
+; CHECK-LABEL: reshuffle_v4i32_2x_nxv4i32_undef1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov w8, s1
+; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 4 x i32> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i32> %b, i32 0
+  %v0 = insertelement <4 x i32> undef, i32 %el0, i32 0
+  %v1 = insertelement <4 x i32> %v0, i32 %el1, i32 1
+  ret <4 x i32> %v1
+}
+
+
+define <8 x i16> @reshuffle_v8i16_2x_nxv8i16_undef1(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
+; CHECK-LABEL: reshuffle_v8i16_2x_nxv8i16_undef1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov w8, s1
+; CHECK-NEXT:    mov v0.h[1], w8
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %b, i32 0
+  %v0 = insertelement <8 x i16> undef, i16 %el0, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %el1, i32 1
+  ret <8 x i16> %v1
+}
+
+
+define <8 x i16> @reshuffle_v8i16_2x_nxv8i16_undef2(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
+; CHECK-LABEL: reshuffle_v8i16_2x_nxv8i16_undef2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[1]
+; CHECK-NEXT:    umov w9, v1.h[1]
+; CHECK-NEXT:    mov v0.h[1], w8
+; CHECK-NEXT:    fmov w8, s1
+; CHECK-NEXT:    mov v0.h[2], w8
+; CHECK-NEXT:    mov v0.h[3], w9
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %el0 = extractelement <vscale x 8 x i16> %a, i32 0
+  %el1 = extractelement <vscale x 8 x i16> %a, i32 1
+  %el2 = extractelement <vscale x 8 x i16> %b, i32 0
+  %el3 = extractelement <vscale x 8 x i16> %b, i32 1
+  %v0 = insertelement <8 x i16> undef, i16 %el0, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %el1, i32 1
+  %v2 = insertelement <8 x i16> %v1, i16 %el2, i32 2
+  %v3 = insertelement <8 x i16> %v2, i16 %el3, i32 3
+  ret <8 x i16> %v3
+}
+
+
+attributes #0 = { "target-features"="+sve" }