This is an archive of the discontinued LLVM Phabricator instance.

[NFC][SVE] Add more tests to CodeGen/AArch64/sve-fixed-length-reshuffle.ll
Needs ReviewPublic

Authored by david-arm on Feb 10 2022, 7:47 AM.

Details

Summary

This patch just adds more tests for cases where we extract elements
from a scalable vector and re-insert them into a new fixed-width vector:

CodeGen/AArch64/sve-fixed-length-reshuffle.ll

Some of these tests exercise the AArch64TargetLowering::ReconstructShuffle
code path.

Diff Detail

Event Timeline

david-arm created this revision.Feb 10 2022, 7:47 AM
david-arm requested review of this revision.Feb 10 2022, 7:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 10 2022, 7:47 AM
Matt added a subscriber: Matt.Mar 17 2022, 5:57 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 17 2022, 5:57 PM

The tests all seem valid, but it's a bit difficult to review this patch without knowing what it's really trying to test without really going through AArch64TargetLowering::ReconstructShuffle in detail. That function is quite big/complicated, so it's not trivial to spot whether anything is missing or redundant.
My main question is whether all the insert/extract-subvector tests need to test all the permutations of element type and subvector?

llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
35

Do we also want a test for extract elements 0 and 3, and inserting that into elements 0 and 1?

67

Do we need a define <2 x i1> @reshuffle_v2i1_nxv8i1(..) as well?